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first somehow working version for MIST

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This commit is contained in:
Eugene Lozovoy
2024-09-08 23:02:45 +03:00
parent a2692e3446
commit b575eed412
92 changed files with 1163 additions and 22527 deletions
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32
rtl/common/zmem.v
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@ -11,7 +11,7 @@
// | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
// zneg _/```\___/```\___/```\_______/```\___________/```\___________________/```\___________________________/```\________________
module zmem
module zmem
(
input clk,
input c0, c1, c2, c3,
@ -88,8 +88,8 @@ assign romwe_n = !(memwr && w0_we);
assign rompg = xtpage[0][4:0];
// RAM
assign zd_ena = !rom_n_ram && memrd;
wire ramreq = !rom_n_ram && ((memrd && !cache_hit_en) || (memwr && ramwr_en));
assign zd_ena = memrd;
wire ramreq = ((memrd && !cache_hit_en) || (memwr && ramwr_en));
// DOS signal control
assign dos_on = win0 && opfetch_s && (za[13:8]==6'h3D) && rom128 && !w0_map_n;
@ -98,11 +98,11 @@ assign dos_off = !win0 && opfetch_s && !vdos;
assign dos = (dos_on || dos_off) ^^ dos_r; // to make dos appear 1 clock earlier than dos_r
reg dos_r;
always @(posedge clk) begin
always @(posedge clk) begin
if (rst) dos_r <= 0;
else if (dos_off) dos_r <= 0;
else if (dos_on) dos_r <= 1;
end
end
// VDOS signal control
// vdos turn on/off is delayed till next opfetch due to INIR that writes right after iord cycle
@ -116,7 +116,7 @@ always @(posedge clk) begin
end
else if (vdos_on) pre_vdos <= 1;
else if (opfetch_s) vdos_r <= pre_vdos;
end
end
// address, data in and data out
assign cpu_wrbsel = za[0];
@ -172,7 +172,7 @@ reg pending_cpu_req;
always @(posedge clk) begin
if (rst) pending_cpu_req <= 0;
else if (cpu_next && c3) pending_cpu_req <= 0;
else if (dram_beg) pending_cpu_req <= 1;
else if (dram_beg) pending_cpu_req <= 1;
end
wire stall14_ini = dram_beg && (!cpu_next || opfetch || memrd); // no wait at all in write cycles, if next dram cycle is available
@ -183,20 +183,20 @@ always @(posedge clk) begin
if (rst) stall14_cycrd <= 0;
else if (cpu_next && c3) stall14_cycrd <= 0;
else if (dram_beg && (!c3 || !cpu_next) && (opfetch || memrd)) stall14_cycrd <= 1;
end
end
reg stall14_fin;
always @(posedge clk) begin
if (rst) stall14_fin <= 0;
else if (stall14_fin && ((opfetch && c1) || (memrd && c2))) stall14_fin <= 0;
else if (cpu_next && c3 && cpu_req && (opfetch || memrd)) stall14_fin <= 1;
end
end
// cache
// wire cache_hit = (ch_addr[7:2] != 6'b011100) && (cpu_hi_addr == cache_a) && cache_v; // debug for BM
wire cache_hit = (cpu_hi_addr == cache_a) && cache_v; // asynchronous signal meaning that address requested by CPU is cached and valid
wire cache_hit_en = cache_hit && cache_en[win];
wire cache_inv = cache_hit && !rom_n_ram && memwr_s && ramwr_en; // cache invalidation should be only performed if write happens to cached address
wire cache_inv = cache_hit && memwr_s && ramwr_en; // cache invalidation should be only performed if write happens to cached address
wire [12:0] cpu_hi_addr = {page[7:0], za[13:9]};
wire [12:0] cache_a;
@ -205,22 +205,22 @@ wire [7:0] ch_addr = cpu_addr[7:0];
wire [15:0] cache_d;
wire cache_v;
dpram #(.DATAWIDTH(16), .ADDRWIDTH(8)) cache_data
dpram #(.DATAWIDTH(16), .ADDRWIDTH(8)) cache_data
(
.clock(clk),
.address_a(ch_addr),
.address_a(ch_addr),
.data_a(cpu_rddata),
.wren_a(cpu_strobe),
.wren_a(cpu_strobe),
.address_b(ch_addr),
.q_b(cache_d)
);
dpram #(.DATAWIDTH(14), .ADDRWIDTH(8)) cache_addr
dpram #(.DATAWIDTH(14), .ADDRWIDTH(8)) cache_addr
(
.clock(clk),
.address_a(ch_addr),
.address_a(ch_addr),
.data_a({!cache_inv, cpu_hi_addr}),
.wren_a(cpu_strobe || cache_inv),
.wren_a(cpu_strobe || cache_inv),
.address_b(ch_addr),
.q_b({cache_v, cache_a})
);