diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..1b04712 --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "mist-modules"] + path = mist-modules + url = https://github.com/mist-devel/mist-modules diff --git a/TSConf.qsf b/TSConf.qsf index 56d2347..24642be 100644 --- a/TSConf.qsf +++ b/TSConf.qsf @@ -1,56 +1,310 @@ -# -------------------------------------------------------------------------- -# -# MiSTer project -# -# WARNING WARNING WARNING: -# Do not add files to project in Quartus IDE! It will mess this file! -# Add the files manually to files.qip file. -# -# -------------------------------------------------------------------------- - -set_global_assignment -name TOP_LEVEL_ENTITY sys_top -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - -set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Standard Edition" - -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" -set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON -set_global_assignment -name QII_AUTO_PACKED_REGISTERS NORMAL -set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON -set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MUX_RESTRUCTURE ON -set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON -set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON -set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON -set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON -set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON -set_global_assignment -name ECO_OPTIMIZE_TIMING ON -set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION ON -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON -set_global_assignment -name ALM_REGISTER_PACKING_EFFORT LOW -set_global_assignment -name SEED 1 - -source sys/sys.tcl -source sys/sys_analog.tcl -source files.qip +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.4 Build 182 03/12/2014 SJ Full Version +# Date created = 01:27:30 May 03, 2016 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# zxspectrum_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:40:24 MAY 17, 2014" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_46 -to UART_TX +set_location_assignment PIN_31 -to UART_RX +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PIN_49 -to SDRAM_A[0] +set_location_assignment PIN_44 -to SDRAM_A[1] +set_location_assignment PIN_42 -to SDRAM_A[2] +set_location_assignment PIN_39 -to SDRAM_A[3] +set_location_assignment PIN_4 -to SDRAM_A[4] +set_location_assignment PIN_6 -to SDRAM_A[5] +set_location_assignment PIN_8 -to SDRAM_A[6] +set_location_assignment PIN_10 -to SDRAM_A[7] +set_location_assignment PIN_11 -to SDRAM_A[8] +set_location_assignment PIN_28 -to SDRAM_A[9] +set_location_assignment PIN_50 -to SDRAM_A[10] +set_location_assignment PIN_30 -to SDRAM_A[11] +set_location_assignment PIN_32 -to SDRAM_A[12] +set_location_assignment PIN_83 -to SDRAM_DQ[0] +set_location_assignment PIN_79 -to SDRAM_DQ[1] +set_location_assignment PIN_77 -to SDRAM_DQ[2] +set_location_assignment PIN_76 -to SDRAM_DQ[3] +set_location_assignment PIN_72 -to SDRAM_DQ[4] +set_location_assignment PIN_71 -to SDRAM_DQ[5] +set_location_assignment PIN_69 -to SDRAM_DQ[6] +set_location_assignment PIN_68 -to SDRAM_DQ[7] +set_location_assignment PIN_86 -to SDRAM_DQ[8] +set_location_assignment PIN_87 -to SDRAM_DQ[9] +set_location_assignment PIN_98 -to SDRAM_DQ[10] +set_location_assignment PIN_99 -to SDRAM_DQ[11] +set_location_assignment PIN_100 -to SDRAM_DQ[12] +set_location_assignment PIN_101 -to SDRAM_DQ[13] +set_location_assignment PIN_103 -to SDRAM_DQ[14] +set_location_assignment PIN_104 -to SDRAM_DQ[15] +set_location_assignment PIN_58 -to SDRAM_BA[0] +set_location_assignment PIN_51 -to SDRAM_BA[1] +set_location_assignment PIN_85 -to SDRAM_DQMH +set_location_assignment PIN_67 -to SDRAM_DQML +set_location_assignment PIN_60 -to SDRAM_nRAS +set_location_assignment PIN_64 -to SDRAM_nCAS +set_location_assignment PIN_66 -to SDRAM_nWE +set_location_assignment PIN_59 -to SDRAM_nCS +set_location_assignment PIN_33 -to SDRAM_CKE +set_location_assignment PIN_43 -to SDRAM_CLK +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY TSConf_top +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON +set_global_assignment -name SAVE_DISK_SPACE OFF + +# Fitter Assignments +# ================== +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# SignalTap II Assignments +# ======================== +set_global_assignment -name ENABLE_SIGNALTAP ON + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ------------------------ +# start ENTITY(zxspectrum) + +# Pin & Location Assignments +# ========================== +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*] + +# Fitter Assignments +# ================== +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[14] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[15] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to UART_TX +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CONF_DATA0 + +# start DESIGN_PARTITION(Top) +# --------------------------- + +# Incremental Compilation Assignments +# =================================== +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + +# end DESIGN_PARTITION(Top) +# ------------------------- + +# end ENTITY(zxspectrum) +# ---------------------- +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:build_id_verilog.tcl" +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS" + + +set_global_assignment -name SEED 0 +set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp +set_global_assignment -name QIP_FILE pll.qip +set_global_assignment -name QIP_FILE files.qip +set_global_assignment -name QIP_FILE "mist-modules/mist.qip" + + +set_location_assignment PIN_90 -to SPI_SS4 +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON +set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON +set_global_assignment -name ECO_OPTIMIZE_TIMING ON +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT LOW +set_global_assignment -name SEED 1 + +source sys/sys.tcl +source sys/sys_analog.tcl +source files.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/TSConf.sdc b/TSConf.sdc index 6493f2d..92b3961 100644 --- a/TSConf.sdc +++ b/TSConf.sdc @@ -1,13 +1,46 @@ -derive_pll_clocks +# Clock constraints + +create_clock -name "CLOCK_27" -period 37.037 [get_ports {CLOCK_27}] +create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] + +# Automatically constrain PLL and other generated clocks +derive_pll_clocks -create_base_clocks + +# Automatically calculate clock uncertainty to jitter and other effects. derive_clock_uncertainty -set_multicycle_path -to {emu|tsconf|U16|*} -setup 2 -set_multicycle_path -to {emu|tsconf|U16|*} -hold 1 +# Clock groups +set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] -set_multicycle_path -from {emu|tsconf|CPU|*} -setup 2 -set_multicycle_path -from {emu|tsconf|CPU|*} -hold 1 -set_multicycle_path -to {emu|tsconf|CPU|*} -setup 2 -set_multicycle_path -to {emu|tsconf|CPU|*} -hold 1 +# SDRAM delays +set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports SDRAM_CLK] -max 6.4 [get_ports SDRAM_DQ[*]] +set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports SDRAM_CLK] -min 3.2 [get_ports SDRAM_DQ[*]] -set_multicycle_path -to {emu|tsconf|U15|*} -setup 2 -set_multicycle_path -to {emu|tsconf|U15|*} -hold 1 +set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports SDRAM_CLK] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] +set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports SDRAM_CLK] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] + +#SDRAM_CLK to internal memory clock +#set_multicycle_path -from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 2 + +# Some relaxed constrain to the VGA pins. The signals should arrive together, the delay is not really important. +set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0 [get_ports {VGA_*}] +set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -min -5 [get_ports {VGA_*}] +set_multicycle_path -to [get_ports {VGA_*}] -setup 5 +set_multicycle_path -to [get_ports {VGA_*}] -hold 4 + +set_false_path -to {dac:*} +set_false_path -to [get_ports {AUDIO_L}] +set_false_path -to [get_ports {AUDIO_R}] +set_false_path -to [get_ports {LED}] +set_false_path -from [get_ports {UART_RX}] + +set_multicycle_path -to {tsconf|U16|*} -setup 2 +set_multicycle_path -to {tsconf|U16|*} -hold 1 + +set_multicycle_path -from {tsconf|CPU|*} -setup 2 +set_multicycle_path -from {tsconf|CPU|*} -hold 1 +set_multicycle_path -to {tsconf|CPU|*} -setup 2 +set_multicycle_path -to {tsconf|CPU|*} -hold 1 + +set_multicycle_path -to {tsconf|U15|*} -setup 2 +set_multicycle_path -to {tsconf|U15|*} -hold 1 diff --git a/TSConf.sv b/TSConf.sv index c909ea3..d1aaaec 100644 --- a/TSConf.sv +++ b/TSConf.sv @@ -2,7 +2,7 @@ // TSConf for MiSTer // // Port to MiSTer -// Copyright (C) 2017-2019 Sorgelig +// Copyright (C) 2017-2019 Sorgelig // // This program is free software; you can redistribute it and/or modify it // under the terms of the GNU General Public License as published by the Free @@ -19,203 +19,57 @@ // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. //============================================================================ -module emu +module TSConf_top ( - //Master input clock - input CLK_50M, + input CLOCK_27, - //Async reset from top-level module. - //Can be used as initial reset. - input RESET, - - //Must be passed to hps_io module - inout [48:0] HPS_BUS, - - //Base video clock. Usually equals to CLK_SYS. - output CLK_VIDEO, - - //Multiple resolutions are supported using different CE_PIXEL rates. - //Must be based on CLK_VIDEO - output CE_PIXEL, - - //Video aspect ratio for HDMI. Most retro systems have ratio 4:3. - //if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio. - output [12:0] VIDEO_ARX, - output [12:0] VIDEO_ARY, - - output [7:0] VGA_R, - output [7:0] VGA_G, - output [7:0] VGA_B, + output LED, + output [VGA_BITS-1:0] VGA_R, + output [VGA_BITS-1:0] VGA_G, + output [VGA_BITS-1:0] VGA_B, output VGA_HS, output VGA_VS, - output VGA_DE, // = ~(VBlank | HBlank) - output VGA_F1, - output [1:0] VGA_SL, - output VGA_SCALER, // Force VGA scaler - output VGA_DISABLE, // analog out is off - input [11:0] HDMI_WIDTH, - input [11:0] HDMI_HEIGHT, - output HDMI_FREEZE, + input SPI_SCK, + inout SPI_DO, + input SPI_DI, + input SPI_SS2, // data_io + input SPI_SS3, // OSD + input CONF_DATA0, // SPI_SS for user_io -`ifdef MISTER_FB - // Use framebuffer in DDRAM - // FB_FORMAT: - // [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp - // [3] : 0=16bits 565 1=16bits 1555 - // [4] : 0=RGB 1=BGR (for 16/24/32 modes) - // - // FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes) - output FB_EN, - output [4:0] FB_FORMAT, - output [11:0] FB_WIDTH, - output [11:0] FB_HEIGHT, - output [31:0] FB_BASE, - output [13:0] FB_STRIDE, - input FB_VBL, - input FB_LL, - output FB_FORCE_BLANK, + input SPI_SS4, -`ifdef MISTER_FB_PALETTE - // Palette control for 8bit modes. - // Ignored for other video modes. - output FB_PAL_CLK, - output [7:0] FB_PAL_ADDR, - output [23:0] FB_PAL_DOUT, - input [23:0] FB_PAL_DIN, - output FB_PAL_WR, -`endif -`endif - - output LED_USER, // 1 - ON, 0 - OFF. - - // b[1]: 0 - LED status is system status OR'd with b[0] - // 1 - LED status is controled solely by b[0] - // hint: supply 2'b00 to let the system control the LED. - output [1:0] LED_POWER, - output [1:0] LED_DISK, - - // I/O board button press simulation (active high) - // b[1]: user button - // b[0]: osd button - output [1:0] BUTTONS, - - input CLK_AUDIO, // 24.576 MHz - output [15:0] AUDIO_L, - output [15:0] AUDIO_R, - output AUDIO_S, // 1 - signed audio samples, 0 - unsigned - output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono) - - //ADC - inout [3:0] ADC_BUS, - - //SD-SPI - output SD_SCK, - output SD_MOSI, - input SD_MISO, - output SD_CS, - input SD_CD, - - //High latency DDR3 RAM interface - //Use for non-critical time purposes - output DDRAM_CLK, - input DDRAM_BUSY, - output [7:0] DDRAM_BURSTCNT, - output [28:0] DDRAM_ADDR, - input [63:0] DDRAM_DOUT, - input DDRAM_DOUT_READY, - output DDRAM_RD, - output [63:0] DDRAM_DIN, - output [7:0] DDRAM_BE, - output DDRAM_WE, - - //SDRAM interface with lower latency - output SDRAM_CLK, - output SDRAM_CKE, output [12:0] SDRAM_A, - output [1:0] SDRAM_BA, inout [15:0] SDRAM_DQ, output SDRAM_DQML, output SDRAM_DQMH, - output SDRAM_nCS, + output SDRAM_nWE, output SDRAM_nCAS, output SDRAM_nRAS, - output SDRAM_nWE, + output SDRAM_nCS, + output [1:0] SDRAM_BA, + output SDRAM_CLK, + output SDRAM_CKE, -`ifdef MISTER_DUAL_SDRAM - //Secondary SDRAM - //Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0 - input SDRAM2_EN, - output SDRAM2_CLK, - output [12:0] SDRAM2_A, - output [1:0] SDRAM2_BA, - inout [15:0] SDRAM2_DQ, - output SDRAM2_nCS, - output SDRAM2_nCAS, - output SDRAM2_nRAS, - output SDRAM2_nWE, -`endif + output AUDIO_L, + output AUDIO_R, - input UART_CTS, - output UART_RTS, - input UART_RXD, - output UART_TXD, - output UART_DTR, - input UART_DSR, - - // Open-drain User port. - // 0 - D+/RX - // 1 - D-/TX - // 2..6 - USR2..USR6 - // Set USER_OUT to 1 to read from USER_IN. - input [6:0] USER_IN, - output [6:0] USER_OUT, - - input OSD_STATUS -); - -assign ADC_BUS = 'Z; -assign USER_OUT = '1; -assign VGA_F1 = 0; -assign {UART_RTS, UART_TXD, UART_DTR} = 0; - -assign LED_USER = (vsd_sel & sd_act) | ioctl_download; -assign LED_DISK = {1'b1, ~vsd_sel & sd_act}; -assign LED_POWER = 0; -assign BUTTONS = 0; -assign VGA_SCALER= 0; -assign VGA_DISABLE = 0; -assign HDMI_FREEZE = 0; - -wire [1:0] ar = status[33:32]; -wire vcrop_en = status[34]; -reg en270p; -always @(posedge CLK_VIDEO) begin - en270p <= ((HDMI_WIDTH == 1920) && (HDMI_HEIGHT == 1080) && !forced_scandoubler && !scale); -end - -wire vga_de; -video_freak video_freak -( - .*, - .VGA_DE_IN(vga_de), - .ARX((!ar) ? 12'd4 : (ar - 1'd1)), - .ARY((!ar) ? 12'd3 : 12'd0), - .CROP_SIZE((en270p & vcrop_en) ? 10'd270 : 10'd0), - .CROP_OFF(0), - .SCALE(status[36:35]) + input UART_RX, + output UART_TX ); -`include "build_id.v" +localparam VGA_BITS = 6; +localparam bit BIG_OSD = 1; + + +assign LED = ~ioctl_download & UART_TX & UART_RX; +assign UART_TX = 1'b1; + + +`include "build_id.v" localparam CONF_STR = { "TSConf;;", - "SC0,VHD,Mount virtual SD;", - "-;", - "o01,Aspect ratio,Original,Full Screen,[ARC1],[ARC2];", - "O12,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", - "-;", - "d0o2,Vertical Crop,Disabled,270p(5x);", - "o34,Scale,Normal,V-Integer,Narrower HV-Integer,Wider HV-Integer;", + "O12,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;", "-;", "O34,Stereo mix,None,25%,50%,100%;", "OST,General Sound,512KB,1MB,2MB;", @@ -232,8 +86,7 @@ localparam CONF_STR = { "OGI,Shift+F11 Reset,ROM,boot.$C,sys.rom;", "OJK, bank,Basic 128,SYS,TR-DOS,Basic 48;", "-;", - "R0,Reset and apply settings;", - "J,Fire 1,Fire 2;", + "T0,Reset and apply settings;", "V,v",`BUILD_DATE }; @@ -255,12 +108,13 @@ assign CMOSCfg[27:25]= status[27:25] + 1'd1; //////////////////// CLOCKS /////////////////// wire clk_sys; +wire locked; pll pll ( - .refclk(CLK_50M), - .outclk_0(clk_sys), - .outclk_1(CLK_VIDEO) + .inclk0(CLOCK_27), + .c0(clk_sys), + .locked(locked) ); reg ce_28m; @@ -273,76 +127,165 @@ always @(negedge clk_sys) begin end -////////////////// HPS I/O /////////////////// -wire [5:0] joy_0; -wire [5:0] joy_1; -wire [15:0] joya_0; -wire [15:0] joya_1; +////////////////// MIST ARM I/O /////////////////// +wire [7:0] joystick_0; +wire [7:0] joystick_1; + wire [1:0] buttons; +wire [1:0] switches; +wire scandoubler_disable; +wire ypbpr; +wire no_csync; wire [63:0] status; -wire [24:0] ps2_mouse; -wire [10:0] ps2_key; -wire forced_scandoubler; -wire [21:0] gamma_bus; +wire [63:0] rtc; + +wire sd_busy_mmc; +wire sd_rd_mmc; +wire sd_wr_mmc; +wire [31:0] sd_lba_mmc; +wire [7:0] sd_buff_din_mmc; + +wire [31:0] sd_lba = sd_lba_mmc; +wire [1:0] sd_rd = { 1'b0, sd_rd_mmc }; +wire [1:0] sd_wr = { 1'b0, sd_wr_mmc }; -wire [31:0] sd_lba; -wire sd_rd; -wire sd_wr; wire sd_ack; wire [8:0] sd_buff_addr; wire [7:0] sd_buff_dout; -wire [7:0] sd_buff_din; +wire [7:0] sd_buff_din = sd_buff_din_mmc; wire sd_buff_wr; -wire img_mounted; -wire img_readonly; +wire [1:0] img_mounted; wire [63:0] img_size; -wire [64:0] RTC; + +wire sd_ack_conf; +wire sd_conf; +wire sd_sdhc; + +wire key_strobe; +wire key_pressed; +wire key_extended; +wire [7:0] key_code; + +wire [8:0] mouse_x; +wire [8:0] mouse_y; +wire [7:0] mouse_flags; +wire mouse_strobe; + +wire [24:0] ps2_mouse = { mouse_strobe_level, mouse_y[7:0], mouse_x[7:0], mouse_flags }; +reg mouse_strobe_level; +always @(posedge clk_sys) if (mouse_strobe) mouse_strobe_level <= ~mouse_strobe_level; + +user_io #(.STRLEN($size(CONF_STR)>>3), .SD_IMAGES(2), .FEATURES(32'h0 | (BIG_OSD << 13))) user_io +( + .clk_sys(clk_sys), + .clk_sd(clk_sys), + .conf_str(CONF_STR), + + .SPI_CLK(SPI_SCK), + .SPI_SS_IO(CONF_DATA0), + .SPI_MOSI(SPI_DI), + .SPI_MISO(SPI_DO), + + .img_mounted(img_mounted), + .img_size(img_size), + .sd_conf(sd_conf), + .sd_ack_conf(sd_ack_conf), + .sd_sdhc(sd_sdhc), + .sd_lba(sd_lba), + .sd_rd(sd_rd), + .sd_wr(sd_wr), + .sd_ack(sd_ack), + .sd_buff_addr(sd_buff_addr), + .sd_din(sd_buff_din), + .sd_dout(sd_buff_dout), + .sd_dout_strobe(sd_buff_wr), + + .key_strobe(key_strobe), + .key_code(key_code), + .key_pressed(key_pressed), + .key_extended(key_extended), + + .mouse_x(mouse_x), + .mouse_y(mouse_y), + .mouse_flags(mouse_flags), + .mouse_strobe(mouse_strobe), + + .joystick_0(joystick_0), + .joystick_1(joystick_1), + + .buttons(buttons), + .status(status), + .scandoubler_disable(scandoubler_disable), + .ypbpr(ypbpr), + .no_csync(no_csync), + .rtc(rtc) +); wire ioctl_wr; wire [24:0] ioctl_addr; wire [7:0] ioctl_dout; wire ioctl_download; -wire [7:0] ioctl_index; +wire [5:0] ioctl_index; +wire [1:0] ioctl_ext_index; -hps_io #(.CONF_STR(CONF_STR)) hps_io +data_io data_io ( .clk_sys(clk_sys), - .HPS_BUS(HPS_BUS), - .joystick_0(joy_0), - .joystick_1(joy_1), - .joystick_l_analog_0(joya_0), - .joystick_l_analog_1(joya_1), - - .buttons(buttons), - .status(status), - .status_menumask({en270p}), - .forced_scandoubler(forced_scandoubler), - .gamma_bus(gamma_bus), - - .RTC(RTC), - - .ps2_mouse(ps2_mouse), - .ps2_key(ps2_key), - - .sd_lba('{sd_lba}), - .sd_rd(sd_rd), - .sd_wr(sd_wr), - .sd_ack(sd_ack), - .sd_buff_addr(sd_buff_addr), - .sd_buff_dout(sd_buff_dout), - .sd_buff_din('{sd_buff_din}), - .sd_buff_wr(sd_buff_wr), - .img_mounted(img_mounted), - .img_readonly(img_readonly), - .img_size(img_size), + .SPI_SCK(SPI_SCK), + .SPI_SS2(SPI_SS2), + .SPI_DI(SPI_DI), + .SPI_DO(SPI_DO), + .clkref_n(1'b0), .ioctl_wr(ioctl_wr), .ioctl_addr(ioctl_addr), .ioctl_dout(ioctl_dout), .ioctl_download(ioctl_download), - .ioctl_index(ioctl_index) + .ioctl_index({ioctl_ext_index, ioctl_index}) +); + + +reg init_reset = 1; +reg old_download; +always @(posedge clk_sys) begin + old_download <= ioctl_download; + if(old_download & ~ioctl_download) init_reset <= 0; +end + + +////////////////// SD /////////////////// +wire sdss; +wire sdclk; +wire sdmiso; +wire sdmosi; +sd_card sd_card +( + .clk_sys(clk_sys), + .img_mounted(img_mounted[0]), //first slot for SD-card emulation + .img_size(img_size), + .sd_busy(sd_busy_mmc), + .sd_rd(sd_rd_mmc), + .sd_wr(sd_wr_mmc), + .sd_lba(sd_lba_mmc), + + .sd_buff_din(sd_buff_din_mmc), + .sd_buff_dout(sd_buff_dout), + .sd_buff_wr(sd_buff_wr), + .sd_buff_addr(sd_buff_addr), + + .sd_ack(sd_ack), + .sd_ack_conf(sd_ack_conf), + + .allow_sdhc(1), + .sd_sdhc(sd_sdhc), + .sd_conf(sd_conf), + + .sd_cs(sdss), + .sd_sck(sdclk), + .sd_sdi(sdmosi), + .sd_sdo(sdmiso) ); @@ -351,8 +294,8 @@ wire [7:0] R,G,B; wire HBlank,VBlank; wire VS, HS; wire ce_vid; - -wire reset; +wire [15:0] SOUND_L; +wire [15:0] SOUND_R; tsconf tsconf ( @@ -390,29 +333,27 @@ tsconf tsconf .GS_DO(gs_mem_dout | gs_mem_mask), .GS_RD(gs_mem_rd), .GS_WR(gs_mem_wr), - .GS_WAIT(~gs_mem_ready), - .SOUND_L(AUDIO_L), - .SOUND_R(AUDIO_R), + .GS_WAIT(~gs_mem_ready), + .SOUND_L(SOUND_L), + .SOUND_R(SOUND_R), - .COLD_RESET(RESET | status[0] | reset_img), + .COLD_RESET(init_reset | status[0]), .WARM_RESET(buttons[1]), - .RESET_OUT(reset), - .RTC(RTC), + .RTC(rtc), .OUT0(status[30]), .CMOSCfg(CMOSCfg), - .PS2_KEY(ps2_key), + .PS2_KEY({key_strobe,key_pressed,key_extended,key_code}), .PS2_MOUSE(ps2_mouse), - .joystick(joy_0[5:0] | joy_1[5:0]), + .joystick(joystick_0[5:0] | joystick_1[5:0]), + .loader_act(ioctl_download), .loader_addr(ioctl_addr[15:0]), .loader_data(ioctl_dout), .loader_wr(ioctl_wr && ioctl_download && !ioctl_index && !ioctl_addr[24:16]) ); -assign DDRAM_CLK = clk_sys; - wire [20:0] gs_mem_addr; wire [7:0] gs_mem_dout; wire [7:0] gs_mem_din; @@ -430,103 +371,82 @@ always_comb begin endcase end -ddram ddram -( - .*, - .addr(gs_mem_addr), - .dout(gs_mem_dout), - .din(gs_mem_din), - .we(gs_mem_wr), - .rd(gs_mem_rd), - .ready(gs_mem_ready) -); +// ddram ddram +// ( +// .*, +// .addr(gs_mem_addr), +// .dout(gs_mem_dout), +// .din(gs_mem_din), +// .we(gs_mem_wr), +// .rd(gs_mem_rd), +// .ready(gs_mem_ready) +// ); -assign AUDIO_S = 1; -assign AUDIO_MIX = status[4:3]; - -reg ce_pix; -always @(posedge CLK_VIDEO) begin - reg old_ce; - - old_ce <= ce_vid; - ce_pix <= ~old_ce & ce_vid; -end reg VSync, HSync; -always @(posedge CLK_VIDEO) begin +always @(posedge clk_sys) begin HSync <= HS; if(~HSync & HS) VSync <= VS; end -wire [1:0] scale = status[2:1]; -assign VGA_SL = {scale == 3, scale == 2}; +////////////////// VIDEO /////////////////// +mist_video #(.COLOR_DEPTH(8), .SD_HCNT_WIDTH(11), .OUT_COLOR_DEPTH(VGA_BITS), .BIG_OSD(BIG_OSD)) mist_video ( + .clk_sys ( clk_sys ), -video_mixer #(.GAMMA(1)) video_mixer -( - .*, - .scandoubler(scale || forced_scandoubler), - .hq2x(scale==1), - .freeze_sync(), - .VGA_DE(vga_de) + // OSD SPI interface + .SPI_SCK ( SPI_SCK ), + .SPI_SS3 ( SPI_SS3 ), + .SPI_DI ( SPI_DI ), + + // scanlines (00-none 01-25% 10-50% 11-75%) + // .scanlines ( status[2:1] ), + + // non-scandoubled pixel clock divider 0 - clk_sys/4, 1 - clk_sys/2 + .ce_divider ( 3'd2 ), + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + .scandoubler_disable ( scandoubler_disable ), + // disable csync without scandoubler + .no_csync ( no_csync ), + // YPbPr always uses composite sync + .ypbpr ( ypbpr ), + // Rotate OSD [0] - rotate [1] - left or right + .rotate ( 2'b00 ), + // composite-like blending + .blend ( 1'b0 ), + + // video in + .R ( R ), + .G ( G ), + .B ( B ), + + .HSync ( HSync ), + .VSync ( VSync ), + + // MiST video output signals + .VGA_R ( VGA_R ), + .VGA_G ( VGA_G ), + .VGA_B ( VGA_B ), + .VGA_VS ( VGA_VS ), + .VGA_HS ( VGA_HS ) ); -////////////////// SD /////////////////// -wire sdclk; -wire sdmosi; -wire sdmiso = vsd_sel ? vsdmiso : SD_MISO; -wire sdss; +////////////////// SOUND /////////////////// +// dac #(.C_bits(16)) dac_l ( +// .clk_i(clk_sys), +// .res_n_i(~init_reset), +// .dac_i(SOUND_L), +// .dac_o(AUDIO_L) +// ); -reg reset_img; -reg vsd_sel = 0; -always @(posedge clk_sys) begin - integer to = 0; - - if(to) to <= to - 1; - else reset_img <= 0; +// dac #(.C_bits(16)) dac_r ( +// .clk_i(clk_sys), +// .res_n_i(~init_reset), +// .dac_i(SOUND_R), +// .dac_o(AUDIO_R) +// ); - if(img_mounted) begin - vsd_sel <= |img_size; - reset_img <= 1; - to <= 10000000; - end -end - -wire vsdmiso; -sd_card sd_card -( - .*, - .clk_spi(clk_sys), - - .sdhc(1), - - .sck(sdclk), - .ss(~vsd_sel | sdss), - .mosi(sdmosi), - .miso(vsdmiso) -); - -assign SD_CS = vsd_sel | sdss; -assign SD_SCK = sdclk & ~SD_CS; -assign SD_MOSI = sdmosi & ~SD_CS; - -reg sd_act; - -always @(posedge clk_sys) begin - reg old_mosi, old_miso; - integer timeout = 0; - - old_mosi <= sdmosi; - old_miso <= sdmiso; - - sd_act <= 0; - if(timeout < 1000000) begin - timeout <= timeout + 1; - sd_act <= 1; - end - - if((old_mosi ^ sdmosi) || (old_miso ^ sdmiso)) timeout <= 0; -end endmodule diff --git a/build_id_verilog.tcl b/build_id_verilog.tcl new file mode 100644 index 0000000..7340497 --- /dev/null +++ b/build_id_verilog.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/files.qip b/files.qip index 184e6a0..075047b 100644 --- a/files.qip +++ b/files.qip @@ -2,7 +2,6 @@ set_global_assignment -name QIP_FILE rtl/T80/T80.qip set_global_assignment -name VERILOG_FILE rtl/memory/dma.v set_global_assignment -name VERILOG_FILE rtl/memory/arbiter.v set_global_assignment -name VERILOG_FILE rtl/memory/sdram.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/memory/ddram.sv set_global_assignment -name VERILOG_FILE rtl/memory/dpram.v set_global_assignment -name VERILOG_FILE rtl/common/zsignals.v set_global_assignment -name VERILOG_FILE rtl/common/zports.v diff --git a/mist-modules b/mist-modules new file mode 160000 index 0000000..9d9bbb1 --- /dev/null +++ b/mist-modules @@ -0,0 +1 @@ +Subproject commit 9d9bbb1689db0661c12256f480960f1e5edd6507 diff --git a/pll.qip b/pll.qip new file mode 100644 index 0000000..afd958b --- /dev/null +++ b/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/pll.v b/pll.v new file mode 100644 index 0000000..6009523 --- /dev/null +++ b/pll.v @@ -0,0 +1,307 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + inclk0, + c0, + locked); + + input inclk0; + output c0; + output locked; + + wire [4:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire5 = 1'h0; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire locked = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .inclk (sub_wire4), + .clk (sub_wire0), + .locked (sub_wire2), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 9, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 28, + altpll_component.clk0_phase_shift = "0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NO_COMPENSATION", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "ON", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "84.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "10000" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "0" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "84.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "28" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/releases/TSConf_20180816.rbf b/releases/TSConf_20180816.rbf deleted file mode 100644 index 2a4fa65..0000000 Binary files a/releases/TSConf_20180816.rbf and /dev/null differ diff --git a/releases/TSConf_20180817.rbf b/releases/TSConf_20180817.rbf deleted file mode 100644 index 0c2a00f..0000000 Binary files a/releases/TSConf_20180817.rbf and /dev/null differ diff --git a/releases/TSConf_20180820.rbf b/releases/TSConf_20180820.rbf deleted file mode 100644 index 50045b7..0000000 Binary files a/releases/TSConf_20180820.rbf and /dev/null differ diff --git a/releases/TSConf_20180824.rbf b/releases/TSConf_20180824.rbf deleted file mode 100644 index 2b1d927..0000000 Binary files a/releases/TSConf_20180824.rbf and /dev/null differ diff --git a/releases/TSConf_20180901.rbf b/releases/TSConf_20180901.rbf deleted file mode 100644 index 49f9f1c..0000000 Binary files a/releases/TSConf_20180901.rbf and /dev/null differ diff --git a/releases/TSConf_20190307.rbf b/releases/TSConf_20190307.rbf deleted file mode 100644 index a4622b7..0000000 Binary files a/releases/TSConf_20190307.rbf and /dev/null differ diff --git a/releases/TSConf_20190712.rbf b/releases/TSConf_20190712.rbf deleted file mode 100644 index b88fc52..0000000 Binary files a/releases/TSConf_20190712.rbf and /dev/null differ diff --git a/releases/TSConf_20190928.rbf b/releases/TSConf_20190928.rbf deleted file mode 100644 index cef3da8..0000000 Binary files a/releases/TSConf_20190928.rbf and /dev/null differ diff --git a/releases/TSConf_20200512.rbf b/releases/TSConf_20200512.rbf deleted file mode 100644 index 9bf91b5..0000000 Binary files a/releases/TSConf_20200512.rbf and /dev/null differ diff --git a/releases/TSConf_20210206.rbf b/releases/TSConf_20210206.rbf deleted file mode 100644 index b1039e5..0000000 Binary files a/releases/TSConf_20210206.rbf and /dev/null differ diff --git a/releases/TSConf_20210302.rbf b/releases/TSConf_20210302.rbf deleted file mode 100644 index 5545ecf..0000000 Binary files a/releases/TSConf_20210302.rbf and /dev/null differ diff --git a/releases/TSConf_20220216.rbf b/releases/TSConf_20220216.rbf deleted file mode 100644 index 06f3419..0000000 Binary files a/releases/TSConf_20220216.rbf and /dev/null differ diff --git a/releases/TSConf_20230302.rbf b/releases/TSConf_20230302.rbf deleted file mode 100644 index 323bc6e..0000000 Binary files a/releases/TSConf_20230302.rbf and /dev/null differ diff --git a/releases/TSConf_20231208.rbf b/releases/TSConf_20231208.rbf deleted file mode 100644 index cf243b1..0000000 Binary files a/releases/TSConf_20231208.rbf and /dev/null differ diff --git a/rtl/common/zmem.v b/rtl/common/zmem.v index ce58656..5e25b63 100644 --- a/rtl/common/zmem.v +++ b/rtl/common/zmem.v @@ -11,7 +11,7 @@ // | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | // zneg _/```\___/```\___/```\_______/```\___________/```\___________________/```\___________________________/```\________________ -module zmem +module zmem ( input clk, input c0, c1, c2, c3, @@ -88,8 +88,8 @@ assign romwe_n = !(memwr && w0_we); assign rompg = xtpage[0][4:0]; // RAM -assign zd_ena = !rom_n_ram && memrd; -wire ramreq = !rom_n_ram && ((memrd && !cache_hit_en) || (memwr && ramwr_en)); +assign zd_ena = memrd; +wire ramreq = ((memrd && !cache_hit_en) || (memwr && ramwr_en)); // DOS signal control assign dos_on = win0 && opfetch_s && (za[13:8]==6'h3D) && rom128 && !w0_map_n; @@ -98,11 +98,11 @@ assign dos_off = !win0 && opfetch_s && !vdos; assign dos = (dos_on || dos_off) ^^ dos_r; // to make dos appear 1 clock earlier than dos_r reg dos_r; -always @(posedge clk) begin +always @(posedge clk) begin if (rst) dos_r <= 0; else if (dos_off) dos_r <= 0; else if (dos_on) dos_r <= 1; -end +end // VDOS signal control // vdos turn on/off is delayed till next opfetch due to INIR that writes right after iord cycle @@ -116,7 +116,7 @@ always @(posedge clk) begin end else if (vdos_on) pre_vdos <= 1; else if (opfetch_s) vdos_r <= pre_vdos; -end +end // address, data in and data out assign cpu_wrbsel = za[0]; @@ -172,7 +172,7 @@ reg pending_cpu_req; always @(posedge clk) begin if (rst) pending_cpu_req <= 0; else if (cpu_next && c3) pending_cpu_req <= 0; - else if (dram_beg) pending_cpu_req <= 1; + else if (dram_beg) pending_cpu_req <= 1; end wire stall14_ini = dram_beg && (!cpu_next || opfetch || memrd); // no wait at all in write cycles, if next dram cycle is available @@ -183,20 +183,20 @@ always @(posedge clk) begin if (rst) stall14_cycrd <= 0; else if (cpu_next && c3) stall14_cycrd <= 0; else if (dram_beg && (!c3 || !cpu_next) && (opfetch || memrd)) stall14_cycrd <= 1; -end +end reg stall14_fin; always @(posedge clk) begin if (rst) stall14_fin <= 0; else if (stall14_fin && ((opfetch && c1) || (memrd && c2))) stall14_fin <= 0; else if (cpu_next && c3 && cpu_req && (opfetch || memrd)) stall14_fin <= 1; -end +end // cache // wire cache_hit = (ch_addr[7:2] != 6'b011100) && (cpu_hi_addr == cache_a) && cache_v; // debug for BM wire cache_hit = (cpu_hi_addr == cache_a) && cache_v; // asynchronous signal meaning that address requested by CPU is cached and valid wire cache_hit_en = cache_hit && cache_en[win]; -wire cache_inv = cache_hit && !rom_n_ram && memwr_s && ramwr_en; // cache invalidation should be only performed if write happens to cached address +wire cache_inv = cache_hit && memwr_s && ramwr_en; // cache invalidation should be only performed if write happens to cached address wire [12:0] cpu_hi_addr = {page[7:0], za[13:9]}; wire [12:0] cache_a; @@ -205,22 +205,22 @@ wire [7:0] ch_addr = cpu_addr[7:0]; wire [15:0] cache_d; wire cache_v; -dpram #(.DATAWIDTH(16), .ADDRWIDTH(8)) cache_data +dpram #(.DATAWIDTH(16), .ADDRWIDTH(8)) cache_data ( .clock(clk), - .address_a(ch_addr), + .address_a(ch_addr), .data_a(cpu_rddata), - .wren_a(cpu_strobe), + .wren_a(cpu_strobe), .address_b(ch_addr), .q_b(cache_d) ); -dpram #(.DATAWIDTH(14), .ADDRWIDTH(8)) cache_addr +dpram #(.DATAWIDTH(14), .ADDRWIDTH(8)) cache_addr ( .clock(clk), - .address_a(ch_addr), + .address_a(ch_addr), .data_a({!cache_inv, cpu_hi_addr}), - .wren_a(cpu_strobe || cache_inv), + .wren_a(cpu_strobe || cache_inv), .address_b(ch_addr), .q_b({cache_v, cache_a}) ); diff --git a/rtl/memory/arbiter.v b/rtl/memory/arbiter.v index 2017a5c..9f29215 100644 --- a/rtl/memory/arbiter.v +++ b/rtl/memory/arbiter.v @@ -49,7 +49,7 @@ // - DMA - CPU -module arbiter +module arbiter ( input clk, @@ -57,16 +57,17 @@ module arbiter input c1, input c2, input c3, + input cyc, // dram.v interface - output [20:0] dram_addr, // address for dram access + output [21:0] dram_addr, // address for dram access output dram_req, // dram request output dram_rnw, // Read-NotWrite output [ 1:0] dram_bsel, // byte select: bsel[1] for wrdata[15:8], bsel[0] for wrdata[7:0] output [15:0] dram_wrdata, // data to be written // video - input [20:0] video_addr, // during access block, only when video_strobe==1 + input [20:0] video_addr, // during access block, only when video_strobe==1 input go, // start video access blocks input [ 4:0] video_bw, // [4:3] - total cycles: 11 = 8 / 01 = 4 / 00 = 2 // [2:0] - need cycles @@ -77,65 +78,77 @@ module arbiter output next_vid, // used for TM prefetch // CPU - input [20:0] cpu_addr, + input [20:0] cpu_addr, input [ 7:0] cpu_wrdata, input cpu_req, input cpu_rnw, + input cpu_csrom, input cpu_wrbsel, output reg cpu_next, // next cycle is allowed to be used by CPU output reg cpu_strobe, // c2 strobe output reg cpu_latch, // c2-c3 strobe output curr_cpu_o, + // DMA - input [20:0] dma_addr, + input [20:0] dma_addr, input [15:0] dma_wrdata, input dma_req, input dma_rnw, output dma_next, // TS - input [20:0] ts_addr, + input [20:0] ts_addr, input ts_req, output ts_pre_next, output ts_next, // TM - input [20:0] tm_addr, - input tm_req, - output tm_next + input [20:0] tm_addr, + input tm_req, + output tm_next, + + // ROM loader + input loader_clk, + input [15:0] loader_addr, + input [7:0] loader_data, + input loader_wr ); assign curr_cpu_o = curr_cpu; -localparam CYCLES = 5; +localparam CYCLES = 6; -localparam CYC_CPU = 5'b00001; -localparam CYC_VID = 5'b00010; -localparam CYC_TS = 5'b00100; -localparam CYC_TM = 5'b01000; -localparam CYC_DMA = 5'b10000; -localparam CYC_FREE = 5'b00000; +localparam CYC_CPU = 6'b000001; +localparam CYC_VID = 6'b000010; +localparam CYC_TS = 6'b000100; +localparam CYC_TM = 6'b001000; +localparam CYC_DMA = 6'b010000; +localparam CYC_LOADER = 6'b100000; +localparam CYC_FREE = 6'b000000; -localparam CPU = 0; -localparam VIDEO = 1; -localparam TS = 2; -localparam TM = 3; -localparam DMA = 4; +localparam CPU = 0; +localparam VIDEO = 1; +localparam TS = 2; +localparam TM = 3; +localparam DMA = 4; +localparam LOADER = 5; reg [CYCLES-1:0] curr_cycle; // type of the cycle in progress reg [CYCLES-1:0] next_cycle; // type of the next cycle -wire next_cpu = next_cycle[CPU]; -assign next_vid = next_cycle[VIDEO]; -wire next_ts = next_cycle[TS]; -wire next_tm = next_cycle[TM]; -wire next_dma = next_cycle[DMA]; +wire next_cpu = next_cycle[CPU]; +assign next_vid = next_cycle[VIDEO]; +wire next_ts = next_cycle[TS]; +wire next_tm = next_cycle[TM]; +wire next_dma = next_cycle[DMA]; +wire next_loader = next_cycle[LOADER]; -wire curr_cpu = curr_cycle[CPU]; -wire curr_vid = curr_cycle[VIDEO]; -wire curr_ts = curr_cycle[TS]; -wire curr_tm = curr_cycle[TM]; -wire curr_dma = curr_cycle[DMA]; +wire curr_cpu = curr_cycle[CPU]; +wire curr_vid = curr_cycle[VIDEO]; +wire curr_ts = curr_cycle[TS]; +wire curr_tm = curr_cycle[TM]; +wire curr_dma = curr_cycle[DMA]; +wire curr_loader = curr_cycle[LOADER]; // track blk_rem counter: @@ -148,11 +161,11 @@ wire video_idle = ~|vid_rem; reg [2:0] blk_rem; // remaining accesses in a block (7..0) reg stall; -always @(posedge clk) begin +always @(posedge clk) begin if (c3) begin blk_rem <= blk_nrem; if (video_start) stall <= bw_full & go; - end + end end @@ -167,6 +180,18 @@ reg [2:0] vid_rem; // remaining video accesses in block always @(posedge clk) if (c3) vid_rem <= vid_nrem; +reg loader_wr0; +reg [7:0] loader_data0; +always @(posedge loader_clk) begin + if (loader_wr) begin + loader_wr0 <= 1'd1; + loader_data0 <= loader_data; + end + else if (cyc) begin + loader_wr0 <= 1'd0; + end +end + // next cycle decision wire [CYCLES-1:0] cyc_dev = tm_req ? CYC_TM : (ts_req ? CYC_TS : CYC_DMA); wire dev_req = ts_req || tm_req || dma_req; @@ -174,7 +199,11 @@ wire dev_req = ts_req || tm_req || dma_req; wire dev_over_cpu = 0; always @* begin - if (video_start) begin // video burst start + if (loader_wr0) begin + cpu_next = 1'b0; + next_cycle = CYC_LOADER; + end + else if (video_start) begin // video burst start if (go) begin // video active line - 38us-ON, 26us-ON cpu_next = dev_over_cpu ? 1'b0 : !bw_full; next_cycle = dev_over_cpu ? CYC_VID : (bw_full ? CYC_VID : (cpu_req ? CYC_CPU : CYC_VID)); @@ -182,26 +211,27 @@ always @* begin else begin // video idle cpu_next = !dev_over_cpu; next_cycle = dev_over_cpu ? cyc_dev : (cpu_req ? CYC_CPU : (dev_req ? cyc_dev : CYC_FREE)); - end + end end else begin // video burst in progress cpu_next = dev_over_cpu ? 1'b0 : !video_only; next_cycle = video_only ? CYC_VID : (dev_over_cpu ? cyc_dev : (cpu_req ? CYC_CPU : (!video_idle ? CYC_VID : (dev_req ? cyc_dev : CYC_FREE)))); - end + end end -always @(posedge clk) if (c3) curr_cycle <= next_cycle; +always @(posedge clk) if (c3) curr_cycle <= next_cycle; // DRAM interface -assign dram_wrdata= curr_dma ? dma_wrdata : {cpu_wrdata,cpu_wrdata}; // write data has to be clocked at c0 in dram.v -assign dram_bsel = {cpu_wrbsel | next_dma, ~cpu_wrbsel | next_dma}; +assign dram_wrdata= curr_loader? {loader_data0,loader_data0} : curr_dma ? dma_wrdata : {cpu_wrdata,cpu_wrdata}; // write data has to be clocked at c0 in dram.v +assign dram_bsel = next_loader? {loader_addr[0], ~loader_addr[0]} : next_dma ? 2'b11 : {cpu_wrbsel, ~cpu_wrbsel}; assign dram_req = |next_cycle; -assign dram_rnw = next_cpu ? cpu_rnw : ~next_dma | dma_rnw; -assign dram_addr = {21{next_cpu}} & cpu_addr - | {21{next_vid}} & video_addr - | {21{next_ts }} & ts_addr - | {21{next_tm }} & tm_addr - | {21{next_dma}} & dma_addr; +assign dram_rnw = next_loader? 1'b0 : next_cpu ? cpu_rnw : ~next_dma | dma_rnw; +assign dram_addr = {22{next_loader}} & { 1'b1, 6'b000000, loader_addr[15:1] } + | {22{next_cpu}} & { cpu_csrom, {6{~cpu_csrom}} & cpu_addr[20:15], cpu_addr[14:0] } + | {22{next_vid}} & { 1'b0, video_addr } + | {22{next_ts }} & { 1'b0, ts_addr } + | {22{next_tm }} & { 1'b0, tm_addr } + | {22{next_dma}} & { 1'b0, dma_addr }; reg cpu_rnw_r; always @(posedge clk) if (c3) cpu_rnw_r <= cpu_rnw; diff --git a/rtl/memory/ddram.sv b/rtl/memory/ddram.sv deleted file mode 100644 index 283af09..0000000 --- a/rtl/memory/ddram.sv +++ /dev/null @@ -1,124 +0,0 @@ -// -// ddram.v -// -// DE10-nano DDR3 memory interface -// -// Copyright (c) 2017 Sorgelig -// -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// ------------------------------------------ -// - -// 8-bit version - -module ddram -( - input reset, - input DDRAM_CLK, - - input DDRAM_BUSY, - output [7:0] DDRAM_BURSTCNT, - output [28:0] DDRAM_ADDR, - input [63:0] DDRAM_DOUT, - input DDRAM_DOUT_READY, - output DDRAM_RD, - output [63:0] DDRAM_DIN, - output [7:0] DDRAM_BE, - output DDRAM_WE, - - input [27:0] addr, // 256MB at the end of 1GB - output [7:0] dout, // data output to cpu - input [7:0] din, // data input from cpu - input we, // cpu requests write - input rd, // cpu requests read - output ready // dout is valid. Ready to accept new read/write. -); - -assign DDRAM_BURSTCNT = 1; -assign DDRAM_BE = (8'd1< -// -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// IPFS_FILES : pll.vo -// RELATED_FILES: pll.v, pll_0002.v diff --git a/rtl/pll/pll_0002.qip b/rtl/pll/pll_0002.qip deleted file mode 100644 index 9f8ded1..0000000 --- a/rtl/pll/pll_0002.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" -set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" -set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" -set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" diff --git a/rtl/pll/pll_0002.v b/rtl/pll/pll_0002.v deleted file mode 100644 index d78465a..0000000 --- a/rtl/pll/pll_0002.v +++ /dev/null @@ -1,90 +0,0 @@ -`timescale 1ns/10ps -module pll_0002( - - // interface 'refclk' - input wire refclk, - - // interface 'reset' - input wire rst, - - // interface 'outclk0' - output wire outclk_0, - - // interface 'outclk1' - output wire outclk_1, - - // interface 'locked' - output wire locked -); - - altera_pll #( - .fractional_vco_multiplier("true"), - .reference_clock_frequency("50.0 MHz"), - .operation_mode("direct"), - .number_of_clocks(2), - .output_clock_frequency0("84.000000 MHz"), - .phase_shift0("0 ps"), - .duty_cycle0(50), - .output_clock_frequency1("56.000000 MHz"), - .phase_shift1("0 ps"), - .duty_cycle1(50), - .output_clock_frequency2("0 MHz"), - .phase_shift2("0 ps"), - .duty_cycle2(50), - .output_clock_frequency3("0 MHz"), - .phase_shift3("0 ps"), - .duty_cycle3(50), - .output_clock_frequency4("0 MHz"), - .phase_shift4("0 ps"), - .duty_cycle4(50), - .output_clock_frequency5("0 MHz"), - .phase_shift5("0 ps"), - .duty_cycle5(50), - .output_clock_frequency6("0 MHz"), - .phase_shift6("0 ps"), - .duty_cycle6(50), - .output_clock_frequency7("0 MHz"), - .phase_shift7("0 ps"), - .duty_cycle7(50), - .output_clock_frequency8("0 MHz"), - .phase_shift8("0 ps"), - .duty_cycle8(50), - .output_clock_frequency9("0 MHz"), - .phase_shift9("0 ps"), - .duty_cycle9(50), - .output_clock_frequency10("0 MHz"), - .phase_shift10("0 ps"), - .duty_cycle10(50), - .output_clock_frequency11("0 MHz"), - .phase_shift11("0 ps"), - .duty_cycle11(50), - .output_clock_frequency12("0 MHz"), - .phase_shift12("0 ps"), - .duty_cycle12(50), - .output_clock_frequency13("0 MHz"), - .phase_shift13("0 ps"), - .duty_cycle13(50), - .output_clock_frequency14("0 MHz"), - .phase_shift14("0 ps"), - .duty_cycle14(50), - .output_clock_frequency15("0 MHz"), - .phase_shift15("0 ps"), - .duty_cycle15(50), - .output_clock_frequency16("0 MHz"), - .phase_shift16("0 ps"), - .duty_cycle16(50), - .output_clock_frequency17("0 MHz"), - .phase_shift17("0 ps"), - .duty_cycle17(50), - .pll_type("General"), - .pll_subtype("General") - ) altera_pll_i ( - .rst (rst), - .outclk ({outclk_1, outclk_0}), - .locked (locked), - .fboutclk ( ), - .fbclk (1'b0), - .refclk (refclk) - ); -endmodule - diff --git a/rtl/rtc/mc146818a.v b/rtl/rtc/mc146818a.v index 4e1031c..62fd800 100644 --- a/rtl/rtc/mc146818a.v +++ b/rtl/rtc/mc146818a.v @@ -77,10 +77,7 @@ always @(*) begin end always @(posedge CLK) begin - reg flg; - - flg <= RTC[64]; - if (flg != RTC[64]) begin + if (RTC[62] && !b_reg[7]) begin seconds_reg <= RTC[7:0]; minutes_reg <= RTC[15:8]; hours_reg <= RTC[23:16]; diff --git a/rtl/tsbios.mif b/rtl/tsbios.mif deleted file mode 100644 index f2579f4..0000000 --- a/rtl/tsbios.mif +++ /dev/null @@ -1,2753 +0,0 @@ --- http://srecord.sourceforge.net/ --- --- Generated automatically by srec -o --mif --- -DEPTH = 65536; -WIDTH = 8; -ADDRESS_RADIX = HEX; -DATA_RADIX = HEX; -CONTENT BEGIN -0000: F3 31 00 60 C3 4F 16 FF 01 AF 27 ED 70 F0 18 FB C3 00 20 FF FF FF FF FF; -0018: C3 E9 1B FF FF FF FF FF C9 FF FF FF FF FF FF FF C9 FF FF FF FF FF FF FF; -0030: C9 FF FF FF FF FF FF FF C3 35 16 FF FF FF FF FF FF FF FF FF FF FF FF FF; -0048: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -0060: FF FF FF FF FF FF ED 45 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -0078: FF FF FF FF FF FF FF FF C5 21 4B 5D 11 4C 5D 01 68 00 36 00 ED B0 F1 32; -0090: B1 5D 21 00 00 22 A4 5D 22 A6 5D CD 8E 09 CD F1 09 20 51 CD 7C 02 20 50; -00A8: 21 12 0A 11 62 5D 01 0B 00 ED B0 CD 1E 02 28 44 22 00 44 ED 53 02 44 21; -00C0: 00 44 CD BB 01 21 00 44 06 01 CD 00 01 21 11 44 ED 5B 09 44 D5 01 EF 01; -00D8: ED B0 EB 06 01 CD 00 01 3A 4C 5D FE 0F 20 F4 DD 21 F7 13 11 00 5C CD 1E; -00F0: 0A D1 AF C9 3E 01 18 06 3E 02 18 02 3E 03 37 C9 AF 32 4D 5D CD 1C 01 20; -0108: 0C C5 2A 9D 5D 3E 01 CD 35 01 C1 10 F4 2A 9D 5D 3A 4C 5D C9 22 9D 5D 3A; -0120: 4B 5D B7 20 0E 3A 4C 5D B7 C0 C5 21 99 5D CD BB 01 C1 C9 AF C9 32 4E 5D; -0138: E5 2A 5E 5D ED 5B 60 5D CD B8 09 E1 3A 4E 5D CD D0 09 22 9D 5D 21 5E 5D; -0150: 11 5A 5D 01 04 00 ED B0 2A 5E 5D ED 5B 60 5D ED 4B 4E 5D 09 30 01 13 22; -0168: 5E 5D ED 53 60 5D 21 4B 5D 79 86 77 ED 4B 89 5D B9 D8 2A 99 5D ED 5B 9B; -0180: 5D CD 8D 01 CD BB 01 C8 C1 C1 C3 15 01 CD FD 03 CB 21 CB 10 CB 21 CB 10; -0198: C5 ED 53 52 5D 22 50 5D ED 4B 93 5D CD 27 04 CD 0B 02 CD A0 09 21 00 42; -01B0: 3E 01 CD D0 09 C1 21 00 42 09 C9 CD 84 04 5E 23 56 23 7E 23 66 6F B4 B3; -01C8: B2 28 32 7C FE 0F 28 36 EB 22 99 5D ED 53 9B 5D 01 02 00 B7 ED 42 30 01; -01E0: 1B 3A 89 5D CD 15 04 ED 4B 95 5D CD 27 04 EB ED 4B 97 5D 09 EB CD 0B 02; -01F8: CD A0 09 AF C9 2A 8B 5D ED 5B 8D 5D 18 CB 32 4C 5D B7 C9 ED 4B 8F 5D ED; -0210: 43 56 5D ED 4B 91 5D ED 43 58 5D C3 2B 04 21 A4 5D 11 99 5D 01 04 00 ED; -0228: B0 CD 84 04 3A 4C 5D FE 0F C8 21 00 44 06 01 CD 00 01 36 00 21 E0 43 CD; -0240: 48 02 C0 7C FE 46 18 E4 01 20 00 09 7E B7 C8 CD 58 02 20 F4 3E 01 B7 C9; -0258: E5 11 62 5D 06 0B CD 74 02 E1 C0 11 62 5D 01 20 00 ED B0 2A 7C 5D ED 5B; -0270: 76 5D AF C9 1A BE C0 23 13 10 F9 C9 11 00 00 21 00 00 22 99 5D 22 9B 5D; -0288: 22 AC 5D 22 AE 5D 22 A0 5D 22 A2 5D CD A0 09 21 00 44 3E 01 CD D0 09 3E; -02A0: 03 32 9F 5D 32 B3 5D 21 C2 45 11 10 00 06 04 7E FE 05 28 72 FE 0B 28 6E; -02B8: FE 0C 28 6A FE 0F 28 66 19 10 EC 3A B3 5D B7 CA F9 03 ED 5B AE 5D 2A AC; -02D0: 5D CD A0 09 21 00 44 3E 01 CD D0 09 21 9F 5D 35 CA EB 03 21 CE 45 06 10; -02E8: AF B6 23 10 FC C2 EB 03 2A D6 45 ED 5B D8 45 22 56 5D ED 53 58 5D 2A AC; -0300: 5D ED 5B AE 5D CD 2B 04 ED 53 AE 5D 22 AC 5D CD A0 09 21 00 44 3E 01 CD; -0318: D0 09 2A C6 45 ED 5B C8 45 CD 2B 04 18 0D 23 23 23 23 5E 23 56 23 7E 23; -0330: 66 6F EB 22 8F 5D ED 53 91 5D CD A0 09 21 00 44 3E 01 CD D0 09 2A 0B 44; -0348: 7C 3D 3D B5 C2 C3 02 3A 0D 44 B7 CA C3 02 3A 0E 44 B7 CA C3 02 3A 10 44; -0360: B7 CA C3 02 2A 11 44 7C B5 2A 16 44 B4 B5 C2 C3 02 2A 24 44 B4 B5 2A 26; -0378: 44 B4 B5 CA C3 02 3A 0D 44 32 89 5D 06 08 CB 3F 38 04 10 FA 3E 01 B7 C2; -0390: C3 02 2A 0E 44 22 82 5D 3A 10 44 32 84 5D 2A 24 44 22 85 5D 2A 26 44 22; -03A8: 87 5D 2A 2C 44 22 8B 5D 2A 2E 44 22 8D 5D 2A 85 5D ED 5B 87 5D ED 4B 84; -03C0: 5D 06 00 CD 42 04 E5 D5 2A 82 5D 22 93 5D D1 C1 CD 27 04 22 95 5D ED 53; -03D8: 97 5D 21 00 00 22 99 5D 22 9B 5D 22 A4 5D 22 A6 5D AF C9 2A A0 5D ED 5B; -03F0: A2 5D AF 32 B3 5D C3 33 03 3E 01 B7 C9 7D 08 7D 6C 63 5A 16 00 17 CB 15; -0408: CB 14 CB 13 CB 12 08 E6 7F 06 00 4F C9 FE 02 D8 CB 3F CB 25 CB 14 CB 13; -0420: CB 12 CB 3F 30 F4 C9 09 D0 13 C9 EB ED 4B 58 5D 09 EB ED 4B 56 5D 09 30; -0438: 01 13 22 56 5D ED 53 58 5D C9 78 41 4F 0C B7 20 04 05 28 2C 04 AF B8 20; -0450: 01 0D 05 E5 C5 62 6B B8 28 04 19 10 FD 47 0D 20 F9 22 54 5D C1 E1 54 5D; -0468: B8 28 06 19 38 0B 10 FB 47 0D 20 F7 ED 5B 54 5D C9 D9 2A 54 5D 23 22 54; -0480: 5D D9 18 EA AF 32 4B 5D 32 4C 5D C9 40 00 00 00 00 95 48 00 00 01 AA 87; -0498: 50 00 00 02 00 FF 22 5E 5D ED 53 60 5D 22 A8 5D ED 53 AA 5D C9 ED 5B A8; -04B0: 5D ED 4B AA 5D 08 CD 37 06 20 FE 08 08 CD A0 06 FE FE 20 F9 CD D4 04 08; -04C8: 3D 20 F1 CD FC 05 CD C1 05 C3 99 05 C5 D5 01 57 00 ED B2 ED B2 ED 78 ED; -04E0: 78 D1 C1 C9 B7 C0 CD F6 04 11 02 00 B7 C0 11 00 00 C9 CD B9 06 C9 CD 99; -04F8: 05 11 0A 02 CD CD 05 11 40 1F 1B 7A B3 CA 93 05 CD 74 06 20 F5 3D 20 F2; -0510: CD 6F 06 F5 ED 58 ED 58 ED 60 ED 68 F1 20 E3 CB 57 28 2E 11 40 1F 1B 7A; -0528: B3 28 10 26 00 CD 17 06 20 F4 FE 01 28 F0 B7 20 02 18 50 11 40 1F 1B 7A; -0540: B3 28 50 CD F4 05 20 F6 FE 01 28 F2 B7 20 44 18 3A 11 AA 01 B7 ED 52 20; -0558: 3A 11 40 1F 1B 7A B3 28 32 26 40 CD 17 06 20 F4 FE 01 28 F0 B7 20 24 CD; -0570: 0F 06 20 1F 01 57 00 ED 78 ED 68 ED 68 ED 68 CB 77 28 08 3E 01 32 B2 5D; -0588: AF 18 0E CD 6A 06 20 03 B7 28 F2 CD B9 06 3E 01 C9 C5 F5 01 77 00 3E 03; -05A0: ED 79 01 57 00 3E FF ED 79 F1 C1 C9 C5 F5 01 77 00 3E 01 ED 79 01 57 00; -05B8: 3E FF ED 79 F1 C1 C3 AC 06 C5 F5 06 10 AF DB 57 10 FB F1 C1 C9 01 57 00; -05D0: 3E FF ED 79 1B 7A B3 20 F7 C9 CD 99 05 CD AC 05 C5 01 57 00 ED 79 AF ED; -05E8: 79 ED 79 ED 79 ED 79 3D ED 79 C1 C9 3E 41 CD DA 05 C3 8C 06 3E 4C CD E0; -0600: 05 AF DB 57 C3 8C 06 3E 77 CD DA 05 C3 8C 06 3E 7A CD DA 05 C3 8C 06 CD; -0618: 07 06 CD 99 05 CD AC 05 01 57 00 3E 69 ED 79 2E 00 ED 61 ED 69 ED 69 ED; -0630: 69 2D ED 69 C3 8C 06 CD 99 05 CD AC 05 E5 C5 D5 69 60 3A B2 5D B7 20 09; -0648: EB 29 EB ED 6A 65 6A 53 5F 3E 52 01 57 00 ED 79 ED 61 ED 69 ED 51 ED 59; -0660: 3E FF ED 79 D1 C1 E1 C3 8C 06 21 98 04 18 08 21 92 04 18 03 21 8C 04 CD; -0678: 99 05 CD AC 05 01 57 00 ED A3 ED A3 ED A3 ED A3 ED A3 ED A3 D5 C5 01 57; -0690: 00 16 0A ED 78 CB 7F 28 04 15 20 F7 14 C1 D1 C9 C5 01 57 00 ED 78 FE FF; -06A8: 28 FA C1 C9 C5 F5 01 57 00 ED 78 3C 20 FB F1 C1 C9 AF D3 77 D3 57 C9 22; -06C0: 5E 5D ED 53 60 5D 7C 62 53 5F 22 A8 5D ED 53 AA 5D C9 E5 D5 2A A8 5D ED; -06D8: 5B AA 5D 7C E6 0F 67 3A B0 5D B4 01 D0 FF ED 79 01 70 00 ED 69 01 B0 00; -06F0: ED 51 01 90 00 ED 59 D1 E1 C9 01 D0 FF ED 78 E6; -0700: 0F 67 01 70 00 ED 68 01 B0 00 ED 50 01 90 00 ED 58 C9 F5 08 CD FA 07 01; -0718: 50 00 08 ED 79 CD D2 06 3E 20 CD E8 07 C1 C5 CD F2 07 CD 34 07 CD EB 07; -0730: C1 10 F3 C9 1E 10 16 11 3E 20 4B ED A2 4A ED A2 4B ED A2 4A ED A2 4B ED; -0748: A2 4A ED A2 4B ED A2 4A ED A2 4B ED A2 4A ED A2 4B ED A2 4A ED A2 4B ED; -0760: A2 4A ED A2 4B ED A2 4A ED A2 3D C2 3A 07 C9 28 04 3E E0 18 02 3E F0 32; -0778: B0 5D 01 D0 FF ED 79 C9 B7 28 4A FE 03 30 46 FE 02 CD 6F 07 3E 08 CD 04; -0790: 08 21 C4 00 CD 11 08 20 34 11 00 00 21 02 00 CD BF 06 CD D2 06 3E EC CD; -07A8: 04 08 21 C4 00 CD 11 08 20 1B 21 31 00 CD 21 08 28 13 21 00 44 CD 34 07; -07C0: CD FA 06 7A B3 B4 20 05 7D FE 02 28 04 3E 01 B7 C9 11 00 00 AF C9 CD DF; -07D8: 07 2B 7C B5 20 F8 C9 FB 76 C9 01 F0 00 ED 78 C9 CD 04 08 CD E2 07 07 D0; -07F0: 18 F9 CD E2 07 E6 08 C0 18 F8 CD E2 07 E6 C0 FE 40 C8 18 F6 01 F0 00 ED; -0808: 79 C9 01 F0 00 ED 78 0F C9 CD E2 07 CB 7F C8 CD DF 07 2B 7C B5 20 F2 3C; -0820: C9 CD E2 07 E6 08 C0 CD DF 07 2B 7C B5 20 F2 C9 01 BA FF 3E 01 ED 79 21; -0838: 01 00 CD D6 07 C9 22 5E 5D ED 53 60 5D 7C 62 53 5F 22 A8 5D ED 53 AA 5D; -0850: C9 E5 D5 2A A8 5D ED 5B AA 5D 7C E6 0F 67 3A B0 5D B4 01 BE FE ED 79 01; -0868: BE FB ED 69 01 BE FD ED 51 01 BE FC ED 59 D1 E1 C9 01 BE FE ED 78 E6 0F; -0880: 67 01 BE FB ED 68 01 BE FD ED 50 01 BE FC ED 58 C9 F5 08 CD 58 09 01 BE; -0898: FA 08 ED 79 CD 51 08 3E 20 CD 46 09 C1 C5 CD 50 09 CD B3 08 CD 49 09 C1; -08B0: 10 F3 C9 1E F8 16 D8 0E BE 3E 40 43 ED A2 42 ED A2 43 ED A2 42 ED A2 43; -08C8: ED A2 42 ED A2 43 ED A2 42 ED A2 3D C2 BB 08 C9 28 04 3E E0 18 02 3E F0; -08E0: 32 B0 5D 01 BE FE ED 79 C9 FE 03 38 4A FE 05 30 46 FE 04 CD D8 08 3E 08; -08F8: CD 62 09 21 C4 00 CD 6F 09 20 34 11 00 00 21 02 00 CD 3E 08 CD 51 08 3E; -0910: EC CD 62 09 21 C4 00 CD 6F 09 20 1B 21 31 00 CD 7F 09 28 13 21 00 44 CD; -0928: B3 08 CD 79 08 7A B3 B4 20 05 7D FE 02 28 04 3E 01 B7 C9 11 00 00 AF C9; -0940: 01 BE FF ED 78 C9 CD 62 09 CD 40 09 07 D0 18 F9 CD 40 09 E6 08 C0 18 F8; -0958: CD 40 09 E6 C0 FE 40 C8 18 F6 01 BE FF ED 79 C9 01 BE FF ED 78 0F C9 CD; -0970: 40 09 CB 7F C8 CD DF 07 2B 7C B5 20 F2 3C C9 CD 40 09 E6 08 C0 CD DF 07; -0988: 2B 7C B5 20 F2 C9 3A B1 5D B7 CA F2 04 FE 03 CA 30 08 FE 04 CA 30 08 C9; -09A0: 3A B1 5D B7 CA 9E 04 3D CA BF 06 3D CA BF 06 3D CA 3E 08 3D CA 3E 08 C9; -09B8: 3A B1 5D B7 CA A5 04 3D CA C6 06 3D CA C6 06 3D CA 45 08 3D CA 45 08 C9; -09D0: 4F 3A B1 5D B7 28 0E 3D 28 0F 3D 28 0C 3D 28 0D 3D 28 0A 79 C9 79 C3 AD; -09E8: 04 79 C3 12 07 79 C3 91 08 3A B1 5D 4F B7 28 0E 3D 28 0F 3D 28 0C 3D 28; -0A00: 0D 3D 28 0A 4F C9 79 C3 E4 04 79 C3 80 07 79 C3 E9 08 42 4F 4F 54 20 20; -0A18: 20 20 24 43 20 00 06 00 D9 16 BF 0E 10 CD F9 0A DD 7E 00 DD 23 D9 12 13; -0A30: D9 29 10 03 CD F9 0A 38 EF 1E 01 3E 80 29 10 03 CD F9 0A 17 38 F7 FE 03; -0A48: 38 05 83 5F A9 20 EC 83 FE 04 28 62 CE FF FE 02 D9 4F D9 3E BF 38 15 29; -0A60: 10 03 CD F9 0A 17 38 F7 28 05 3C 82 30 08 92 3C 20 0D 3E EF 0F BF 29 10; -0A78: 03 CD F9 0A 17 38 F7 D9 26 FF 28 09 67 3C DD 7E 00 DD 23 28 0B 6F 19 ED; -0A90: B0 18 9D D9 CB 0A 18 99 FE E0 38 F1 07 A9 3C 28 F2 D6 10 6F 4F 26 FF 19; -0AA8: ED A0 DD 7E 00 DD 23 12 23 13 7E C3 2E 0A 3E 80 29 10 03 CD F9 0A 8F 20; -0AC0: 16 38 F5 3E FC 18 13 47 DD 4E 00 DD 23 3F 18 8A FE 0F 38 F3 20 83 C9 9F; -0AD8: 3E EF 29 10 03 CD F9 0A 17 38 F7 D9 20 BD CB 7F 28 E6 D6 EA 87 47 DD 7E; -0AF0: 00 DD 23 12 13 10 F7 18 98 41 DD 6E 00 DD 66 01 DD 23 DD 23 C9 54 53 2D; -0B08: 42 49 4F 53 20 53 65 74 75 70 20 55 74 69 6C 69 74 79 00 42 75 69 6C 64; -0B20: 20 64 61 74 65 3A 20 32 38 2E 30 34 2E 32 30 31 38 20 30 30 3A 33 31 3A; -0B38: 35 36 00 41 72 72 6F 77 73 20 2D 20 6D 6F 76 65 2C 20 20 45 6E 74 65 72; -0B50: 20 2D 20 63 68 61 6E 67 65 20 6F 70 74 69 6F 6E 2C 20 20 46 31 32 20 2D; -0B68: 20 65 78 69 74 00 53 79 73 74 65 6D 20 4D 65 64 69 74 61 74 69 6F 6E 3A; -0B80: 00 50 72 65 73 73 20 53 53 20 2B 20 52 65 73 65 74 20 74 6F 20 63 68 61; -0B98: 6E 67 65 20 73 74 61 72 74 2D 75 70 20 6F 70 74 69 6F 6E 73 00 55 4E 4B; -0BB0: 4E 4F 57 4E 20 45 52 52 4F 52 21 00 42 6F 6F 74 2D 44 65 76 69 63 65 20; -0BC8: 4E 4F 54 20 52 45 41 44 59 21 00 46 41 54 33 32 20 4E 4F 54 20 46 4F 55; -0BE0: 4E 44 21 00 62 6F 6F 74 2E 24 63 20 4E 4F 54 20 46 4F 55 4E 44 21 00 07; -0BF8: 07 20 10 0A 0A 0C 08 8C 0B 53 65 6C 65 63 74 20 4E 56 52 41 4D 20 6F 70; -0C10: 74 69 6F 6E 73 3A 00 43 0C E2 0C 56 0C A8 0D 64 0C B7 0D 73 0C 03 0D 80; -0C28: 0C 3A 0D 8B 0C 03 0D 9B 0C 3A 0D A6 0C 66 0D B6 0C DF 0D C5 0C A8 0D D3; -0C40: 0C 17 0E 03 14 5D 43 50 55 20 53 70 65 65 64 2C 20 4D 48 7A 3A 00 02 16; -0C58: 5D 43 50 55 20 43 61 63 68 65 3A 00 04 1B 5D 23 37 46 46 44 20 73 70 61; -0C70: 6E 3A 00 05 17 5D 52 65 73 65 74 20 74 6F 3A 00 04 18 5D 20 20 62 61 6E; -0C88: 6B 3A 00 05 19 5D 43 53 20 52 65 73 65 74 20 74 6F 3A 00 04 1A 5D 20 20; -0CA0: 62 61 6E 6B 3A 00 06 15 5D 42 6F 6F 74 20 44 65 76 69 63 65 3A 00 07 1C; -0CB8: 5D 5A 58 20 50 61 6C 65 74 74 65 3A 00 02 1D 5D 4E 47 53 20 52 65 73 65; -0CD0: 74 3A 00 08 1E 5D 49 4E 54 20 4F 66 66 73 65 74 3A 00 20 20 20 20 20 20; -0CE8: 20 33 2E 35 00 20 20 20 20 20 20 20 20 20 37 00 20 20 20 20 20 20 20 20; -0D00: 31 34 00 20 20 20 52 4F 4D 20 23 30 30 00 20 20 20 52 4F 4D 20 23 30 34; -0D18: 00 20 20 20 52 41 4D 20 23 46 38 00 42 44 20 62 6F 6F 74 2E 24 63 00 42; -0D30: 44 20 73 79 73 2E 72 6F 6D 00 20 20 20 20 54 52 2D 44 4F 53 00 20 20 42; -0D48: 61 73 69 63 20 34 38 00 20 42 61 73 69 63 20 31 32 38 00 20 20 20 20 20; -0D60: 20 20 53 59 53 00 53 44 20 5A 2D 63 6F 6E 74 72 00 49 44 45 20 4E 65 6D; -0D78: 6F 20 4D 00 49 44 45 20 4E 65 6D 6F 20 53 00 20 20 20 20 52 53 2D 32 33; -0D90: 32 00 49 44 45 20 53 6D 75 63 20 4D 00 49 44 45 20 53 6D 75 63 20 53 00; -0DA8: 20 4F 46 46 00 20 20 4F 4E 00 41 75 74 6F 00 20 20 20 20 20 35 31 32 6B; -0DC0: 00 20 20 20 20 20 31 32 38 6B 00 31 32 38 6B 20 41 75 74 6F 00 20 20 20; -0DD8: 20 31 30 32 34 6B 00 44 65 66 61 75 6C 74 00 42 2E 62 6C 61 63 6B 00 20; -0DF0: 20 4C 69 67 68 74 00 20 20 20 50 61 6C 65 00 20; -0E00: 20 20 44 61 72 6B 00 47 72 61 79 73 63 6C 00 20 43 75 73 74 6F 6D 00 30; -0E18: 00 31 00 32 00 33 00 34 00 35 00 36 00 37 00 00 00 10 00 00 40 10 40 00; -0E30: 02 10 02 00 42 10 42 08 21 18 00 00 60 18 60 00 03 18 03 00 63 18 63 00; -0E48: 00 14 00 00 50 14 50 80 02 94 02 80 52 94 52 00 00 18 00 00 60 18 60 00; -0E60: 03 18 03 00 63 18 63 00 00 10 00 00 40 10 40 00 02 10 02 00 42 10 42 00; -0E78: 00 18 00 00 60 18 60 00 03 18 03 00 63 18 63 00 00 08 00 00 20 08 20 00; -0E90: 01 08 01 00 21 08 21 00 00 10 00 00 40 10 40 00 02 10 02 00 42 10 42 08; -0EA8: 21 10 21 08 41 10 41 08 22 10 22 08 42 10 42 08 21 18 21 08 61 18 61 08; -0EC0: 23 18 23 08 63 18 63 00 00 63 0C C6 18 29 25 8C 31 10 42 73 4E D6 5A 00; -0ED8: 00 84 10 08 21 6B 2D CE 39 31 46 94 52 18 63 00 00 08 00 10 00 18 00 00; -0EF0: 20 08 20 10 20 18 20 00 40 08 40 10 40 18 40 00 60 08 60 10 60 18 60 00; -0F08: 01 08 01 10 01 18 01 00 21 08 21 10 21 18 21 00 41 08 41 10 41 18 41 00; -0F20: 61 08 61 10 61 18 61 00 02 08 02 10 02 18 02 00 22 08 22 10 22 18 22 00; -0F38: 42 08 42 10 42 18 42 00 62 08 62 10 62 18 62 00 03 08 03 10 03 18 03 00; -0F50: 23 08 23 10 23 18 23 00 43 08 43 10 43 18 43 00 63 08 63 10 63 18 63 00; -0F68: 7A 78 63 76 61 73 64 66 67 71 77 65 72 74 31 32 33 34 35 30 39 38 37 36; -0F80: 70 6F 69 75 79 0D 6C 6B 6A 68 20 0E 6D 6E 62 00 5A 58 43 56 41 53 44 46; -0F98: 47 51 57 45 52 54 07 06 04 05 08 0C 0F 09 0B 0A 50 4F 49 55 59 0D 4C 4B; -0FB0: 4A 48 20 0E 4D 4E 42 00 3A 60 3F 2F 7E 7C 5C 7B 7D 20 20 20 3C 3E 21 40; -0FC8: 23 24 25 5F 29 28 27 26 22 3B 20 5D 5B 0D 3D 2B 2D 5E 20 0E 2E 2C 2A 00; -0FE0: 00 00 01 00 00 03 00 01 00 00 01 FF FF FF FF FF FF FF FF FF FF 00 00 42; -0FF8: 08 84 10 C6 18 08 21 4A 29 8C 31 CE 39 21 04 63 0C A5 14 E7 1C 29 25 6B; -1010: 2D AD 35 EF 3D 7F 7B 00 7C 2E 8C 82 AA BA 92 18 08 FE D6 E0 C2 C6 EE 3E; -1028: 45 44 E3 43 38 10 00 13 08 02 AC D0 01 E6 31 82 F2 7F B0 E0 9E 29 2B A7; -1040: 30 D3 C8 A1 D2 E5 1D 44 ED 08 BA F1 A1 0E 06 7A D8 88 18 A6 70 FD 6C F6; -1058: C7 C1 1E 12 40 30 FE FC 70 E0 40 3E 22 00 17 2E E4 4F C9 96 FA C6 E6 92; -1070: 80 E0 20 8C F8 FE 66 40 02 0E 26 10 FB FE 88 A2 A0 6F 9B 8F 6C EC CF 00; -1088: 7E B6 FF 7C 76 36 1A 03 3C 60 66 3C CE 06 F7 4F 54 0D 29 D8 D9 15 B6 C1; -10A0: F3 54 5F 3E 0E 08 04 7E 87 30 DF C9 63 00 20 5F C5 F5 9F 40 7E 61 66 28; -10B8: E1 FE 91 14 90 CC 36 1B 48 06 42 7E E9 C8 AB 5F 30 1F E0 DD C6 8D 24 48; -10D0: 18 40 7E E8 CA C6 1C 18 3E 60 89 C4 E1 EE 18 63 66 0C 30 77 80 C6 8A D9; -10E8: 34 2C 3A 73 B1 08 C3 4F 3A 06 02 F1 B0 32 E6 60 49 20 20 01 C8 EA 18 0A; -1100: A8 8F C0 99 93 A3 F9 AB 49 64 02 93 03 C7 53 CF D1 C0 A5 62 29 6E 76 28; -1118: FB 2A E5 38 26 68 E0 3C 7E 06 DB 80 6C AA 65 40 3E C7 7E DD 03 60 7C 53; -1130: 40 16 E0 52 D8 11 EF 0C D0 41 9D B8 5A 3E EB B6 E0 30 05 DB 95 6A FB 99; -1148: 60 E4 40 9A 50 73 B5 58 87 98 CF 09 1C C0 5A 5E CF 78 60 C0 7E 80 D4 5A; -1160: DB 90 A0 3B 42 60 49 55 A8 6B 50 80 C3 3B 78 83 6D AE 1F 7F 31 81 6E 8E; -1178: E4 F0 C9 41 35 68 A8 41 DC 57 EF 36 E3 48 6C 78 FF 44 60 24 73 C8 82 AB; -1190: D6 4C 54 C0 46 EA 76 C8 2D 62 90 57 2F A0 05 A8 B0 A8 2B F6 95 43 39 B0; -11A8: 88 21 60 BA 4B 5F B0 96 97 D0 84 2A 24 C6 ED FF D6 EE 44 D5 A0 C6 12 D2; -11C0: 7D A6 94 D0 21 90 1E 24 E4 C9 81 B5 E5 C0 01 03 00 75 78 60 90 98 D1 B7; -11D8: DF 86 E7 FF 10 08 A9 F2 4B A9 91 3E 30 50 20 97 00 1F 52 35 30 87 4E 32; -11F0: 50 05 E3 A1 1C 36 30 78 52 34 9F E5 50 8F D0 42 28 80 B5 3F 3F 81 0C F9; -1208: 95 38 E1 D0 FF BF 0D 7C AF 4E 1C D0 FC D6 F4 80 E5 6A AF B0 30 F5 F0 FF; -1220: 48 1D B0 D5 3C 82 17 FF F5 4C 78 92 5E 38 C0 50 2F 78 00 2F 1E 00 58 47; -1238: FF E0 72 70 FF 08 43 59 FD 1C E0 CB 43 1E C3 EC 70 00 2C 0E 0E 47 34 58; -1250: E3 F1 12 42 99 A1 18 8A D1 2F 08 E1 CB 08 00 9D C3 18 78 1E 36 F0 3B A7; -1268: FF C3 E7 B3 00 D6 7C F7 E3 D8 6D 60 62 40 46 AC 1B 04 6A 1E 3E 08 3E A0; -1280: C8 6B 1F 08 D8 54 F4 08 F7 95 1F F8 00 FC 4F 91 72 10 31 93 BF 84 10 DF; -1298: 86 18 40 DE 7F 01 2D 1D 70 7B BF FE 74 62 FF B4 5C E0 38 15 C7 E1 F6 DE; -12B0: D6 F0 30 A0 0E 8C E7 50 CE DB FB 6E 28 D7 15 91 87 C3 08 91 BC C2 70 07; -12C8: E9 90 6A A9 A0 D0 0F 00 8B 07 00 21 85 FF 03 E8 FF 50 D1 FF 3D 78 08 7A; -12E0: 00 FF E1 00 FF FF 8A FE 08 A1 92 BD BC 22 88 BD BC 55 AA BD BC 77 DD DF; -12F8: 7E 18 B2 BD F8 E9 EA DB BD CC E6 BF FE 0F CB 67 A4 E6 06 F6 3B 82 FA 0D; -1310: EA 57 90 E2 B2 0D C9 90 03 B8 7C 1D AD 17 A0 1F 80 E4 B1 2F FF EC 86 F4; -1328: 6D DB D0 07 49 1F E3 19 78 1B 57 67 72 67 60 7F C9 0F 10 DE 27 E7 D5 2A; -1340: CF E7 07 E4 54 48 21 1D 74 40 3E 83 BE 33 A0 40 97 D1 BD 7A 90 B9 5C 3D; -1358: A9 07 74 90 57 8B 88 97 0C B0 D8 7A F9 B8 52 3D DF 40 D9 3D A5 D9 BE B1; -1370: ED 7E 7B F0 0F FB F6 8F E8 5E F7 7F 5F 0E 68 09 99 EE 7F FE FB 65 9D BD; -1388: C7 98 EF 01 80 7B 40 80 1E D0 80 DD F5 80 17 18 7F 19 9D 7F 75 BA 8E 75; -13A0: 07 7F 3A 2F A0 7F 76 23 C0 DF EE 80 24 F3 72 A8 24 D2 AE A0 61 F6 C9 D5; -13B8: AC B6 47 BF 0B 0E 1B 5C 7B F6 D8 CC 3A 40 D3 6D D7 61 76 DC 69 D7 00 41; -13D0: E6 9D E4 7E 92 B3 04 C9 7E F3 0C 6C FB 1C 8F CD EF FC DC CC 19 38 38 6C; -13E8: 71 9E E1 30 06 3E 5F 5E B7 AA 54 80 01 00 F0 50 FC FF 00 23 0D 44 05 0B; -1400: 4F 71 10 01 FA FC 16 07 07 B3 06 0B B0 D2 80 76 FB FA 74 10 01 FD 7F 3E; -1418: 14 ED 79 C3 00 C0 18 F4 1F FC 3C 40 FF CD 01 21 B6 FC 5F 87 ED 74 2E F1; -1430: 3D 07 4A 5D C3 19 26 CE FA 3B 8E 59 4F 3A 4B 36 5E 48 40 A7 4D EF 6D 2D; -1448: 92 5C 70 BE 08 02 B2 B6 1A 06 12 E2 AA 58 FF 58 EA 21 17 29 3C 40 E0 50; -1460: 18 99 F0 BB 38 62 E1 AF EB 8F D3 F7 DB F7 FE 1E 28 03 FE 1F C0 CF 31 3E; -1478: 01 32 EF 5C C9 00 C2 F8 FF 5F FB FC F4 09 A8 10 4B 7F FC C4 15 53 81 0F; -1490: C9 52 34 5B EA AB 2F FF 8A 1F 22 31 35 36 5F 30 03 DB 01 3D 3F 3C 5D 53; -14A8: 74 6F 72 6D F4 3F 20 42 FA F9 CC E6 2E 6D 56 7A 75 32 08 03 BF 80 25 DB; -14C0: 18 5D 4F 5F 09 26 A4 BF 07 47 66 26 FC FF 4F A7 2C AA DA 02 E6 21 F7 22; -14D8: DF 3E 62 7D EA 90 1A B5 90 50 8A 62 C4 C9 19 C7 F9 C0 B0 22 32 33 36 30; -14F0: 30 22 0D 80 0D 80 31 00 60 2A 3B 5D 22 FE 5B ED; -1500: 5B F4 5C 21 19 6F E5 06 42 CD 96 5D AA DF 8E 21 00 DB 06 25 F5 BF 3A AE; -1518: E5 E6 F7 F6 10 CD 90 BC 3B FB 06 05 DE 87 3E 20 DD F4 5F 18 79 3E 17 89; -1530: 15 96 98 28 A4 C9 CD 05 5E 0E FF F3 0C 28 0C 79 E6 07 20 0D D9 3E 08 FE; -1548: 2D 7A 4F 01 12 1E AC 7B E5 E1 16 00 CA 6F E0 C8 20 DF 24 1C CB 63 D9 FA; -1560: 27 A3 14 10 D2 C9 3C 0E 5F 0F 53 EC 09 F2 80 07 DD 8D F1 21 D7 3F 01 7F; -1578: E4 0D 30 E5 28 0E 3A D6 88 F0 FA E3 93 32 05 B5 6B D9 A9 3E D4 2B FF B5; -1590: 0E 07 B1 C9 21 AA 20 E5 A2 E0 01 C0 63 CD 8D 40 0E EF DD 2E 0A 3E FD DB; -15A8: EF 1F DC 75 40 38 FB 06 F8 21 55 AA ED 61 ED 69 21 EE CC DD 26 C8 CD 78; -15C0: 40 30 48 BC 20 45 80 1C 02 0D BD 3D 1B DB 38 6F 78 6D 32 67 22 6B AF 4D; -15D8: D7 B6 29 5F 23 57 AD ED AB AC AD 08 1B 83 19 77 AE 23 D1 F6 1B 7A B3 20; -15F0: F1 3F FF 0A 6F 08 AD 20 05 37 21 82 FF C9 DD 2D C2 0D 40 B7 E6 6E A9 3A; -1608: 06 00 8E 38 C0 C4 07 10 F7 DD 25 C8 18 F2 06 F8 ED 78 C9 01 EF FB 3E 83; -1620: 35 A7 79 7E 02 00 80 04 3C 96 61 84 2A 03 FA F5 29 07 3C 60 C9 C5 D5 E5; -1638: F5 CD B1 19 3A 04 5D B7 20 07 CD 97 19 78 32 04 5D F1 E1 D1 C1 FB C9 F3; -1650: 01 AF 11 3E 05 ED 79 ED 56 3E 3F ED 47 AF D3 FE CD 55 1A CD 2C 1A 18 06; -1668: CD 7F 1A C3 40 18 01 AF 00 ED 78 CB 77 28 07 AF 32 13 5D CD 8A 1A 3A 1D; -1680: 5D B7 28 04 3E 80 D3 33 01 FE 7F ED 78 0F 0F D2 40 18 F3 CD E6 1A 01 AF; -1698: 11 3E 05 ED 79 06 12 3E 02 ED 79 06 13 AF ED 79 06 01 3E 05 ED 79 06 00; -16B0: AF ED 79 3A 1C 5D 21 67 0E B7 28 21 21 27 0E 3D 28 1B 21 47 0E 3D 28 15; -16C8: 21 A7 0E 3D 28 0F 21 87 0E 3D 28 09 21 C7 0E 3D 28 03 21 29 5D CD 45 1B; -16E0: CD 61 1B 3A 13 5D 01 AF 29 ED 79 3A 1E 5D 06 22 ED 79 21 00 17 11 00 50; -16F8: 01 F4 00 ED B0 C3 00 50 3A 1B 5D 0F 0F 57 3A 16 5D 07 07 5F 3A 14 5D B3; -1710: 01 AF 20 ED 79 01 FE FE ED 78 0F 3A 1A 5D 5F 3A 19 5D 30 07 3A 18 5D 5F; -1728: 3A 17 5D B7 28 0E 3D 28 13 3D 28 19 3D 28 5C 3D 28 7C 18 FE 01 AF 10 AF; -1740: ED 79 18 14 01 AF 10 3E 04 ED 79 18 0B 01 AF 10 3E F8 ED 79 3E 08 B2 57; -1758: 7B B7 28 0A 3D 28 15 3D 28 1D 3D 28 23 76 7A F6 01 01 AF 21 ED 79 31 2E; -1770: 3D C3 2F 3D 7A F6 01 01 AF 21 ED 79 C3 00 00 7A 01 AF 21 ED 79 C3 00 00; -1788: 7A F6 04 01 AF 21 ED 79 C3 00 00 01 AF 13 AF ED 79 3A 15 5D B7 06 00 28; -17A0: 17 04 3D 28 13 04 3D 28 0F 3D 28 2C 04 3D 28 08 04 3D 28 04 18 FE 18 FE; -17B8: D5 CD 80 00 DC F4 17 38 F8 F1 D5 F6 01 01 AF 21 ED 79 06 10 AF ED 79 FD; -17D0: 21 3A 5C 21 58 27 D9 C9 D5 DD 21 9B 15 11 00 40 CD 1E 0A F1 30 0D F6 01; -17E8: 01 AF 21 ED 79 06 10 AF ED 79 E9 76 F5 CD CB 1A 21 08 03 01 40 09 3E 0A; -1800: CD 9D 1B 11 6E 0B 26 05 06 0A CD 85 1B 11 81 0B 26 09 06 0A CD 85 1B F1; -1818: 47 3D 11 BC 0B 28 0F 3D 11 D3 0B 28 09 3D 11 E4 0B 28 03 11 AD 0B C5 26; -1830: 07 06 0A CD 85 1B F1 3D 20 FE 3A B1 5D 47 37 C9 01 AF 00 3E 20 ED 79 CD; -1848: 94 18 CD E6 1A CD CB 1A 21 00 00 01 50 1E 3E 8F CD 9D 1B 11 05 0B 26 01; -1860: 06 8E CD 85 1B 11 1B 0B 26 02 06 8E CD 85 1B 11 3B 0B 26 1C 06 87 CD 85; -1878: 1B CD 57 19 3A 0F 5D CD EC 18 FB 3A 04 5D B7 28 FA CD A2 18 AF D3 FE 32; -1890: 04 5D 18 EF AF 32 04 5D 32 05 5D 32 0F 5D 32 01 5D C9 3A 05 5D B7 28 01; -18A8: C9 3A 08 5D 3D 47 3A 0F 5D 4F 3A 04 5D FE 02 28 09 FE 03 28 11 FE 04 28; -18C0: 16 C9 79 B7 C8 CD E8 18 3D 32 0F 5D 18 1E 79 B8 D0 CD E8 18 3C 18 F2 ED; -18D8: 5B 11 5D 1A 3C 12 79 CD EC 18 C3 8A 1A C3 92 16 06 89 18 02 06 79 F5 CD; -18F0: 2A 19 2A 06 5D 84 67 CD 90 1B 3A 10 5D 4F ED 5B 11 5D 1A B9 38 02 AF 12; -1908: F5 ED 5B 0D 5D CD 79 1B 4F ED 44 C6 24 6F F1 EB 06 00 0C D6 01 38 03 09; -1920: 18 F9 EB 06 8F CD 90 1B F1 C9 F5 2A 09 5D 87 87 85 6F 8C 95 67 5E 23 56; -1938: 23 ED 53 0B 5D 1A 13 32 10 5D 1A 13 32 11 5D 1A 13 32 12 5D D5 5E 23 56; -1950: ED 53 0D 5D D1 F1 C9 21 F7 0B 5E 23 56 23 4E 23 46 23 E5 EB 3E 8F CD 9D; -1968: 1B E1 7E 23 32 06 5D 7E 23 32 07 5D 5E 23 56 23 46 23 7E 32 08 5D 4F 23; -1980: EB CD 90 1B ED 53 09 5D 3A 0F 5D 47 AF C5 CD E8 18 C1 3C B9 38 F7 C9 3A; -1998: 03 5D FE 0B 06 02 C8 FE 0A 06 03 C8 FE 0D 06 04 C8 FE 0E 06 01 C8 06 00; -19B0: C9 CD F7 19 30 38 4F 06 00 21 8F 0F CB 43 20 0A 21 B7 0F CB 4B 20 03 21; -19C8: 67 0F 09 4E 3A 01 5D B9 28 0B 3E 0F 32 00 5D 79 32 01 5D 18 16 3A 00 5D; -19E0: 3D 32 00 5D 20 0C 3E 02 32 00 5D 79 18 05 AF 32 01 5D AF 32 03 5D C9 01; -19F8: FE FE AF 5F ED 60 2E 05 CB 1C 30 09 3C 2D 20 F8 CB 00 38 F0 C9 B7 28 10; -1A10: FE 24 28 10 06 7F ED 48 CB 49 20 02 CB CB 37 C9 CB C3 18 E0 CB CB CB 43; -1A28: 28 DA 37 C9 11 14 5D 0E 35 CD 3B 1A 1A BD C0 13 1A BC C9 21 FF FF 1A 13; -1A40: AC 67 06 08 29 30 08 7C EE 10 67 7D EE 21 6F 10 F3 0D 20 EA C9 01 F7 EF; -1A58: 3E 80 ED 79 DD 21 13 5D 2E B0 3E 38 0E F7 06 DF ED 69 06 BF ED 50 DD 72; -1A70: 00 DD 23 2C 3D 20 EF 01 F7 EF 3E 00 ED 79 C9 21 DF 0F 11 13 5D 01 36 00; -1A88: ED B0 CD 2C 1A 22 49 5D 01 F7 EF 3E 80 ED 79 DD 21 13 5D 2E B0 3E 38 0E; -1AA0: F7 06 DF ED 69 06 BF DD 56 00 DD 23 ED 51 2C 3D 20 EF 01 F7 EF 3E 00 ED; -1AB8: 79 C9 01 AF 13 3E F7 ED 79 DD 21 15 10 11 00 C0 C3 1E 0A CD EC 1A CD BA; -1AD0: 1A CD 42 1B 01 AF 00 3E 83 ED 79 06 01 3E F6 ED 79 06 13 ED 79 C9 1E 05; -1AE8: 16 1B 18 04 1E F6 16 40 21 00 00 AF 01 AF 13 ED 59 06 1C ED 59 06 1F ED; -1B00: 59 06 1B ED 61 06 1E ED 61 06 1A ED 69 CB FC CB F4 77 2C 77 2C 06 1D ED; -1B18: 69 06 28 15 15 ED 51 06 26 3E 7F ED 79 06 27 3E 01 ED 79 CD 08 00 06 28; -1B30: AF ED 79 06 26 3E 7E ED 79 06 27 3E 01 ED 79 C3 08 00 21 27 0E 01 AF 07; -1B48: 3E 0F ED 79 06 15 3E 10 ED 79 11 E0 01 01 20 00 ED B0 01 AF 15 AF ED 79; -1B60: C9 21 E7 0E 01 AF 07 3E 0F ED 79 06 15 3E 10 ED 79 11 00 00 01 80 00 18; -1B78: DF D5 2E FF 1A 13 2C B7 20 FA D1 7D C9 CD 79 1B 0F E6 7F ED 44 C6 28 6F; -1B90: CB F4 CB FC 1A 13 B7 C8 CD E1 1B 18 F7 CB F4 CB FC 05 05 C5 E5 11 CD C9; -1BA8: 06 BB CD C4 1B E1 C1 24 C5 E5 11 20 BA 06 BA CD C4 1B E1 C1 24 10 F1 11; -1BC0: CD C8 06 BC E5 C5 72 23 73 5D 54 1C 0D 0D 06 00 ED B0 C1 70 E1 CB FD 77; -1BD8: 5D 54 1C 0D 06 00 ED B0 C9 77 CB FD 70 CB BD 2C C9 C9 01 B4 00 78 B1 28; -1BF0: 0F 21 00 5D 36 00 0B 78 B1 28 05 5D 54 13 ED B0; -1C00: 01 00 00 78 B1 28 08 21 1E 1C 11 00 5D ED B0 01 00 00 78 B1 C8 21 1E 1C; -1C18: 11 B4 5D ED B0 C9 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1C30: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1C48: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1C60: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1C78: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1C90: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1CA8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1CC0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1CD8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1CF0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1D08: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1D20: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1D38: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1D50: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1D68: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1D80: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1D98: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1DB0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1DC8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1DE0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1DF8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1E10: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1E28: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1E40: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1E58: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1E70: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1E88: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1EA0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1EB8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1ED0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1EE8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1F00: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1F18: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1F30: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1F48: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1F60: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1F78: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1F90: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1FA8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1FC0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1FD8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -1FF0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F3 D9 57 01 AF 20 3E 02; -2008: ED 79 06 12 ED 78 1E F7 ED 59 32 0D 96 ED 73 13 96 31 00 C0 21 63 20 06; -2020: 00 4A 09 09 7E 23 66 6F 01 30 20 C5 E5 D9 08 C9 ED 7B 13 96 D9 08 01 AF; -2038: 12 3A 0D 96 ED 79 D9 08 C9 E5 ED 57 F5 21 61 20 22 FF 9E 3E 9E ED 47 ED; -2050: 5E FB 76 F3 10 FB F1 ED 47 FE 40 30 02 ED 56 E1 C9 FB C9 8A 22 A9 22 2C; -2068: 21 40 20 82 22 40 20 40 20 40 20 40 20 40 20 40 20 40 20 40 20 40 20 40; -2080: 20 40 20 0F 21 32 21 38 21 54 21 67 21 F5 20 40 20 40 20 40 20 40 20 40; -2098: 20 40 20 40 20 40 20 40 20 40 20 A9 20 F3 20 F4 20 C5 CD 00 21 C1 C0 78; -20B0: FE 03 30 33 B7 28 0C 3D 28 0B 3D C0 CD 09 22 3E 01 18 09 3E 01 CD 09 22; -20C8: CD 15 96 AF CD 18 96 20 1A CD 64 29 20 19 21 00 00 22 0F 96 22 11 96 3E; -20E0: 01 32 00 A0 AF 4F C9 3E 18 B7 C9 3E 08 B7 C9 3E 0A B7 C9 C9 C9 21 00 00; -20F8: 22 0F 96 22 11 96 18 32 21 00 A0 54 5D 13 36 00 01 8D 00 ED B0 AF C9 CD; -2110: 9E 27 28 14 22 0F 96 ED 53 11 96 D9 CD 2C 21 2A 3D A0 ED 5B 3F A0 AF C9; -2128: 3E 01 B7 C9 21 0F 96 C3 1F 24 21 0F 96 C3 70 22 CD 5D 21 CD 1F 28 20 10; -2140: 22 0F 96 ED 53 11 96 E5 D5 CD 2C 21 D1 E1 AF C9 3E 02 B7 C9 CD 5D 21 CD; -2158: 40 28 20 F4 C9 E5 D5 C5 CD 81 21 C1 D1 E1 C9 CD 9E 27 28 BC 22 0F 96 ED; -2170: 53 11 96 3E E5 02 CD 0D 28 21 0F 96 CD 1C 27 AF C9 16 00 3E 02 CD E8 21; -2188: 5F CB 23 CB 12 CB 23 CB 12 CB 23 CB 12 CB 23 CB 12 CB 23 CB 12 AF CD E8; -21A0: 21 CB 3F B3 5F 3E 04 CD E8 21 CB 27 CB 27 CB 27 B2 57 ED 53 2F A0 ED 53; -21B8: 37 A0 3E 09 CD E8 21 C6 14 57 3E 08 CD E8 21 CB 27 CB 27 CB 27 CB 27 CB; -21D0: 27 CB 12 5F 3E 07 CD E8 21 B3 5F ED 53 31 A0 ED 53 33 A0 ED 53 39 A0 C9; -21E8: 01 F7 DF ED 79 06 BF ED 78 4F E6 0F 47 CB 39 CB 39 CB 39 CB 39 79 81 81; -2200: 81 81 81 81 81 81 81 80 C9 21 27 22 B7 28 03 21 1B 22 11 15 96 01 0C 00; -2218: ED B0 C9 C3 41 2C C3 23 2D C3 44 2C C3 70 2C C9 C9 C9 C3 30 2F C3 AE 2E; -2230: C3 D4 2E 11 21 A0 06 08 CD 5F 22 CD 50 22 CC 05 2C 7E FE 2E 20 01 23 06; -2248: 03 CD 50 22 CC 05 2C C9 7E B7 C8 FE 2E 23 C8 12 13 10 F5 3E 01 B7 C9 7E; -2260: FE 2E C0 12 23 13 05 7E FE 2E C0 12 23 13 05 C9 11 81 A0 01 04 00 ED B0; -2278: C9 21 81 A0 01 04 00 ED B0 C9 3E 03 32 00 96 C3 C0 22 ED 43 0B 96 EB 7C; -2290: E6 3F 67 3E 01 32 00 96 CD C0 22 ED 4B 0B 96 EB C9 3E 01 32 00 96 C3 C0; -22A8: 22 ED 43 0B 96 EB 7C E6 3F 67 3E 02 32 00 96 CD C0 22 ED 4B 0B 96 EB C9; -22C0: AF 32 03 A0 CD D4 22 20 04 78 CD ED 22 2A 69 A0 3A 02 A0 C9 22 69 A0 3A; -22D8: 02 A0 B7 C0 3A 01 A0 B7 20 09 C5 21 61 A0 CD 1F 24 C1 C9 AF C9 32 04 A0; -22F0: 2A 1D A0 ED 5B 1F A0 CD CB 2B 21 04 A0 3A 4D A0; -2300: ED 4B 01 A0 91 47 7E B7 C8 90 30 03 80 47 AF 77 78 32 05 A0 2A 69 A0 CD; -2318: 5D 23 22 69 A0 21 1D A0 11 19 A0 01 04 00 ED B0 2A 1D A0 ED 5B 1F A0 ED; -2330: 4B 05 A0 09 30 01 13 22 1D A0 ED 53 1F A0 21 01 A0 79 86 77 ED 4B 4D A0; -2348: B9 DA F0 22 2A 61 A0 ED 5B 63 A0 CD D5 23 CD 1F 24 CA F0 22 C9 ED 4B 00; -2360: 96 0D CA 1B 96 0D CA 1E 96 0D C8 C9 21 53 A0 11 07 A0 01 04 00 ED B0 2A; -2378: 07 A0 ED 5B 09 A0 CD D5 23 D8 7E 23 B6 23 B6 23 B6 23 28 37 EB 21 07 A0; -2390: 34 C2 9E 23 23 34 20 06 23 34 20 02 23 34 EB 7C FE 92 DA 82 23 2A 1D A0; -23A8: ED 5B 1F A0 23 7C B5 20 01 13 CD C4 2B 21 00 90 3E 01 CD 1B 96 21 00 90; -23C0: C3 82 23 D9 2A 07 A0 ED 5B 09 A0 E5 21 07 A0 CD 57 2B E1 AF C9 CD FF 2A; -23D8: CB 21 CB 10 CB 21 CB 10 C5 ED 53 0D A0 22 0B A0 ED 4B 4B A0 7A B8 38 10; -23F0: 7B B9 38 0C ED 4B 49 A0 7C B8 38 04 7D B9 30 1C ED 4B 5B A0 CD 5F 2B CD; -2408: 71 24 CD C4 2B 21 00 90 3E 01 CD 1B 96 C1 21 00 90 09 AF C9 C1 37 C9 CD; -2420: BC 2B 5E 23 56 23 7E 23 66 6F B4 B3 B2 28 34 7C E6 0F FE 0F 28 36 EB 22; -2438: 61 A0 ED 53 63 A0 01 02 00 B7 ED 42 30 01 1B 3A 4D A0 CD 45 2B ED 4B 5D; -2450: A0 CD 5F 2B EB ED 4B 5F A0 09 EB CD 71 24 CD C4 2B AF C9 2A 4F A0 ED 5B; -2468: 51 A0 18 CB 32 02 A0 B7 C9 ED 4B 57 A0 ED 43 15 A0 ED 4B 59 A0 ED 43 17; -2480: A0 C3 63 2B 21 21 A0 CD 62 25 2A 81 A0 ED 5B 83 A0 22 61 A0 ED 53 63 A0; -2498: CD BC 2B 21 00 92 06 01 CD A1 22 21 00 92 11 20 00 06 10 AF BE CA 2E 25; -24B0: 19 10 F9 3A 02 A0 FE 0F 20 E1 CD 6C 23 38 6B 22 7D A0 ED 53 7F A0 D9 3E; -24C8: FF 2B 36 0F 2B 77 2B 77 2B 77 21 00 90 3E 01 CD 1E 96 2A 61 A0 ED 5B 63; -24E0: A0 CD D5 23 38 44 EB 21 7D A0 01 04 00 ED B0 21 00 90 3E 01 CD 1E 96 21; -24F8: 7D A0 CD 1F 24 C0 21 00 90 54 5D 13 36 00 01 FF 01 ED B0 2A 1D A0 ED 5B; -2510: 1F A0 E5 D5 21 00 90 3E 01 CD 1E 96 3A 4D A0 CD D3 2B D1 E1 CD C4 2B C3; -2528: 9B 24 3E 01 B7 C9 EB 2A 79 A0 22 3B A0 2A 7B A0 22 35 A0 21 21 A0 01 21; -2540: 00 ED B0 7A 32 70 A0 2A 19 A0 ED 5B 1B A0 CD CB 2B 21 00 92 3E 01 CD 1E; -2558: 96 2A 79 A0 ED 5B 7B A0 AF C9 E5 06 0B 7E FE 21 28 3D FE 2D 28 39 FE 2A; -2570: 30 04 FE 23 30 31 FE 30 38 08 FE 3A 38 08 FE 40 30 04 36 5F 18 21 FE 5B; -2588: 28 F8 FE 5C 28 F4 FE 5D 28 F0 FE 61 38 11 FE 7B 38 0A FE 7C 28 E4 FE F2; -25A0: 30 E0 18 03 D6 20 77 23 10 BB E1 E5 01 07 00 09 06 07 CD C0 25 E1 01 0A; -25B8: 00 09 06 03 CD C0 25 C9 7E FE 5F C0 36 20 2B 10 F7 C9 21 79 A0 CD 1C 27; -25D0: 21 79 A0 11 53 A0 01 04 00 ED B0 3E 01 B7 C9 CD 17 2B 3A 4D A0 CD 26 2B; -25E8: ED 53 77 A0 22 75 A0 CD 04 26 38 E7 CD 34 26 38 D1 CD 8C 26 C8 CD 2E 26; -2600: 38 C8 18 F0 21 00 80 22 02 96 CD 6C 23 D8 22 79 A0 ED 53 7B A0 22 53 A0; -2618: ED 53 55 A0 7C 4D 2A 02 96 71 23 77 23 73 23 72 23 22 02 96 AF C9 CD 77; -2630: 23 D8 18 E1 2A 75 A0 2B 22 75 A0 7C B5 28 2D D9 7C FE 92 38 06 CD 77 23; -2648: D8 18 03 CD 82 23 22 53 A0 ED 53 55 A0 7C 4D 2A 02 96 71 23 77 23 73 23; -2660: 72 23 7C FE 90 D0 22 02 96 C3 34 26 2A 77 A0 7C B5 20 12 11 FF 0F 2A 02; -2678: 96 73 23 73 23 73 23 72 23 22 02 96 C9 2B 22 77 A0 C3 3F 26 21 00 80 4E; -2690: 23 46 23 5E 23 56 23 E5 60 69 CD D5 23 EB E1 22 71 A0 01 04 00 ED B0 2B; -26A8: 7E FE 0F 28 4F 23 7C FE 90 30 53 2A 71 A0 4E 23 46 23 5E 23 56 23 22 73; -26C0: A0 60 69 CD FF 2A ED 4B 0B A0 B7 ED 42 20 0A EB ED 4B 0D A0 B7 ED 42 28; -26D8: 0E 21 00 90 3E 01 CD 1E 96 2A 71 A0 C3 8F 26 26 00 6F CB 25 CB 14 CB 25; -26F0: CB 14 01 00 90 09 EB 2A 73 A0 18 A3 21 00 90 3E 01 CD 1E 96 AF C9 CD FC; -2708: 26 2A 71 A0 11 00 80 01 04 00 ED B0 ED 53 02 96 3E 01 B7 C9 11 00 92 01; -2720: 04 00 ED B0 21 00 00 22 53 A0 22 55 A0 2A 00 92 ED 5B 02 92 7A FE 0F C8; -2738: B3 B4 B5 C8 CD D5 23 D8 11 00 92 0E 00 7E 71 12 2C 1C 7E 71 12 2C 1C 7E; -2750: 71 12 2C 1C 7E 71 12 2A 00 92 ED 5B 02 92 7A FE 0F 28 33 CD FF 2A ED 4B; -2768: 0B A0 B7 ED 42 20 1C EB ED 4B 0D A0 B7 ED 42 20 12 26 00 6F CB 25 CB 14; -2780: CB 25 CB 14 01 00 90 09 C3 40 27 21 00 90 3E 01 CD 1E 96 C3 2D 27 21 00; -2798: 90 3E 01 C3 1E 96 7E 23 32 2C A0 CD 33 22 21 81 A0 11 61 A0 01 04 00 ED; -27B0: B0 CD BC 2B 3A 02 A0 FE 0F C8 21 00 92 06 01 CD A1 22 36 00 21 E0 91 CD; -27C8: CD 27 C0 18 E7 01 20 00 09 7E B7 C8 CD DD 27 20 F4 3E 01 B7 C9 E5 11 21; -27E0: A0 06 0B CD 05 28 CC FE 27 E1 C0 E5 11 21 A0 01 20 00 ED B0 C1 2A 3B A0; -27F8: ED 5B 35 A0 AF C9 1A 4F 7E E6 10 B9 C9 1A BE C0 23 13 10 F9 C9 2A 19 A0; -2810: ED 5B 1B A0 CD CB 2B 21 00 92 3E 01 C3 1E 96 ED 53 3D A0 ED 43 3F A0 7E; -2828: 32 2C A0 23 CD 33 22 2A 3D A0 ED 5B 3F A0 CD DF 25 C0 CD 84 24 C0 AF C9; -2840: CD 33 22 21 00 00 22 3D A0 22 3F A0 3E 10 32 2C A0 11 00 00 21 00 02 CD; -2858: DF 25 C0 CD 84 24 C0 21 79 A0 CD 1F 24 21 21 A0 36 2E 23 36 20 23 3E 20; -2870: 06 09 CD 00 2C 2A 61 A0 22 3B A0 2A 63 A0 22 35 A0 21 21 A0 11 00 92 01; -2888: 20 00 ED B0 21 22 A0 36 2E 2A 81 A0 22 3B A0 2A 83 A0 22 35 A0 21 21 A0; -28A0: 01 20 00 ED B0 62 6B 13 01 BF 01 36 00 ED B0 21 00 92 3E 01 CD 1E 96 3A; -28B8: 4D A0 CD D3 2B AF C9 2A 44 A0 ED 5B 46 A0 CD C4 2B 21 00 92 3E 01 CD 1B; -28D0: 96 21 53 A0 11 EC 93 01 04 00 ED B0 21 00 92 3E 01 CD 1E 96 C9 ED 43 04; -28E8: 96 ED 53 08 96 22 06 96 CD 2F 29 C8 CD 10 29 ED 5B 04 96 B7 ED 52 D0 2A; -2900: 06 96 5E 23 56 23 7E 23 66 6F EB CD D5 23 18 DD 44 4D 3A 4D A0 2A 08 96; -2918: 71 23 70 23 73 23 72 23 22 08 96 3D C8 03 08 78 B1 20 01 13 08 18 E9 5E; -2930: 23 56 23 7E 23 66 6F B4 B3 B2 C8 7C FE 0F C8 EB 01 02 00 B7 ED 42 30 01; -2948: 1B 3A 4D A0 CD 45 2B ED 4B 5D A0 CD 5F 2B EB ED 4B 5F A0 09 EB CD 71 24; -2960: 3E 01 B7 C9 21 00 00 54 5D 22 61 A0 22 63 A0 22 06 96 22 08 96 22 6C A0; -2978: 22 6E A0 CD C4 2B 21 00 92 3E 01 CD 1B 96 3E 03 32 6B A0 32 0A 96 21 C2; -2990: 93 11 10 00 06 04 7E FE 05 28 72 FE 0B 28 6E FE 0C 28 6A FE 0F 28 66 19; -29A8: 10 EC 3A 0A 96 B7 CA FB 2A ED 5B 08 96 2A 06 96 CD C4 2B 21 00 92 3E 01; -29C0: CD 1B 96 21 6B A0 35 CA ED 2A 21 CE 93 06 10 AF B6 23 10 FC C2 ED 2A 2A; -29D8: D6 93 ED 5B D8 93 22 15 A0 ED 53 17 A0 2A 06 96 ED 5B 08 96 CD 63 2B ED; -29F0: 53 08 96 22 06 96 CD C4 2B 21 00 92 3E 01 CD 1B; -2A00: 96 2A C6 93 ED 5B C8 93 CD 63 2B 18 0D 23 23 23 23 5E 23 56 23 7E 23 66; -2A18: 6F EB 22 57 A0 ED 53 59 A0 CD C4 2B 21 00 92 3E 01 CD 1B 96 2A 0B 92 7C; -2A30: 3D 3D B5 C2 AA 29 3A 0D 92 B7 CA AA 29 3A 0E 92 B7 CA AA 29 3A 10 92 B7; -2A48: CA AA 29 2A 11 92 7C B5 2A 16 92 B4 B5 C2 AA 29 2A 24 92 B4 B5 2A 26 92; -2A60: B4 B5 CA AA 29 3A 0D 92 32 4D A0 06 08 CB 3F 38 04 10 FA 3E 01 B7 C2 AA; -2A78: 29 2A 0E 92 22 42 A0 2A 30 92 11 00 00 CD 71 24 22 44 A0 ED 53 46 A0 3A; -2A90: 10 92 32 48 A0 2A 24 92 22 49 A0 2A 26 92 22 4B A0 2A 2C 92 22 4F A0 2A; -2AA8: 2E 92 22 51 A0 2A 49 A0 ED 5B 4B A0 ED 4B 48 A0 06 00 CD 7A 2B E5 D5 2A; -2AC0: 42 A0 22 5B A0 D1 C1 CD 5F 2B 22 5D A0 ED 53 5F A0 21 00 00 22 61 A0 22; -2AD8: 63 A0 22 81 A0 22 83 A0 21 53 A0 06 04 CD FF 2B CD BC 2B AF C9 2A 6C A0; -2AF0: ED 5B 6E A0 AF 32 0A 96 C3 1A 2A 3E 01 B7 C9 7D 08 7D 6C 63 5A 16 00 17; -2B08: CB 15 CB 14 CB 13 CB 12 08 E6 7F 06 00 4F C9 7D 6C 63 5A 16 00 01 01 00; -2B20: B7 C4 5F 2B 3E 02 FE 02 D8 0E 00 CB 3F CB 3A CB 1B CB 1C CB 1D CB 19 CB; -2B38: 3F 30 F2 79 B7 C8 01 01 00 CD 5F 2B C9 FE 02 D8 CB 3F CB 25 CB 14 CB 13; -2B50: CB 12 CB 3F 30 F4 C9 06 04 34 C0 23 10 FB C9 09 D0 13 C9 EB ED 4B 17 A0; -2B68: 09 EB ED 4B 15 A0 09 30 01 13 22 15 A0 ED 53 17 A0 C9 78 41 4F 0C B7 20; -2B80: 04 05 28 2C 04 AF B8 20 01 0D 05 E5 C5 62 6B B8 28 04 19 10 FD 47 0D 20; -2B98: F9 22 0F A0 C1 E1 54 5D B8 28 06 19 38 0B 10 FB 47 0D 20 F7 ED 5B 0F A0; -2BB0: C9 D9 2A 0F A0 23 22 0F A0 D9 18 EA AF 32 01 A0 32 02 A0 C9 22 1D A0 ED; -2BC8: 53 1F A0 22 89 A0 ED 53 8B A0 C9 21 00 90 54 5D 13 36 00 01 FF 01 ED B0; -2BE0: 3D C8 F5 2A 1D A0 ED 5B 1F A0 01 01 00 09 30 01 13 CD C4 2B 21 00 90 3E; -2BF8: 01 CD 1E 96 F1 18 E1 AF 77 23 10 FC C9 3E 20 12 13 10 FC C9 7C 0E F7 FE; -2C10: 80 30 04 ED 4B 0B 96 E6 3F 57 79 01 AF 27 ED 70 FA 1E 2C C9 11 00 02 19; -2C28: 7C FE 40 38 0E FE 80 30 0A E6 3F 67 3A 0B 96 3C 32 0B 96 ED 70 FA 3B 2C; -2C40: C9 C3 C0 2D ED 5B 89 A0 ED 4B 8B A0 08 3E 52 CD 07 2E 08 08 CD 4B 2E FE; -2C58: FE 20 F9 CD B1 2C 08 3D 20 F1 3E 4C CD ED 2D CD 4B 2E 3C 20 FA C3 A8 2D; -2C70: ED 5B 89 A0 ED 4B 8B A0 08 AF DB 77 E6 02 C0 78 B1 B2 B3 3E 03 C8 3E 59; -2C88: CD 07 2E CD 4B 2E 3C 20 FA 08 08 3E FC CD DD 2C CD 4B 2E 3C 20 FA 08 3D; -2CA0: 20 F0 0E 57 3E FD ED 79 CD 4B 2E 3C 20 FA C3 A8 2D C5 D5 CD 0C 2C 06 1F; -2CB8: ED 79 05 ED 51 05 ED 69 06 28 AF ED 79 06 26 3D ED 79 06 27 3E 02 ED 79; -2CD0: CD 24 2C 01 57 00 ED 78 ED 78 D1 C1 C9 C5 D5 01 57 00 ED 79 CD 0C 2C 06; -2CE8: 1C ED 79 05 ED 51 05 ED 69 06 28 AF ED 79 06 26 3D ED 79 06 27 3E 82 ED; -2D00: 79 CD 24 2C 01 57 00 3E FF ED 79 00 ED 79 D1 C1 C9 40 00 00 00 00 95 48; -2D18: 00 00 01 AA 87 50 00 00 02 00 FF B7 C0 CD 31 2D 11 02 00 B7 C0 11 00 00; -2D30: C9 CD A8 2D 01 57 00 11 FF 10 ED 59 15 20 FB AF 08 21 11 2D CD D2 2D CD; -2D48: 4B 2E 08 3D 28 6C 08 3D 20 EF 21 17 2D CD D2 2D CD 4B 2E ED 60 00 ED 60; -2D60: 00 ED 60 00 ED 60 21 00 00 CB 57 20 02 26 40 3E 77 CD ED 2D CD 4B 2E 3E; -2D78: 69 ED 79 00 ED 61 00 ED 69 00 ED 69 00 ED 69 3E FF ED 79 CD 4B 2E A7 20; -2D90: DE 3E 7B CD ED 2D CD 4B 2E A7 20 F5 21 1D 2D CD D2 2D CD 4B 2E A7 20 F4; -2DA8: D5 C5 1E 03 01 77 00 ED 59 1E 00 0E 57 ED 59 C1 D1 C9 CD C0 2D 3E 01 C9; -2DC0: AF D3 77 D3 57 C9 D5 C5 01 77 00 1E 01 ED 59 C1 D1 C9 CD C6 2D C5 01 57; -2DD8: 00 ED A3 00 ED A3 00 ED A3 00 ED A3 00 ED A3 00 ED A3 00 C1 C9 C5 CD C6; -2DF0: 2D 01 57 00 ED 79 AF ED 79 00 ED 79 00 ED 79 00 ED 79 3D ED 79 C1 C9 E5; -2E08: D5 C5 F5 C5 01 57 00 3E 7A CD ED 2D CD 4B 2E ED 78 00 ED 60 00 ED 60 00; -2E20: ED 60 CB 77 E1 20 0A EB 29 EB ED 6A 65 6A 53 1E 00 F1 01 57 00 ED 79 00; -2E38: ED 61 00 ED 69 00 ED 51 00 ED 59 3E FF ED 79 C1 D1 E1 C9 C5 D5 11 FF 10; -2E50: 01 57 00 ED 78 BB 20 03 15 20 F8 D1 C1 C9 01 F0 00 ED 79 C9 01 F0 00 ED; -2E68: 79 C9 01 F0 00 ED 78 C9 E5 D5 2A 89 A0 ED 5B 8B A0 7C 62 53 5F 7C E6 0F; -2E80: 67 3A 8D A0 B4 01 D0 FF ED 79 0E 70 ED 69 0E B0 ED 51 0E 90 ED 59 D1 E1; -2E98: C9 01 D0 FF ED 78 E6 0F 67 0E 70 ED 68 0E B0 ED 50 0E 90 ED 58 C9 08 CD; -2EB0: 09 2F 08 01 50 00 ED 79 08 CD 70 2E 3E 20 CD 5E 2E CD FA 2E 08 08 CD 01; -2EC8: 2F CD 85 2F CD FA 2E 08 3D 20 F2 C9 08 CD 09 2F 08 01 50 00 ED 79 08 CD; -2EE0: 70 2E 3E 30 CD 5E 2E CD FA 2E 08 08 CD 01 2F CD A5 2F CD FA 2E 08 3D 20; -2EF8: F2 C9 CD 6A 2E 07 D0 18 F9 CD 6A 2E E6 08 C0 18 F8 CD 6A 2E E6 C0 FE 40; -2F10: C8 18 F6 CD 6A 2E 0F C9 3E B0 32 8D A0 01 D0 00 ED 79 CD 6A 2E 07 C9 3E; -2F28: E0 18 EF CD 18 2F 18 09 FE 02 D0 3D 28 F5 CD 27 2F 3E 08 CD 64 2E 2E 20; -2F40: CD 6A 2E 07 30 12 CD 13 2F 38 0D 06 01 CD 41 20 2D 20 ED 11 F4 01 18 1E; -2F58: 11 00 00 62 6B CD C4 2B CD 70 2E 01 F0 00 3E EC ED 79 06 04 CD 41 20 CD; -2F70: 99 2E 7A B3 28 04 3E 01 B7 C9 21 00 92 CD 85 2F 11 00 00 AF C9 CD 0C 2C; -2F88: 06 1F ED 79 05 ED 51 05 ED 69 06 28 AF ED 79 06 26 3D ED 79 06 27 3E 03; -2FA0: ED 79 C3 24 2C CD 0C 2C 06 1C ED 79 05 ED 51 05 ED 69 06 28 AF ED 79 06; -2FB8: 26 3D ED 79 06 27 3E 83 ED 79 C3 24 2C FF FF FF FF FF FF FF FF FF FF FF; -2FD0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -2FE8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3000: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3018: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3030: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3048: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3060: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3078: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3090: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -30A8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -30C0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -30D8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -30F0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3100: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3118: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3130: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3148: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3160: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3178: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3190: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -31A8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -31C0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -31D8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -31F0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3208: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3220: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3238: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3250: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3268: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3280: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3298: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -32B0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -32C8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -32E0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -32F8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3310: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3328: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3340: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3358: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3370: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3388: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -33A0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -33B8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -33D0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -33E8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3400: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3418: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3430: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3448: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3460: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3478: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3490: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -34A8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -34C0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -34D8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -34F0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3508: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3520: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3538: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3550: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3568: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3580: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3598: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -35B0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -35C8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -35E0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -35F8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3610: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3628: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3640: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3658: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3670: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3688: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -36A0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -36B8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -36D0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -36E8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3700: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3718: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3730: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3748: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3760: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3778: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3790: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -37A8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -37C0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -37D8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -37F0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3800: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3818: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3830: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3848: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3860: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3878: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3890: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -38A8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -38C0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -38D8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -38F0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3908: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3920: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3938: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3950: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3968: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3980: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3998: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -39B0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -39C8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -39E0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -39F8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3A10: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3A28: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3A40: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3A58: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3A70: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3A88: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3AA0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3AB8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3AD0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3AE8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3B00: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3B18: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3B30: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3B48: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3B60: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3B78: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3B90: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3BA8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3BC0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3BD8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3BF0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3C08: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3C20: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3C38: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3C50: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3C68: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3C80: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3C98: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3CB0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3CC8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3CE0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3CF8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3D10: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3D28: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3D40: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3D58: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3D70: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3D88: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3DA0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3DB8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3DD0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3DE8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3E00: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3E18: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3E30: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3E48: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3E60: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3E78: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3E90: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3EA8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3EC0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3ED8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3EF0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3F00: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3F18: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3F30: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3F48: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3F60: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3F78: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3F90: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3FA8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3FC0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3FD8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -3FF0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F3 11 FF FF 3E 07 18 01; -4008: 00 D3 FE 3E 3F 18 04 00 C3 82 3D ED 47 C3 1B 00 C3 07 27 00 00 00 18 04; -4020: C3 72 2F C9 62 6B 18 03 C3 23 23 36 02 2B BC 20 FA 18 07 FF FF FF FF FF; -4038: FB C9 B7 ED 52 19 23 30 06 35 28 03 35 28 F3 2B 22 B4 5C 11 AF 3E 01 A8; -4050: 00 7B EB 31 00 60 22 00 5F 21 79 00 E5 21 2F 3D E5 21 ED B8 18 03 C3 56; -4068: 2A 22 10 5F F5 3E C9 32 12 5F F1 2A 00 5F C3 10 5F EB 23 22 7B 5C 2B 01; -4080: 40 1E ED 43 38 5C 22 B2 5C 21 00 3C 22 36 5C 2A B2 5C 36 3E 2B F9 2B 2B; -4098: 22 3D 5C 11 03 13 D5 ED 56 FD 21 3A 5C 21 B6 5C 22 4F 5C 11 AF 15 01 15; -40B0: 00 EB CD 17 01 EB 2B 22 57 5C 23 22 53 5C 22 4B 5C 36 80 23 22 59 5C 36; -40C8: 0D 23 36 80 23 22 61 5C 22 63 5C 22 65 5C 3E 38 32 8D 5C 32 8F 5C 32 48; -40E0: 5C 21 23 05 22 09 5C FD 35 C6 FD 35 CA 21 C6 15 11 10 5C 01 0E 00 CD 17; -40F8: 01 FD CB 01 CE 21 C2 5C 36 C9 E7 DF 0E 21 6B 5C 36 02 21 8B 12 E5 3E AA; -4110: 32 00 5B FB C3 31 3D 22 00 5F 21 2F 3D E5 21 ED B0 22 10 5F 2A 00 5F C3; -4128: 10 5F CD E5 20 CD 97 1D 2A 59 5C 23 5E 23 56 7A B3 EB 28 04 AF 32 10 5D; -4140: E5 CD 32 02 E1 22 42 5C AF 32 44 5C E7 B0 16 2A 53 5C 2B 22 57 5C ED 7B; -4158: 3D 5C 3A 10 5D B7 21 76 1B 28 03 E7 B0 1B E5 21 C2 5C E5 C9 CD F1 20 CD; -4170: 4A 29 3E FF 32 15 5D AF 32 F7 5C 3E AA 32 17 5D 21 01 02 22 1A 5D 21 00; -4188: 00 39 22 1C 5D 2B 2B F9 CD 1D 02 2A B2 5C ED 5B 5D 5C ED 52 EB 30 06 B7; -41A0: 11 01 01 ED 52 22 5D 5C CD C7 01 CA D3 01 FE EA 23 20 F5 CD C7 01 28 F3; -41B8: FE 3A C2 D3 01 23 CD 48 30 2A 11 5D C3 0A 03 7E FE 0D C8 FE 80 C8 B7 C9; -41D0: CD 43 1E 21 00 00 22 F8 5C CD E5 20 CD 63 1D 21 17 5D 36 AA 21 1F 5D 7E; -41E8: B7 36 00 20 06 CD 1C 1E CD 12 02 ED 7B 1C 5D 2A 1A 5D ED 4B 0F 5D 06 00; -4200: E9 CD 32 02 FD CB 00 7E C0 11 C2 5C ED 7B 3D 5C D5 C9 CD 8C 1D FE 0D C8; -4218: CD 2A 1E 18 F5 2A 3D 5C 22 13 5D 2A 1C 5D 2B 2B 22 3D 5C 11 16 3D 73 23; -4230: 72 C9 2A 13 5D 22 3D 5C C9 21 00 00 22 F7 5C 39 22 1C 5D 2B 2B F9 CD 1D; -4248: 02 21 17 5D 7E FE AA 3E 00 32 0F 5D CA CB 02 36 AA CD 97 1D CD 88 1D 21; -4260: 60 03 DF CD 6E 10 3A B6 5C FE F4 28 04 21 00 10 DF 3A 00 5B FE AA 20 53; -4278: CD F1 20 2A 59 5C 3E FE 32 0E 5D 36 F7 23 36 22 23 36 62 23 36 6F 23 36; -4290: 6F 23 36 74 23 36 22 23 22 5B 5C 36 0D 23 36 80 23 22 61 5C 22 63 5C 22; -42A8: 65 5C FD CB 01 DE 18 3F 06 03 7E 12 23 13 10 FA C9 06 20 C5 EE 08 D3 FF; -42C0: F5 3E 05 CD FF 3D F1 C1 10 F1 C9 2A 1C 5D 2B 2B F9 CD F1 20 CD 83 1D 3A; -42D8: 16 5D F6 03 CD B9 02 3A 16 5D CD B9 02 AF 32 15 5D CD 35 21 CD 32 30 CD; -42F0: 9F 1D 21 CB 02 22 1A 5D AF 32 0F 5D 2A 59 5C E5 11 20 5D CD B0 02 E1 22; -4308: 11 5D 7E 47 E6 80 78 28 09 FE FE 28 05 F5 CD C8 3D F1 21 F3 2F 2B 0E 00; -4320: 0C 57 3E 15 B9 DA D3 01 7A 23 BE 20 F3 FE FE C4 4A 29 3E 09 32 06 5D AF; -4338: 32 0F 5D 32 D6 5C 32 10 5D 21 3B 5C CB BE 06 00 21 08 30 0D CB 21 09 5E; -4350: 23 56 EB E5 11 59 03 D5 E9 21 3B 5C CB FE E1 E9 16 01 05 2A 20 54 52 2D; -4368: 44 4F 53 20 56 65 72 20 35 2E 30 34 54 2A 0D 0D 7F 20 31 39 38 36 20 54; -4380: 65 63 68 6E 6F 6C 6F 67 79 20 52 65 73 65 61 72 63 68 20 4C 74 64 2E 16; -4398: 05 0B 28 55 2E 4B 2E 29 16 07 05 42 45 54 41 20 31 32 38 00 CD FD 03 CD; -43B0: 80 3D CD 80 3D ED 4B 0A 5E CD A9 1D 21 D2 29 DF C3 D3 01 F5 3A 0E 5D FE; -43C8: FE 20 02 F1 C9 F1 32 0F 5D 3A 15 5D B7 CC 07 27 C9 21 28 2A 3E 01 C3 4A; -43E0: 1C 21 66 27 AF C3 4A 1C AF 32 CC 5C ED 5B CC 5C 16 00 CD 4A 29 21 25 5D; -43F8: 06 01 C3 3D 1E CD 4A 29 11 08 00 18 ED CD FD 03 3A 0C 5E FE 10 28 06 21; -4410: E2 29 DF 18 AB CD 11 3E CB 86 CB 8E 3A 08 5E CB 47 20 02 CB C6 CB 5F C0; -4428: CB CE C9 2A 11 5D 23 7E FE 0D C9 CD 2B 04 01 02 00 ED 43 DB 5C 28 2B FE; -4440: 23 20 1A 22 5D 5C CD 0B 1E CD 8C 1D FE 0D 28 1A FE 2C C2 1A 1D CD 2A 1E; -4458: CD BD 1D 18 03 CD DF 1D CD 75 1D CD B5 1D EB CD 81 1C CD 75 1D 3A F6 5C; -4470: 32 F9 5C CD 05 04 3A DB 5C FE 02 F5 CC 97 1D F1 FE 11 D2 1A 1D CD 84 1D; -4488: 3E FF 32 F8 5C 21 F7 29 DF 21 1A 5E DF CD 80 3D 3A 09 5E 21 19 5E 96 E5; -44A0: CD A3 1D 21 2B 2A DF E1 4E CD A4 1D 21 1D 2A DF CD E8 03 21 25 5D CD F6; -44B8: 04 CD 80 3D 3A F6 5C C6 41 D7 06 02 CD F6 04 C5 3E 3A D7 E5 CD 38 29 01; -44D0: 0D 00 E1 E5 09 4E C5 79 06 02 FE 0A 38 01 05 FE 64 30 05 3E 20 D7 10 FB; -44E8: C1 CD A9 1D E1 C1 11 10 00 19 10 D0 18 C0 E5 C5 3A F9 5C 21 F6 5C BE C4; -4500: CB 3D C1 E1 C3 C6 2F 11 10 00 19 C9 E5 C5 01 DB A1 09 38 03 C1 E1 C9 21; -4518: CC 5C 34 CD EC 03 C1 E1 21 25 5D C9 E6 DF DE 41 DA 1A 1D FE 04 D2 1A 1D; -4530: C9 CD B5 1D 79 B8 CA 1A 1D C9 CD CD 1D CD 75 1D CD 2E 10 CD B0 1C 3A F6; -4548: 5C 32 F8 5C C2 D9 03 C5 CD 5D 16 CD B0 1C F5 3A F8 5C 21 F6 5C BE C2 1A; -4560: 1D CD 05 04 F1 CA 50 1C C1 CD 6B 16 CD 43 1E C3 E1 03 3A 10 5D B7 C9 3A; -4578: 07 5D B7 CA D9 03 C3 E1 03 C5 CD 97 1D 3A F6 5C C6 41 CD 82 3D 3E 3A CD; -4590: 82 3D 21 DD 5C CD 38 29 21 20 28 CD 07 27 CD 52 10 FE 59 F5 CD 97 1D F1; -45A8: C1 C0 C5 CD 97 1D C1 CD 81 07 AF C9 3A E5 5C FE 23 28 02 AF C9 3E 0A 32; -45C0: 06 5D CD B3 1C 3E 09 32 06 5D C9 3A DD 5C FE 2A C2 D9 03 CD B5 1D EB CD; -45D8: 81 1C 7E FE 2A C2 1A 1D 3A F6 5C 32 F9 5C 3A F9 5C CD CB 3D CD 05 04 3E; -45F0: FF 32 0D 5D 3A F8 5C CD CB 3D CD 05 04 3A 0D 5D; -4600: 3C 32 0D 5D 4F CD 5D 16 3A DD 5C FE 00 CA E1 03 FE 01 28 E0 21 E6 5C 11; -4618: ED 5C 01 07 00 ED B0 3A F9 5C CD CB 3D CD B3 1C 20 0A CD B4 05 20 05 CD; -4630: 81 05 20 C0 CD 3C 06 CD 43 1E 18 B8 CD FD 03 3A 09 5E FE 80 CA 45 1C 21; -4648: ED 5C 11 E6 5C 01 07 00 ED B0 ED 5B EA 5C 16 00 B7 2A 0A 5E ED 52 DA 45; -4660: 1C 22 0A 5E 2A 06 5E 22 EB 5C E5 CD 2F 07 E1 22 EB 5C 2A F4 5C 22 06 5E; -4678: 21 09 5E 34 4E 0D 06 00 C5 11 09 00 ED 53 F4 5C CD 43 1E C1 CD 6B 16 C9; -4690: 2A 11 5D 23 7E E6 DF FE 53 CA 60 13 FE 42 CA 2C 15 CD CD 1D CD 75 1D CD; -46A8: 6F 16 CD 2E 10 CD B0 1C 3A F6 5C 32 F8 5C C2 CB 05 CD 5D 16 21 E6 5C 11; -46C0: ED 5C 01 07 00 ED B0 CD B0 1C F5 C5 3A F6 5C 32 F9 5C 3A F8 5C CD CB 3D; -46D8: CD 05 04 3A F9 5C CD CB 3D CD 05 04 C1 F1 20 0B CD B4 05 20 06 CD 81 05; -46F0: C2 E1 03 CD 3C 06 CD 43 1E 3A E5 5C FE 23 C2 E1 03 3E 0A 32 06 5D 21 E6; -4708: 5C 34 3A F8 5C CD CB 3D CD B4 05 C2 E1 03 CD 5D 16 21 E6 5C 11 ED 5C 01; -4720: 07 00 ED B0 3A F9 5C CD CB 3D CD 05 04 18 C4 3A F1 5C B7 C8 E5 21 23 5D; -4738: 96 E1 30 39 3A F1 5C 47 AF 32 F1 5C C5 3A F8 5C CD CB 3D C1 C5 2A CF 5C; -4750: E5 ED 5B F2 5C CD 3D 1E 2A F4 5C 22 F2 5C 3A F9 5C CD CB 3D E1 C1 ED 5B; -4768: EB 5C CD 4D 1E 2A F4 5C 22 EB 5C 18 BA 32 F1 5C E5 21 23 5D 46 E1 AF 18; -4780: C3 AF 32 07 5D 18 19 CD DF 1D CD 75 1D CD 2E 10 AF 32 07 5D CD 2F 29 CD; -4798: A0 07 C2 77 05 C3 E1 03 3A DD 5C 32 08 5D C0 21 07 5D 34 C5 CD FD 03 3A; -47B0: 09 5E C1 0C B9 20 05 3D 32 09 5E AF F5 28 04 21 19 5E 34 C5 CD 43 1E C1; -47C8: 0D CD 5D 16 F1 CA D2 07 3E 01 32 DD 5C F5 CD 40 1E 3A 08 5D 32 DD 5C F1; -47E0: 28 05 CD B3 1C 18 B9 CD FD 03 2A EB 5C 22 06 5E ED 5B EA 5C 2A 0A 5E 16; -47F8: 00 19 22 0A 5E C3 43 1E E6 FC C3 9A 3D FF 20 4D 65 73 73 61 67 65 20 66; -4810: 6F 72 20 68 61 63 6B 65 72 73 3A 20 42 61 73 65 20 76 65 72 73 69 6F 6E; -4828: 20 35 2E 30 33 2C 20 48 69 67 68 20 73 70 65 65 64 2C 20 54 75 72 62 6F; -4840: 20 66 6F 72 6D 61 74 2E 20 7F 43 6F 70 79 72 69 67 68 74 20 43 2E 43 2E; -4858: 20 31 39 39 31 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4870: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4888: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -48A0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -48B8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -48D0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -48E8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4900: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4918: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4930: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4948: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4960: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4978: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4990: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -49A8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -49C0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -49D8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -49F0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4A08: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4A20: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4A38: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4A50: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4A68: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4A80: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4A98: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4AB0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4AC8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4AE0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4AF8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4B10: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4B28: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4B40: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4B58: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4B70: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4B88: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4BA0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4BB8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4BD0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4BE8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4C00: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4C18: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4C30: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4C48: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4C60: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4C78: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4C90: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4CA8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4CC0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4CD8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4CF0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4D00: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4D18: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4D30: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4D48: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4D60: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4D78: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4D90: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4DA8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4DC0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4DD8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4DF0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4E08: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4E20: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4E38: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4E50: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4E68: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4E80: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4E98: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4EB0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4EC8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4EE0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4EF8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4F10: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4F28: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4F40: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4F58: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4F70: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4F88: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4FA0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4FB8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4FD0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -4FE8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -5000: 16 09 05 49 6E 74 65 72 66 61 63 65 20 6F 6E 65 20 66 69 74 74 65 64 00; -5018: CD DF 1D CD 75 1D CD 31 05 1A CD 24 05 32 19 5D CD CB 3D C3 E1 03 06 43; -5030: 3A D6 5C B7 20 17 CD 8C 1D FE AF 06 43 28 0E FE E4 06 44 28 08 FE 23 06; -5048: 23 28 02 06 42 21 E5 5C 70 C9 F3 E5 C5 D5 E7 8E 02 0E 00 20 F9 E7 1E 03; -5060: 30 F4 15 5F E7 33 03 D1 C1 E1 E6 DF FB C9 21 E5 58 06 0A 36 07 23 10 FB; -5078: 36 02 23 36 16 23 36 34 23 36 25 23 36 28 23 36 07 21 EE 40 06 08 AF C5; -5090: 37 17 E5 F5 06 05 23 77 10 FC F1 E1 C1 11 00 01 19 10 EC C9 C9 20 44 65; -50A8: 6C 2E 20 46 69 6C 65 28 73 29 00 54 69 74 6C 65 3A A0 17 11 20 44 69 73; -50C0: 6B 20 44 72 69 76 65 3A 20 00 17 10 20 00 17 10 20 34 30 20 54 72 61 63; -50D8: 6B 20 53 2E 20 53 69 64 65 00 17 10 20 38 30 20 54 72 61 63 6B 20 53 2E; -50F0: 20 53 69 64 65 00 17 10 20 34 30 20 54 72 61 63 6B 20 44 2E 20 53 69 64; -5108: 65 00 17 10 20 38 30 20 54 72 61 63 6B 20 44 2E 20 53 69 64 65 00 17 10; -5120: 20 46 72 65 65 20 53 65 63 74 6F 72 20 00 0D 0D 20 20 46 69 6C 65 20 4E; -5138: 61 6D 65 20 20 20 20 53 74 61 72 74 20 4C 65 6E 67 74 68 20 4C 69 6E 65; -5150: 00 2A 61 5C 22 CF 5C 01 22 02 C3 23 1E AF 11 10 27 ED 52 38 03 3C 18 F9; -5168: C6 30 CD A8 11 19 AF 11 E8 03 ED 52 38 03 3C 18 F9 C6 30 CD A8 11 19 AF; -5180: 11 64 00 ED 52 38 03 3C 18 F9 C6 30 CD A8 11 19 AF 11 0A 00 ED 52 38 03; -5198: 3C 18 F9 C6 30 CD A8 11 19 7D C6 30 CD A8 11 C9 E5 D5 CD 82 3D D1 E1 C9; -51B0: E5 C5 3A F9 5C 21 F6 5C BE C4 CB 3D C1 E1 CD 0C 05 7E B7 CA D3 01 FE 01; -51C8: CC 07 05 C0 18 E2 CD 2B 04 01 02 00 ED 43 DB 5C 28 2B FE 23 20 1A 22 5D; -51E0: 5C CD 0B 1E CD 8C 1D FE 0D 28 1A FE 2C C2 1A 1D CD 2A 1E CD BD 1D 18 03; -51F8: CD DF 1D CD 75 1D CD B5 1D EB CD 81 1C CD 75 1D 3A F6 5C 32 F9 5C CD 05; -5210: 04 3A DB 5C FE 02 F5 CC 97 1D F1 FE 11 D2 1A 1D CD 84 1D 3E FF 32 F8 5C; -5228: CD 51 11 21 06 5E ED 5B CF 5C 01 20 00 ED B0 CD E8 03 21 25 5D E5 21 B3; -5240: 10 C5 DF 2A CF 5C 01 14 00 09 DF 21 BA 10 DF 3A F6 5C C6 41 CD 82 3D CD; -5258: 80 3D 2A CF 5C 01 03 00 09 7E 2A CF 5C 01 13 00 09 96 E5 CD A3 1D 21 AA; -5270: 10 DF 2A CF 5C 01 02 00 09 7E 21 CE 10 FE 19 28 11 21 E2 10 FE 18 28 0A; -5288: 21 F6 10 FE 17 28 03 21 0A 11 DF E1 4E CD A4 1D 21 A5 10 DF 21 1E 11 DF; -52A0: 2A CF 5C 01 04 00 09 4E 23 46 CD A9 1D 21 2E 11 DF C1 E1 06 10 CD B0 11; -52B8: CD 80 3D C5 E5 CD 38 29 01 0D 00 E1 E5 09 4E C5 79 06 02 FE 0A 38 01 05; -52D0: FE 64 30 05 3E 20 D7 10 FB C1 CD A9 1D 21 CA 10 DF E1 E5 01 09 00 09 5E; -52E8: 23 56 E5 EB CD 5D 11 3E 20 CD 82 3D E1 23 5E 23 56 EB CD 5D 11 E1 E5 01; -5300: 08 00 09 7E FE 42 CC 1B 13 E1 C1 11 10 00 19 10 A4 E5 CD 80 3D CD 80 3D; -5318: C3 3E 12 01 05 00 09 46 23 5E 23 56 05 28 0E 05 28 0B 3E 10 1C BB 20 03; -5330: 1E 00 14 10 F7 2A CF 5C 01 21 00 09 06 02 E5 CD 3D 1E 3E 80 E1 01 00 02; -5348: ED B1 7E FE AA C0 23 4E 23 46 78 B1 C8 C5 3E 20 CD 82 3D C1 CD A9 1D C9; -5360: CD C5 1D CD 2A 1E CD BD 1D CD 75 1D CD 6F 16 21 AA 27 CD 07 27 CD 52 10; -5378: FE 59 20 F9 CD 9F 1D CD 2E 10 CD B0 1C C2 D9 03 CD B7 13 3A E5 5C FE 23; -5390: C2 E1 03 3E 0A 32 06 5D 21 E6 5C 34 CD 97 1D 21 AA 27 CD 07 27 CD 52 10; -53A8: FE 59 20 F9 CD B3 1C C2 E1 03 CD B7 13 18 DC CD 5D 16 21 E6 5C 11 ED 5C; -53C0: 01 07 00 ED B0 3A F1 5C 32 10 5D CD 05 04 CD 11 3E 32 D9 5C 3E FF 32 21; -53D8: 5D CD 51 14 2A 1F 5D 22 EB 5C 2A F4 5C 22 06 5E 21 09 5E 34 4E 0D 06 00; -53F0: C5 11 09 00 ED 53 F4 5C CD 43 1E C1 CD 6B 16 CD; -5400: 43 1E C9 AF 32 21 5D CD 05 04 CD 11 3E 32 DA 5C CD B3 1C CA 50 1C CD FD; -5418: 03 3A 09 5E FE 80 CA 23 27 21 ED 5C 11 E6 5C 01 07 00 ED B0 CD FD 03 3A; -5430: 10 5D 32 EA 5C ED 5B EA 5C 16 00 B7 2A 0A 5E ED 52 DA 45 1C 22 0A 5E 2A; -5448: 06 5E 22 EB 5C 22 1F 5D C9 3A F1 5C B7 C8 3A 21 5D B7 20 13 CD 97 1D 21; -5460: AA 27 CD 07 27 CD 52 10 FE 59 20 F9 CD 9F 1D 3A F1 5C B7 C8 E5 21 23 5D; -5478: 96 E1 30 4F 3A F1 5C 47 AF 32 F1 5C C5 32 CE 5C 2A CF 5C E5 ED 5B F2 5C; -5490: CD D8 14 CD 3D 1E 2A F4 5C 22 F2 5C CD 97 1D 21 85 27 CD 07 27 CD 52 10; -54A8: FE 59 20 F9 CD 9F 1D 3A 21 5D B7 C4 03 14 E1 C1 ED 5B EB 5C CD E4 14 CD; -54C0: 4D 1E 2A F4 5C 22 EB 5C C3 51 14 32 F1 5C E5 21 23 5D 46 E1 AF C3 84 14; -54D8: E5 D5 CD 11 3E 3A D9 5C 77 D1 E1 C9 E5 D5 CD 11 3E 3A DA 5C 77 D1 E1 C9; -54F0: AF 32 21 5D CD 05 04 CD 11 3E 32 DA 5C 3A 08 5E 32 E7 5C 21 80 02 FE 19; -5508: 28 15 21 00 05 FE 18 28 0E FE 17 28 0A 21 00 0A FE 16 28 03 C3 1A 1D 22; -5520: DD 5C ED 4B DF 5C ED 42 DA 45 1C C9 CD 75 1D CD 6F 16 21 79 27 CD 07 27; -5538: 21 AA 27 CD 07 27 CD 52 10 FE 59 20 F9 CD 9F 1D 3E FF 32 21 5D CD 05 04; -5550: CD 11 3E 32 D9 5C 3A 08 5E FE 19 21 80 02 28 15 21 00 05 FE 18 28 0E FE; -5568: 17 28 0A 21 00 0A FE 16 28 03 C3 1A 1D ED 4B 0A 5E ED 42 22 E5 5C 22 DF; -5580: 5C 21 00 00 22 E1 5C 22 E3 5C CD B8 15 CD 05 04 3A E7 5C 32 08 5E 2A DD; -5598: 5C ED 4B DF 5C ED 42 22 0A 5E CD E4 14 11 09 00 ED 53 F4 5C CD 43 1E C3; -55B0: E1 03 2A E5 5C 7C B5 C9 CD B2 15 C8 3A 21 5D B7 20 19 CD 97 1D 21 79 27; -55C8: CD 07 27 21 AA 27 CD 07 27 CD 52 10 FE 59 20 F9 CD 9F 1D CD B2 15 C8 C5; -55E0: E5 21 23 5D 4E 06 00 E1 ED 42 C1 D2 44 16 ED 4B E5 5C 21 00 00 22 E5 5C; -55F8: C5 2A CF 5C E5 CD D8 14 ED 5B E1 5C 41 CD 3D 1E 2A F4 5C 22 E1 5C CD 97; -5610: 1D 21 79 27 CD 07 27 21 85 27 CD 07 27 CD 52 10 FE 59 20 F9 CD 9F 1D 3A; -5628: 21 5D B7 C4 F0 14 E1 C1 ED 5B E3 5C 41 CD E4 14 CD 4D 1E 2A F4 5C 22 E3; -5640: 5C C3 B8 15 22 E5 5C E5 21 23 5D 4E 06 00 E1 AF C3 F8 15 CD 5D 16 3A DD; -5658: 5C FE 01 C9 4F AF C5 CD E9 17 C1 C9 4F CD 6B 16 C3 43 1E 3E FF 18 EF 3E; -5670: FF 32 0E 5D CD 80 16 2A 61 5C 22 CF 5C C3 23 1E E7 1A 1F 21 FF FF ED 42; -5688: 7C FE 10 30 02 3E 11 3D 32 23 5D 47 0E 00 C9 22 D7 5C 22 DB 5C ED 5B EA; -56A0: 5C 2A D9 5C 16 00 19 22 D9 5C C9 CD 75 1D CD 6F 16 CD 05 04 3A 19 5E B7; -56B8: CA E1 03 21 00 00 22 D9 5C 0E FF 0C CD 53 16 20 FA 79 32 D4 5C 2A EB 5C; -56D0: 22 D5 5C CD 97 16 0C CD 53 16 28 FA FE 00 C2 10 17 3A D4 5C 4F 0C CD 53; -56E8: 16 FE 00 28 7F AF 32 DD 5C CD 40 1E CD 97 16 18 EC FF FF FF FF FF FF FF; -5700: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 3A EA 5C 32 D3 5C 32 D1; -5718: 5C 2A EB 5C 22 D5 5C C5 CD A5 17 C1 2A F4 5C 22 D5 5C 22 EB 5C AF 32 EA; -5730: 5C 3A DD 5C F5 3E 01 32 DD 5C CD 40 1E F1 32 DD 5C 3A D4 5C 4F 2A DB 5C; -5748: 22 EB 5C 3A D1 5C 32 EA 5C CD 40 1E 3A D4 5C 3C 4F CD 5D 16 2A D5 5C 22; -5760: EB 5C CD 40 1E 3A D4 5C 4F C3 C3 16 2A CF 5C 01 00 10 CD 2E 1E CD FD 03; -5778: 2A 0A 5E ED 5B D9 5C 19 22 0A 5E 3A 09 5E 21 19 5E 96 32 09 5E 36 00 2A; -5790: D5 5C 22 06 5E F5 CD 43 1E F1 4F CD 5D 16 AF 32 DD 5C C3 69 05 3A D3 5C; -57A8: B7 C8 E5 21 23 5D 96 E1 30 2B 3A D3 5C 47 AF 32 D3 5C C5 2A CF 5C E5 ED; -57C0: 5B D5 5C CD 3D 1E 2A F4 5C 22 D5 5C E1 C1 ED 5B D7 5C CD 4D 1E 2A F4 5C; -57D8: 22 D7 5C 18 C8 32 D3 5C E5 21 23 5D 46 E1 AF 18 D1 F5 21 CC 5C 36 00 79; -57F0: D6 10 38 03 34 18 F9 C6 10 4F C5 CD EC 03 C1 F1 CD A4 1C 11 DD 5C 01 10; -5808: 00 B7 28 01 EB ED B0 C9 3E FF 32 F9 5C CD 52 18 CD 36 18 CD 75 1D 3E FF; -5820: 32 10 5D 3A F9 5C FE FF CA E1 03 3A E5 5C FE 42 CA 2A 01 C3 E1 03 CD 7A; -5838: 18 CD 75 1D CD AB 18 C3 21 19 2A 5D 5C 23 7E FE 0D C8 3E 01 32 D6 5C CD; -5850: EB 1D AF 32 10 5D C9 CD 2E 10 3E 42 B8 20 07 2A 5D 5C 2B 22 5D 5C CD EB; -5868: 1D 2A D9 5C 22 D7 5C 2A DB 5C 22 D9 5C AF 32 D6 5C C9 CD 2B 04 CA 7B 02; -5880: CD DF 1D CD 72 05 C4 57 18 CD 8C 1D FE AF CC 42 18 FE E4 F5 CD 72 05 CC; -5898: 2E 10 F1 CC FC 1B CD 75 1D CD 2F 29 C2 D9 03 CD 5D 16 C9 3A D6 5C B7 2A; -58B0: E6 5C 28 03 2A D9 5C ED 5B EB 5C FE 03 3A EA 5C D5 ED 5B E8 5C 20 04 ED; -58C8: 5B DB 5C 47 ED 53 DB 5C 3A E5 5C FE 43 78 20 25 78 BA 28 1A 3D BA 78 28; -58E0: 15 3A D6 5C FE 03 78 28 0D AF 32 D6 5C 50 1E 00 ED 53 DB 5C 18 03 CD 1B; -58F8: 19 78 CD AC 1E 47 3A E5 5C FE 43 D1 C8 D5 FE 42 F5 CC 01 1A F1 FE 44 CC; -5910: 4C 1A CD 1B 19 3A DC 5C 47 D1 C9 3E 03 32 D6 5C C9 CD 72 05 28 07 F5 CD; -5928: 94 1A F1 FE FF F5 CC 5C 19 F1 28 03 C3 4D 1E 3A D6 5C FE 03 CC 46 19 2A; -5940: 59 5C 2B 36 80 C9 3A F9 5C FE FF C2 DE 2F 3A DB 5C B7 C8 4F 06 01 ED 5B; -5958: F4 5C 18 0E 3A F9 5C FE FF C2 3D 1E ED 53 F4 5C 0E 00 78 B7 C8 22 D7 5C; -5970: ED 53 D9 5C C5 06 01 ED 5B D9 5C 21 25 5D CD 3D 1E 2A F4 5C 22 D9 5C C1; -5988: 2A D7 5C 11 25 5D 1A BE 20 0B 23 13 0D 20 F7 22 D7 5C 10 D8 C9 21 6B 27; -59A0: 3E 0D C3 4A 1C 3E FF 18 02 3E EE 32 10 5D C3 18 18 3E FF 32 1F 5D CD 7A; -59B8: 18 CD 75 1D 3A E5 5C FE 42 C2 1A 1D ED 4B E6 5C ED 43 DB 5C C5 03 E7 30; -59D0: 00 36 80 EB D1 E5 ED 5B EB 5C CD 1B 19 3A DC 5C 47 CD 52 18 CD 21 19 E1; -59E8: ED 5B 53 5C E7 D2 08 C3 E1 03 EB 37 ED 52 D8 11 0A 00 19 44 4D E7 05 1F; -5A00: C9 ED 5B 53 5C 2A 59 5C 2B E5 D5 ED 52 ED 5B E6 5C D5 E5 21 00 00 3A F9; -5A18: 5C FE FF 28 03 21 05 00 19 22 DB 5C E1 3A F9 5C FE FF 20 05 D1 D1 E1 18; -5A30: 17 CD F2 19 C1 D1 E1 C5 E7 E5 19 C1 CD 32 1E 23 ED 4B E8 5C 09 22 4B 5C; -5A48: 2A 53 5C C9 ED 5B E8 5C ED 53 DB 5C 2A D7 5C 3A F9 5C FE FF C8 2A D9 5C; -5A60: E5 CD F2 19 E1 7C B5 28 10 2A D7 5C 2B 2B 2B ED 4B D9 5C 03 03 03 CD 2E; -5A78: 1E 2A 59 5C 2B ED 4B E8 5C C5 03 03 03 CD 32 1E 23 3A D2 5C 77 23 D1 73; -5A90: 23 72 23 C9 3A D9 5C 48 47 79 B8 38 19 78 B7 CA 1A 1D 05 28 0B 3E 10 1C; -5AA8: BB 20 03 1E 00 14 10 F7 06 01 2A D7 5C C9 21 ED 29 3E 05 C3 4A 1C CD 2F; -5AC0: 29 CA 50 1C CD FD 03 3A 09 5E FE 80 CA 23 27 C9 CD 52 18 21 00 00 22 D1; -5AD8: 5C CD DF 1D CD 8C 1D FE AF 28 56 FE CA 20 11 CD 0B 1E CD 75 1D 2A DB 5C; -5AF0: 22 D1 5C 21 E5 5C 18 27 FE AA 20 11 21 00 40 22; -5B00: D7 5C 21 00 1B 22 D9 5C 22 DB 5C 18 3B CD 75 1D CD 8C 1D 21 E5 5C FE E4; -5B18: 28 12 FE 0D C2 1A 1D 36 42 CD BE 1A CD 1C 1E CD DE 1B 18 27 36 44 CD BE; -5B30: 1A CD 0F 1C 30 1D DA 1A 1D CD E5 1D 2A D9 5C 22 D7 5C 2A DB 5C 22 D9 5C; -5B48: CD 75 1D 3E 43 32 E5 5C CD BE 1A CD 59 1B C3 69 05 2A D7 5C 22 E6 5C EB; -5B60: 2A D9 5C 7D B4 CA 1A 1D 7D B7 28 01 24 7C 32 EA 5C 5F 16 00 2A 0A 5E ED; -5B78: 52 DA 45 1C E5 2A 59 5C 36 AA 23 ED 5B D1 5C 73 23 72 2A DB 5C 22 E8 5C; -5B90: 2A 06 5E 22 EB 5C EB 2A E6 5C 3A EA 5C 47 CD 4D 1E 2A F4 5C E5 CD FD 03; -5BA8: E1 22 06 5E E1 22 0A 5E 21 09 5E 7E 32 1E 5D 34 E5 CD 43 1E E1 4E 0D 3A; -5BC0: E5 5C FE 42 CC C8 1B C9 2A 59 5C ED 5B 53 5C 37 ED 52 22 E6 5C 2A 4B 5C; -5BD8: ED 52 22 E8 5C C9 2A 4B 5C ED 5B 53 5C ED 52 22 DB 5C 2A 53 5C 22 D7 5C; -5BF0: 2A 59 5C 23 23 23 ED 52 22 D9 5C C9 CD 1B 1C D0 21 00 00 22 D9 5C 3A F9; -5C08: 5C FE FF C0 C3 13 1C CD 1B 1C D0 3E 0E 21 DD 27 C3 4A 1C CD 2A 1E CD 9B; -5C20: 1D CB F9 79 32 D2 5C 30 02 37 C9 20 FC 23 5E 23 56 23 22 D7 5C ED 53 DB; -5C38: 5C ED 53 D9 5C CD 2A 1E FE 29 20 E7 C9 21 BB 29 3E 03 CD C3 03 C3 D3 01; -5C50: 21 C5 29 3E 02 18 F3 21 DD 5C 06 08 36 20 23 10 FB CD 31 05 EB CD 81 1C; -5C68: 79 B7 CA 1A 1D FE 09 38 02 0E 08 7E FE 20 DA 1A 1D 11 DD 5C C5 ED B0 C1; -5C80: C9 23 7E FE 3A 20 11 2B 7E CD 24 05 C5 E5 CD CB 3D E1 C1 0B 0B 23 23 C9; -5C98: 2B 3A 19 5D C5 E5 CD CB 3D E1 C1 C9 69 26 00 29 29 29 29 01 25 5D 09 C9; -5CB0: CD 57 1C CD E8 03 06 80 0E 00 C5 CD A4 1C CD 0C 05 C1 C5 79 FE 10 20 05; -5CC8: C1 0E 00 18 ED 11 DD 5C 3A 06 5D 47 AF BE 20 03 C1 18 09 CD 13 27 C1 28; -5CE0: 06 0C 10 D6 F6 FF C9 3E 80 90 4F 32 1E 5D AF C8 CD B3 1C 21 0F 5D 71 C8; -5CF8: 36 FF C9 CD 75 1D CD E5 20 FD CB 01 9E CD 32 02 ED 7B 1C 5D 2A 3D 5C 2B; -5D10: 3E 12 BE 20 04 2B 22 3D 5C C9 FD CB 00 7E 28 05 3E 0B 32 3A 5C 3C 21 B2; -5D28: 29 CD C3 03 C3 D3 01 3A 3A 5C 21 CA 27 FE 14 28 F0 FE 0C 28 EC 21 D2 27; -5D40: FE 03 28 E5 21 DD 27 FE 01 28 DE 18 CD CD 52 18 CD 36 18 CD 75 1D 2A E6; -5D58: 5C 3A E5 5C FE 42 CA 2A 01 E5 C9 21 0E 5D 7E FE FF 36 00 C0 E7 BF 16 C9; -5D70: FD CB 01 7E C9 CD 70 1D C0 E1 C9 CD 2A 1E CD C1 1D 18 ED AF E7 01 16 C9; -5D88: 3E 02 18 F8 E7 18 00 C9 CD 83 1D E7 2C 0F C9 E7 6B 0D C9 E7 B2 28 C9 E7; -5DA0: 6E 0D C9 4F 06 00 C3 A9 1D C5 CD F1 20 C1 E7 1B 1A CD F1 20 C9 E7 F1 2B; -5DB8: C9 E7 99 1E C9 E7 8C 1C C9 E7 82 1C C9 2A 11 5D 23 22 5D 5C C9 CD DF 1D; -5DD0: CD 8C 1D FE 2C C2 1A 1D CD 2A 1E CD BD 1D C9 CD C5 1D C3 BD 1D CD 8C 1D; -5DE8: FE AF C0 CD 7B 1D 28 0B CD B9 1D ED 43 D9 5C ED 43 DB 5C CD 8C 1D FE 2C; -5E00: 28 09 FE 0D C2 1A 1D CD 75 1D C9 CD 7B 1D C8 CD B9 1D ED 43 DB 5C 3E 03; -5E18: 32 D6 5C C9 2A 11 5D E7 A7 11 C9 2A 61 5C E7 30 00 C9 E7 20 00 C9 E7 E8; -5E30: 19 C9 E7 55 16 C9 CD B2 3E 7C D3 3F C9 AF 18 24 CD 6B 16 ED 5B F4 5C 1B; -5E48: 06 01 21 25 5D E5 D5 CD 11 3E CB 7E 28 0A CB 46 20 06 21 D8 29 C3 29 1D; -5E60: D1 E1 3E FF 32 CE 5C ED 53 F4 5C C5 E5 CD 36 1E E1 C1 AF B0 C8 C5 E5 CD; -5E78: 06 3F 3A F4 5C CD 02 3F 3A F5 5C CD 63 3E 3A CE 5C B7 F5 CC 0E 3F F1 C4; -5E90: 0A 3F E1 11 00 01 19 E5 3E 10 21 F4 5C 34 BE 20 06 36 00 21 F5 5C 34 E1; -5EA8: C1 10 CA C9 E5 67 2E 00 E5 ED 52 DC BC 1E E1 7C E1 D8 7A C9 AF 32 D6 5C; -5EC0: 37 C9 21 FF FF 22 D7 5C 22 D9 5C 22 D1 5C CD 2B 04 CA 1A 1D CD DF 1D CD; -5ED8: 75 1D CD 57 1C CD 00 32 E6 80 3E 28 28 02 3E 50 32 D7 5C CD 98 3D CD F6; -5EF0: 1F CD A0 3E 1E 01 CD FD 1F CD EB 1F 1E 00 CD FD 1F 3A DD 5C FE 24 28 13; -5F08: CD F6 1F CD A0 3E CD B5 3E 7C FE 01 20 05 3E 80 32 DA 5C CD BD 20 21 25; -5F20: 5D 36 00 11 26 5D 01 FF 00 ED B0 01 D7 5C 11 DA 5C 0A FE 50 28 13 1A FE; -5F38: 80 28 07 3E 19 21 70 02 18 13 3E 17 21 F0 04 18 0C 1A FE 80 3E 18 20 F4; -5F50: 3E 16 21 F0 09 32 08 5E 22 0A 5E 3E 01 32 07 5E 3E 10 32 0C 5E 21 0F 5E; -5F68: 11 10 5E 01 08 00 36 20 ED B0 21 DD 5C 11 1A 5E 01 08 00 ED B0 CD EB 1F; -5F80: 06 01 11 08 00 21 25 5D CD 62 1E 3A D6 5C F5 AF CD C4 32 2A 0A 5E 22 D7; -5F98: 5C 21 DD 5C DF 3E 0D D7 2A D7 5C F1 E5 16 00 5F ED 52 44 4D CD A9 1D 3E; -5FB0: 2F D7 C1 CD A9 1D C3 6B 32 01 09 02 0A 03 0B 04 0C 05 0D 06 0E 07 0F 08; -5FC8: 10 01 CD 08 3E F6 11 47 3E 32 CD 44 3E 3E 02 CD 44 3E CD FD 3D DB 1F E6; -5FE0: 04 3E 50 28 02 3E 28 32 D7 5C C9 3A 16 5D F6 3C 32 16 5D D3 FF C9 3A 16; -5FF8: 5D E6 6F 18 F3 F3 3E F4 D3 1F 2A E6 5C 0E 7F 06 0A 16 4E CD B1 20 06 0C; -6010: 16 00 CD B1 20 06 03 16 F5 CD B1 20 16 FE CD AF 20 53 CD AF 20 16 00 CD; -6028: AF 20 56 CD AF 20 16 01 CD AF 20 16 F7 CD AF 20 06 16 16 4E CD B1 20 06; -6040: 0C 16 00 CD B1 20 06 03 16 F5 CD B1 20 16 FB CD AF 20 06 00 16 00 CD B1; -6058: 20 16 F7 CD AF 20 06 3C 16 4E CD B1 20 7E 23 FE 10 20 9C 06 00 CD B1 20; -6070: FA 76 20 CD B1 20 DB 1F E6 40 C2 39 3F 3A D8 5C B7 C0 0E 7F 7B D3 3F 2A; -6088: E8 5C 06 03 7E D3 5F E5 F3 3E 80 D3 1F C5 CD E5 3F DB 1F E6 7F C1 28 06; -60A0: 10 EE 21 D6 5C 34 E1 7E 23 FE 01 20 DD FB C9 06 01 DB FF E6 C0 28 FA F8; -60B8: ED 51 10 F5 C9 21 D7 5C 46 AF 23 77 1E FF C5 1C 7B 06 1B CD 44 3E CD EB; -60D0: 1F CD DD 32 3A DA 5C FE 80 20 06 CD F6 1F CD 0F 33 C1 10 E2 C9 F5 3A F8; -60E8: 5C FE FF 28 2F F1 CD 70 29 F5 3A B6 5C FE F4 28 23 AF 21 18 5D B6 36 FF; -6100: 28 1A 3A 0C 5D B7 21 C3 5C 11 33 5D 20 03 11 34 5E 06 2D 4E 1A 77 79 12; -6118: 23 13 10 F7 F1 C9 2A 59 5C 36 0D 22 5B 5C 23 36 80 C9 ED 5B 59 5C 21 20; -6130: 5D CD B0 02 C9 3A 0F 5D B7 F5 C4 2A 21 F1 CC 1E 21 2A 59 5C CD 80 3D 3A; -6148: 19 5D C6 41 D7 3E 3E D7 21 3A 5C 36 FF C3 90 1D CD 2A 1E CD 8C 1D FE 2C; -6160: C2 1A 1D 2A DB 5C 22 D9 5C CD 0B 1E CD 75 1D 2A DB 5C 7C B7 C2 1A 1D 23; -6178: 22 D7 5C 2A D9 5C 22 DB 5C C9 2A 11 5D 22 5D 5C CD 0B 1E CD D0 1D CD 8C; -6190: 1D FE 41 30 05 CD 2A 1E 18 F4 FE A5 F5 CC 58 21 F1 28 0B E6 DF FE 52 28; -61A8: 05 FE 57 C2 1A 1D 32 09 5D CD 75 1D 3E 23 32 E5 5C 3E 00 32 E6 5C CD DB; -61C0: 21 F5 CD 0F 22 F1 F5 C4 88 22 F1 CD 42 22 2A 11 5D 01 24 01 09 22 11 5D; -61D8: C3 D3 01 3E 0A 32 06 5D CD B0 1C F5 CD 05 04 F1 20 1C 3A 09 5D FE 52 28; -61F0: 10 21 E6 5C 34 CD B3 1C 28 F7 21 E6 5C 35 CD B3; -6200: 1C CD 5D 16 AF C9 3A 09 5D FE 52 C0 C3 D9 03 3A DB 5C E7 27 17 78 B1 C2; -6218: 1B 22 C9 3E 19 32 3A 5C 21 04 28 3E 0A C3 4A 1C 3E 0B 21 12 28 18 F6 E5; -6230: 0E 20 EF 3A D7 5C 77 23 AF 77 23 77 23 77 3E 7F E1 C9 F5 CD 0F 22 EB 2A; -6248: 53 5C ED 4B 4F 5C ED 42 EB 73 23 72 CD B2 22 3A 09 5D FE A5 CC 2F 22 28; -6260: 0A 3A 09 5D FE 52 3E FF 20 01 AF 77 F1 C3 70 22 F5 01 14 00 09 E5 CD 23; -6278: 24 E1 23 06 01 F1 B7 F5 C4 4D 1E F1 CC 3D 1E C9 2A D7 5C E5 21 00 20 22; -6290: D7 5C CD 9A 22 E1 22 D7 5C C9 21 00 10 22 D9 5C CD C4 1A CD 59 1B 21 00; -62A8: 00 22 E8 5C CD 6B 16 C3 43 1E 2A 53 5C 2B 22 51 5C E5 01 24 01 CD 32 1E; -62C0: 3E 00 06 00 12 1B 10 FC E1 E5 11 0E 3D 73 23 72 23 11 06 3D 73 23 72 23; -62D8: 36 44 23 23 23 23 23 36 24 23 36 01 23 3A F6 5C 77 23 3A 1E 5D 77 23 3A; -62F0: 09 5D FE 52 36 00 28 04 3A E8 5C 77 23 70 28 04 3A E9 5C 77 23 EB E1 D5; -6308: 11 10 00 19 EB 21 DD 5C 01 10 00 ED B0 E1 C9 0E 0D EF 4E EF 01 24 00 09; -6320: C9 0E 24 06 00 2A 51 5C 09 C9 0E 0D EF 34 C0 E5 CD 43 24 CD FC 23 E1 23; -6338: 34 E5 CD 18 24 E1 3E 10 BE C0 E5 0E 0F EF 7E FE 7F E1 28 0C 2A 51 5C CD; -6350: E1 26 0E 0E EF C3 79 23 CD CF 23 F5 CC 18 24 0E 0E EF F1 C4 70 23 C9 36; -6368: 00 0E 19 EF 16 20 5E C9 CD 67 23 ED 53 D7 5C 18 08 CD 67 23 1C ED 53 D7; -6380: 5C CD 9A 22 CD 70 29 0E 10 EF EB 21 DD 5C 01 10 00 ED B0 0E 0C EF 3A 1E; -6398: 5D 77 C9 0E 0D EF 34 C0 23 34 E5 CD 43 24 0E 23 EF 7E B7 28 09 E1 E5 35; -63B0: CD FC 23 E1 E5 34 CD 18 24 E1 3E 10 BE CC C1 23 C9 CD CF 23 F5 CD 70 29; -63C8: F1 C2 92 24 C3 18 24 36 00 0E 19 EF 34 0E 10 EF 11 DD 5C 01 10 00 ED B0; -63E0: CD B3 1C C0 CD 5D 16 0E 10 EF EB 21 DD 5C 01 10 00 ED B0 0E 0C EF 3A 1E; -63F8: 5D 77 AF C9 CD 23 24 CD 21 23 06 01 CD 4D 1E 0E 0F EF 7E FE 7F C8 CD 21; -6410: 23 AF 47 77 23 10 FC C9 CD 23 24 CD 21 23 06 01 C3 3D 1E 2A 51 5C 01 1E; -6428: 00 09 5E 23 56 0E 0E EF 46 05 04 F5 3E 10 28 09 1C BB 20 03 1E 00 14 10; -6440: F7 F1 C9 0E 0B EF 7E C3 CB 3D 21 C2 5C E5 21 F1 20 E5 F5 CD F1 20 3E 0A; -6458: 32 06 5D F1 CD A2 24 F5 CD 50 26 CA 9E 24 F1 CD 17 23 77 C3 2A 23 0E 0D; -6470: EF 7E 01 0E 00 09 BE C0 0E 0E EF 7E 01 0E 00 09 BE C0 21 B6 5C 7E FE F4; -6488: 28 08 CB 66 28 04 F6 01 E1 C9 3E 07 32 3A 5C CD E5 20 E7 58 00 C9 3E 17; -64A0: 18 F2 57 0E 0F EF 7E FE 7F 7A C0 01 13 00 09 7E B7 7A 20 21 2B 7E B7 20; -64B8: 09 C5 E5 D5 CD F8 24 D1 E1 C1 4E 7A EB 2A CF 5C 09 FE 06 77 CC 04 25 0E; -64D0: 21 EF 34 E1 C9 2B 7E 2B 3C BE 23 34 E5 F5 0E 23 EF 36 FF F1 E1 38 07 7A; -64E8: FE 0D 28 06 C1 C9 7A FE 0D C0 AF 77 23 77 7A C9 2A 61 5C 22 CF 5C 01 10; -6500: 00 C3 23 1E 36 0D 2A 5D 5C 22 D7 5C 2A CF 5C 22 5D 5C 21 3B 5C CB BE CD; -6518: C1 1D 21 3B 5C CB FE 2A CF 5C 22 5D 5C CD C1 1D CD B9 1D C5 D1 0E 20 EF; -6530: 46 AF 21 00 00 22 DB 5C 19 30 09 E5 2A DB 5C 23 22 DB 5C E1 10 F2 22 D9; -6548: 5C 3A DB 5C 21 DA 5C ED 67 E6 0F 32 DB 5C 2A D7 5C 22 5D 5C CD 68 25 0E; -6560: 21 EF 3E FF 77 23 77 C9 0E 19 EF 3A DA 5C BE C2 84 25 0E 0E EF 3A DB 5C; -6578: BE C2 A7 25 0E 0D EF 3A D9 5C 77 C9 CD CA 25 C4 C3 25 3A DA 5C 0E 19 EF; -6590: 77 0E 10 EF 11 DD 5C 01 10 00 ED B0 CD B3 1C C2 D2 25 CD E4 23 18 06 CD; -65A8: CA 25 C4 C3 25 3A DB 5C 0E 0E EF 77 E5 CD 43 24 CD 18 24 E1 2B 3A D9 5C; -65C0: 77 18 B9 CD 43 24 CD FC 23 C9 0E 23 EF 7E B7 36 00 C9 2A DA 5C 26 20 22; -65D8: D7 5C 2A D9 5C E5 2A DB 5C E5 CD 81 23 E1 22 DB 5C E1 22 D9 5C 18 BE CD; -65F0: F1 20 21 3C 5C CB 9E 2A 3D 5C 5E 23 56 B7 21 7F 10 ED 52 20 21 ED 7B 3D; -6608: 5C D1 D1 ED 53 3D 5C CD 2B 26 38 09 21 C2 5C E5 21 E5 20 E5 C9 FE 0D 28; -6620: F3 E7 85 0F 18 E9 CD 2B 26 18 E9 3E 0A 32 06 5D CD 50 26 28 0D FE 7F C2; -6638: 9E 24 01 13 00 09 36 00 18 03 CD 6E 24 CD 17 23 7E F5 CD 9B 23 F1 37 C9; -6650: 0E 0F EF 7E B7 C9 2A 11 5D 22 5D 5C CD 0B 1E CD 75 1D 3A DB 5C E7 27 17; -6668: 78 B1 CA D3 01 E5 2A 4F 5C 09 7E 21 0E 3D BC E1 C2 28 22 36 00 23 36 00; -6680: ED 43 D9 5C 2A 4F 5C 09 2B 22 D7 5C CD CE 26 2A D7 5C 01 24 01 CD 2E 1E; -6698: 21 10 5C 06 10 C5 ED 4B D9 5C 5E 23 56 EB ED 42 EB 38 11 56 2B 5E 23 E5; -66B0: EB 01 24 01 ED 42 EB E1 72 2B 73 23 23 C1 10 DD 2A 11 5D 01 24 01 ED 42; -66C8: 22 11 5D C3 D3 01 01 0F 00 09 7E B7 C8 2A D7 5C 22 51 5C CD E1 26 C3 FC; -66E0: 23 01 0D 00 09 5E 23 56 01 0D 00 09 73 23 72 0E 10 EF 11 DD 5C 01 10 00; -66F8: ED B0 CD 43 24 0E 0C EF 4E CD 6B 16 C3 43 1E 7E B7 C8 E6 7F D7 CB 7E C0; -6710: 23 18 F4 1A BE C0 13 23 10 F9 C9 21 FC 27 3E 06 C3 4A 1C 21 ED 27 3E 04; -6728: C3 4A 1C 3E 1A 18 02 3E 12 32 3A 5C C9 3E 03 18 F8 AF 32 D8 5C 32 D6 5C; -6740: DB 1F 32 CD 5C 5A D5 7B D3 7F 3E 18 CD 9A 3D 3A CD 5C E6 80 C4 A0 3E D1; -6758: CD BB 32 3A D6 5C B7 C8 3E 07 32 0F 5D C9 4F 2E 4B 2E 00 56 65 72 69 66; -6770: 79 20 45 72 72 6F 72 2E 8D 42 41 43 4B 55 50 20 44 49 53 4B 8D 49 6E 73; -6788: 65 72 74 20 44 65 73 74 69 6E 61 74 69 6F 6E 20 64 69 73 6B 0D 74 68 65; -67A0: 6E 20 70 72 65 73 73 20 59 00 49 6E 73 65 72 74 20 53 6F 75 72 63 65 20; -67B8: 64 69 73 6B 20 74 68 65 6E 20 70 72 65 73 73 20 59 00 2A 42 52 45 41 4B; -67D0: 2A 8D 4F 75 74 20 6F 66 20 52 41 4D 8D 41 72 72 61 79 20 6E 6F 74 20 66; -67E8: 6F 75 6E 64 8D 44 69 72 65 63 74 6F 72 79 20 66 75 6C 6C 8D 4E 6F 20 64; -6800: 69 73 6B 8D 53 74 72 65 61 6D 20 6F 70 65 6E 65 64 8D 4E 6F 74 20 64 69; -6818: 73 6B 20 66 69 6C 65 8D 46 69 6C 65 20 65 78 69 73 74 73 0D 4F 76 65 72; -6830: 20 77 72 69 74 65 3F 28 59 2F 4E A9 F5 C5 ED 53 04 5D 22 02 5D CD F1 20; -6848: 3E FF 32 15 5D 32 1F 5D C1 F1 21 01 02 22 1A 5D 21 00 00 39 22 1C 5D 2B; -6860: 2B F9 F5 CD 1D 02 21 8C 28 7E B9 20 12 F1 23 5E 23 56 21 D3 01 E5 D5 2A; -6878: 02 5D ED 5B 04 5D C9 FE FF 20 04 F1 C3 D3 01 23 23 23 18 DD 00 98 3D 01; -6890: CB 3D 02 63 3E 03 02 3F 04 06 3F 05 3D 1E 06 4D 1E 07 D8 28 08 5C 16 09; -68A8: 64 16 0A F0 1C 0B FB 28 0C F2 28 0D D3 01 0E 0F 29 0F D3 01 10 D3 01 11; -68C0: D3 01 12 26 29 13 E0 28 14 E3 28 15 39 27 16 EB 1F 17 F6 1F 18 05 04 FF; -68D8: F5 CD 05 04 F1 C3 79 04 AF 18 02 3E FF 11 DD 5C 01 10 00 B7 28 01 EB ED; -68F0: B0 C9 CD 05 04 CD C4 1A C3 27 1B 22 D7 5C ED 53; -6900: D9 5C ED 53 DB 5C CD 05 04 CD C4 1A C3 53 1B B7 32 D6 5C 22 D9 5C ED 53; -6918: DB 5C CD B3 1C CD A4 18 CD AB 18 C3 21 19 CD 05 04 CD B3 1C C3 A0 07 CD; -6930: 57 1C CD 05 04 C3 B3 1C C5 06 08 7E D7 23 10 FB 3E 3C D7 7E D7 3E 3E D7; -6948: C1 C9 E5 D5 C5 F5 21 0C 5D 7E B7 28 3D E5 01 01 01 C5 CD FD 19 C1 E1 36; -6960: 00 21 25 5D CD 32 1E 2A 11 5D 01 01 01 09 18 1F E5 D5 C5 F5 21 0C 5D 7E; -6978: B7 20 17 36 FF 21 25 5D 01 01 01 CD 2E 1E B7 01 01 01 2A 11 5D ED 42 22; -6990: 11 5D F1 C1 D1 E1 C9 AF 32 D7 5C CD 75 1D CD 2B 04 CA 1A 1D CD 11 3E 3A; -69A8: D7 5C 77 C3 E1 03 3E 80 18 E6 0D 2A 45 52 52 4F 52 2A 8D 0D 4E 6F 20 73; -69C0: 70 61 63 65 8D 0D 46 69 6C 65 20 65 78 69 73 74 73 8D 20 46 72 65 65 8D; -69D8: 0D 52 65 61 64 20 4F 6E 6C F9 0D 44 69 73 63 20 45 72 72 6F F2 0D 52 65; -69F0: 63 2E 20 20 4F 2F C6 54 69 74 6C 65 3A A0 0D 52 65 74 72 79 2C 41 62 6F; -6A08: 72 74 2C 49 67 6E 6F 72 65 3F 00 0D 54 72 6B A0 20 73 65 63 A0 20 44 65; -6A20: 6C 2E 20 46 69 6C 65 8D 0D 4E 6F 20 46 69 6C 65 28 73 29 8D 00 21 41 2A; -6A38: 11 80 40 01 20 00 ED B0 C9 3A B5 03 FE F3 3E 10 28 01 AF 32 01 5C 01 FD; -6A50: 7F 3E 10 ED 79 C9 F5 C5 D5 E5 DD E5 FD E5 D9 C5 D5 E5 08 F5 ED 57 F5 ED; -6A68: 5F F5 21 00 00 39 E5 3E 3C D3 FF 3E 3F ED 47 DB 1F E6 80 0F 0F 0F 32 01; -6A80: 5C CD 65 2F CD A0 3E CD A0 3E 11 0A 00 21 00 40 E5 CD 73 2D 21 00 41 11; -6A98: 0B 00 CD 73 2D E1 E5 11 08 00 CD 1B 2F 21 E3 40 7E 32 00 5C 23 7E 34 23; -6AB0: 5E 23 56 B7 EB 11 C0 00 ED 52 22 E5 40 21 00 40 11 08 00 CD 73 2D E1 ED; -6AC8: 5B E1 40 D5 11 0A 00 CD 1B 2F D1 CD 4C 2D D5 3E 3C D3 FF CD 65 2F 21 00; -6AE0: 40 11 08 00 06 01 CD 1B 2F D1 2A E1 40 ED 53 E1 40 E5 21 00 40 11 08 00; -6AF8: 06 01 CD 73 2D 3A E4 40 3D CD E5 2C 36 40 23 06 07 36 20 23 10 FB 36 43; -6B10: D1 C1 23 71 23 70 23 23 23 36 C0 23 73 23 72 21 00 40 11 00 00 DB 5F 3D; -6B28: 5F 06 01 CD 73 2D 21 00 00 39 22 40 41 31 FF 41 CD 35 2A 21 00 C0 AF 86; -6B40: 23 47 7C B7 78 20 F8 21 00 41 77 E5 21 58 2B E5 21 2F 3D E5 F3 C3 80 40; -6B58: E1 01 FD 7F 3E AA 32 30 41 16 05 3A 01 5C B2 57 ED 51 3A 30 C1 FE AA C2; -6B70: 1B 2C 7A E6 F8 57 23 06 08 72 ED 51 AF 21 00 C0 86 23 5F 7C B7 7B 20 F8; -6B88: 21 00 41 BE 23 28 04 14 10 E7 15 06 08 C5 CD 37 2C C1 10 F9 0E 00 CD 3A; -6BA0: 2F CD 2A 2D 3A E4 40 32 02 41 3C 32 E4 40 2A E5 40 11 01 00 ED 52 22 E5; -6BB8: 40 D8 2A E1 40 22 1E 41 CD 1E 2D 3E 38 32 11 41 3E 01 32 1D 41 21 00 41; -6BD0: 22 19 41 21 00 01 22 1B 41 ED 5B E1 40 CD 65 2F 4A CD 3A 2F 21 00 41 06; -6BE8: 01 CD 58 2D ED 53 E1 40 0E 00 CD 3A 2F CD 34 2D 3A 02 41 CD E5 2C 11 10; -6C00: 41 01 10 00 EB ED B0 DB 5F 3D 5F 16 00 21 00 40 CD 73 2D 01 FD 7F 3A 01; -6C18: 41 ED 79 2A 40 41 F9 21 00 40 11 0A 00 CD 1B 2F 21 00 41 11 0B 00 CD 1B; -6C30: 2F 3E 3C F5 C3 BC 2E 78 3D 32 03 41 47 3A 01 41 E6 07 B8 C8 3E 02 B8 C8; -6C48: 3A 01 41 E6 08 28 06 78 FE 07 C8 18 04 78 FE 05 C8 CD 5D 2C C9 21 01 41; -6C60: 7E E6 F8 4F 78 B1 C5 01 FD 7F ED 79 C1 21 00 C0 7E B7 20 06 23 7C B7 20; -6C78: F7 C9 CD 7E 2C C9 0E 00 CD 3A 2F CD 2A 2D 3A E4 40 32 02 41 3C 32 E4 40; -6C90: 2A E5 40 11 40 00 ED 52 22 E5 40 D8 2A E1 40 22 1E 41 CD 1E 2D 3E 40 32; -6CA8: 1D 41 21 00 C0 22 19 41 21 00 40 22 1B 41 ED 5B E1 40 CD 3E 2D ED 53 E1; -6CC0: 40 0E 00 CD 3A 2F CD 34 2D 3A 02 41 CD E5 2C 11 10 41 01 10 00 EB ED B0; -6CD8: DB 5F 3D 5F 16 00 21 00 40 CD 73 2D C9 4F E6 F0 0F 0F 0F 0F 47 C5 58 16; -6CF0: 00 21 00 40 D5 CD 1B 2F D1 C1 06 00 79 E6 0F 07 07 07 07 21 00 40 85 6F; -6D08: C9 21 10 41 06 09 36 20 23 10 FB 3E 40 32 10 41 3E 43 32 18 41 C9 CD 09; -6D20: 2D 3A 03 41 C6 30 32 11 41 C9 21 00 40 11 08 00 CD 1B 2F C9 21 00 40 11; -6D38: 08 00 CD 73 2D C9 CD 65 2F 4A CD 3A 2F 21 00 C0 06 40 18 0C CD 65 2F 4A; -6D50: CD 3A 2F 21 00 40 06 C0 C5 D5 CD 73 2D 11 00 01 19 D1 1C 7B FE 10 20 07; -6D68: 1E 00 14 4A CD 3A 2F C1 10 E6 C9 7B 3C D3 5F E5 16 14 D5 F3 0E 7F 3E A0; -6D80: D3 1F CD CA 3F D1 E1 DB 1F E6 7F C8 15 E5 D5 20 EA 76 2A E6 5C ED 5B EB; -6D98: 5C 3A EA 5C 47 CD 3D 1E C9 CD DF 1D CD 75 1D CD 2E 10 CD 57 1C ED 43 20; -6DB0: 40 79 FE 08 30 1C CD 05 04 CD B3 1C C2 D9 03 21 DD 5C ED 4B 20 40 09 36; -6DC8: 38 E5 CD B3 1C E1 28 08 36 20 CD B3 1C C3 33 2E CD 5D 16 CD 92 2D 31 FF; -6DE0: 40 06 08 C5 78 01 FD 7F 3D F5 F6 10 ED 79 F1 C6 30 21 DD 5C ED 4B 20 40; -6DF8: 09 77 CD B3 1C 20 06 CD 5D 16 CD 92 2D C1 10 DB 3E 20 21 DD 5C ED 4B 20; -6E10: 40 09 77 CD B3 1C CD 5D 16 C5 F5 01 FD 7F 3A 01 41 ED 79 F1 C1 18 12 CD; -6E28: DF 1D CD 75 1D CD 2E 10 CD 2F 29 C2 D9 03 CD 5D 16 3A DD 5C FE 24 F3 20; -6E40: 02 ED 5E 31 F0 40 CD 11 3E 32 10 40 3A 16 5D 32 11 40 2A E6 5C E5 ED 5B; -6E58: EB 5C D5 1C 7B FE 10 20 03 1E 00 14 4A CD 07 2F 3A 10 40 E6 02 C4 0F 2F; -6E70: 79 CD 50 2F 21 00 41 06 BF C5 D5 CD 1B 2F 11 00 01 19 D1 1C 7B FE 10 20; -6E88: 13 1E 00 14 4A CD 07 2F 3A 10 40 E6 02 C4 0F 2F 79 CD 50 2F C1 10 DA D1; -6EA0: E1 F9 3A 11 40 F5 4A CD 07 2F 3A 10 40 E6 02 C4 0F 2F 79 CD 50 2F 21 00; -6EB8: 40 CD 1B 2F F1 08 F1 ED 4F F1 ED 47 F3 3E FF E2 CC 2E 3E 00 32 00 5C F1; -6ED0: E1 D1 C1 D9 08 FD E1 DD E1 E1 D1 C1 3A 48 5C E6 38 0F 0F 0F D3 FE 3A 08; -6EE8: 5B FE EE 20 0A C5 01 FD 7F 3A 5C 5B ED 79 C1 3A 00 5C B7 3E C9 32 00 5C; -6F00: 20 01 FB F1 C3 00 5C 3A 11 40 F6 3C D3 FF C9 79 B7 1F 4F D0 3A 11 40 E6; -6F18: 6F 18 F1 7B 3C D3 5F E5 16 14 D5 F3 0E 7F 3E 80 D3 1F CD E5 3F D1 E1 DB; -6F30: 1F E6 7F C8 15 E5 D5 20 EA 76 3E 3C D3 FF 3A 00 5C E6 08 20 0A 79 B7 1F; -6F48: 4F 30 04 3E 2C D3 FF 79 D3 7F CD FD 3D 3E 18 D3 1F DB FF E6 80 28 FA C5; -6F60: CD FD 3D C1 C9 3E 08 18 EE 2A 1C 5D 2B 2B F9 C3 2F 1D 22 02 5D ED 53 04; -6F78: 5D E1 5E 23 56 23 E5 21 2F 3D E5 D5 21 C2 5C E5 2A 02 5D ED 5B 04 5D C9; -6F90: 21 FF FF 22 FA 5C 22 FC 5C 22 C8 5C 22 CA 5C AF 32 17 5D 32 19 5D 32 18; -6FA8: 5D 32 0F 5D 32 1F 5D 3E FF D3 FF 32 3A 5C 32 16 5D 32 0C 5D 3E C9 32 C2; -6FC0: 5C 3E D0 D3 1F C9 CD 0C 05 7E B7 CA AC 03 FE 01 CC 07 05 C0 18 F0 06 01; -6FD8: 21 25 5D C3 67 1E E5 ED 5B F4 5C CD D6 2F 3A DB 5C D1 B7 C8 4F 21 25 5D; -6FF0: ED B0 C9 CF 2A D0 D1 E6 D2 EF F8 FE BE F4 D5 F7; -7000: D3 D4 FF 34 EC 38 F0 D6 33 04 18 10 C2 1E AB 16 3A 05 87 07 15 18 D0 1A; -7018: FB 1C A5 19 A9 19 B1 19 4D 1D 82 21 56 26 90 06 97 29 A1 2D AE 29 CE 11; -7030: 10 18 2A 59 5C 22 11 5D 22 D9 5C 3E FF 32 D6 5C 21 DB 5C 22 D7 5C 18 0F; -7048: 22 11 5D 22 D9 5C CD E1 30 C0 23 23 22 D7 5C CD A9 30 20 2B EB 13 06 00; -7060: 21 C8 31 09 7E 2A D9 5C 77 23 EB E7 DD 19 C5 E7 E8 19 C1 3A D6 5C B7 20; -7078: 0E 2A D7 5C 5E 23 56 EB B7 ED 42 EB 72 2B 73 2A D9 5C 7E FE 0D C8 23 22; -7090: D9 5C 7E FE 0D C8 FE 22 20 BD 23 7E FE 0D C8 FE 22 20 F7 23 22 D9 5C 18; -70A8: AE 2A D9 5C 11 FD 30 0E 00 7E E6 DF 47 B7 20 03 23 18 F6 1A E6 80 20 08; -70C0: 1A B8 20 15 23 13 18 E9 1A E6 7F B8 C8 0C 2A D9 5C 13 1A FE FF 20 DA B7; -70D8: C9 13 1A E6 80 28 FA 18 EC 2A 45 5C 23 23 7C B5 28 0A AF 32 D6 5C 2B 2B; -70F0: E7 6E 19 C9 3E FF 32 D6 5C 2A 59 5C C9 53 41 56 45 80 53 41 56 C5 4C 4F; -7108: 41 44 80 4C 4F 41 C4 52 55 4E 80 52 55 CE 43 41 54 80 43 41 D4 45 52 41; -7120: 53 45 80 45 52 41 53 C5 4E 45 57 80 4E 45 D7 4D 4F 56 45 80 4D 4F 56 C5; -7138: 4D 45 52 47 45 80 4D 45 52 47 C5 50 45 45 4B 80 50 45 45 CB 50 4F 4B 45; -7150: 80 50 4F 4B C5 4F 50 45 4E 83 43 4C 4F 53 45 83 43 4F 44 45 80 43 4F 44; -7168: C5 52 4E 44 80 52 4E C4 44 41 54 41 80 44 41 54 C1 53 43 52 45 45 4E 04; -7180: 84 53 43 52 45 45 4E 84 43 4F 50 59 80 43 4F 50 D9 46 4F 52 4D 41 54 80; -7198: 46 4F 52 4D 41 D4 47 4F 54 4F 80 47 4F 54 CF 4C 49 53 54 80 4C 49 53 D4; -71B0: 4C 49 4E 45 80 4C 49 4E C5 56 45 52 49 46 59 80 56 45 52 49 46 D9 FF FF; -71C8: F8 F8 EF EF F7 F7 CF CF D2 D2 E6 E6 D1 D1 D5 D5 BE BE F4 F4 D3 D4 AF AF; -71E0: A5 A5 E4 E4 AA AA FF FF D0 D0 EC EC F0 F0 CA CA D6 D6 00 2A 4F 5C B7 01; -71F8: 25 5D ED 42 C9 53 53 50 21 2C 32 DF CD 52 10 FE 54 28 0C 21 B9 1F 22 E6; -7210: 5C 23 22 E8 5C 18 0A 21 5A 32 22 E6 5C 23 22 E8 5C E7 6E 0D 21 12 33 DF; -7228: CD 11 3E C9 50 72 65 73 73 20 54 20 66 6F 72 20 54 55 52 42 4F 2D 46 4F; -7240: 52 4D 41 54 0D 4F 74 68 65 72 20 6B 65 79 20 66 6F 72 20 46 4F 52 4D 41; -7258: 54 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 01 3E 0D D7 21 8C; -7270: 32 DF CD 52 10 FE 52 28 03 C3 D3 01 E7 6E 0D E7 8E 02 20 FB E7 1E 03 38; -7288: F6 C3 DD 1E 50 72 65 73 73 20 52 20 66 6F 72 20 72 65 70 65 61 74 20 46; -72A0: 4F 52 4D 41 54 0D 4F 74 68 65 72 20 6B 65 79 20 66 6F 72 20 54 52 2D 44; -72B8: 4F 53 00 21 BA 1F 22 E8 5C C3 7D 20 32 E5 5C E7 6E 0D C9 48 45 41 44 20; -72D0: 00 20 20 43 59 4C 49 4E 44 45 52 20 00 B7 D5 F5 3E 16 D7 3A 6B 5C 3D D7; -72E8: 3E 00 D7 21 CB 32 DF F1 3E 30 CE 00 D7 21 D1 32 DF D1 D5 4B 06 00 CD A9; -7300: 1D D1 D5 7B FE 0A 30 03 3E 20 D7 D1 C3 FD 1F 37 18 CC 48 45 41 44 20 30; -7318: 20 20 43 59 4C 49 4E 44 45 52 20 30 00 00 00 00 00 00 00 00 FF FF FF FF; -7330: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7348: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7360: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7378: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7390: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -73A8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -73C0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -73D8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -73F0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7408: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7420: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7438: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7450: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7468: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7480: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7498: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -74B0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -74C8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -74E0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -74F8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7510: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7528: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7540: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7558: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7570: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7588: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -75A0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -75B8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -75D0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -75E8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7600: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7618: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7630: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7648: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7660: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7678: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7690: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -76A8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -76C0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -76D8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -76F0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7700: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7718: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7730: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7748: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7760: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7778: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7790: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -77A8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -77C0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -77D8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -77F0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7808: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7820: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7838: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7850: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7868: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7880: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7898: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -78B0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -78C8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -78E0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -78F8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7910: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7928: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7940: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7958: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7970: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7988: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -79A0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -79B8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -79D0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -79E8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7A00: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7A18: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7A30: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7A48: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7A60: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7A78: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7A90: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7AA8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7AC0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7AD8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7AF0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7B08: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7B20: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7B38: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7B50: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7B68: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7B80: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7B98: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7BB0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7BC8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7BE0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7BF8: FF FF FF FF FF FF FF FF FF 18 03 FF 18 03 C3 00 3D C3 03 3D FF FF FF FF; -7C10: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7C28: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7C40: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7C58: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7C70: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7C88: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7CA0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7CB8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7CD0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; -7CE8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF C3 F1 20 C3 3C 28; -7D00: 00 18 2E 00 18 14 00 C3 EF 25 C3 4A 24 00 18 FA 00 18 E7 00 18 E7 00 C3; -7D18: 69 2F CD 21 3D E5 C3 6C 01 CD F3 31 00 00 DC 4C 3D 21 C2 5C C9 00 00 00; -7D30: C9 CD 21 3D E5 C3 39 02 AF D3 F7 DB F7 FE 1E 28 03 FE 1F C0 CF 31 3E 01; -7D48: 32 EF 5C C9 AF D3 FF DB F6 21 38 3D 11 92 5C 01 14 00 ED B0 21 67 3D E5; -7D60: 21 2F 3D E5 C3 92 5C 21 90 2F E5 21 2F 3D E5 21 55 16 E5 21 FF 5B E5 36; -7D78: C9 21 B5 5C 01 70 00 C9 3E 0D E5 C5 D5 F5 CD F1 20 F1 CD 94 3D CD F1 20; -7D90: D1 C1 E1 C9 E7 10 00 C9 3E 08 D3 1F E5 E7 54 1F 38 03 E7 7B 1B E1 DB FF; -7DA8: E6 80 28 F0 C9 3E 08 CD 9A 3D 11 00 00 DB 1F E6 02 47 DB 1F E6 02 B8 C0; -7DC0: 13 7B B2 20 F5 C3 E7 3E 3A 19 5D 32 F6 5C 21 16 5D 4F 3E 3C B1 D3 FF 77; -7DD8: CD 08 3E E6 80 28 1B CD AD 3D CD 16 3E CD 11 3E FE FF 28 0E E5 CD CA 1F; -7DF0: E1 FE 50 3E 00 20 02 3E 80 77 CD 36 1E 3E 50 0E; -7E00: FF 0D 20 FD 3D 20 F8 C9 11 FA 5C 2A F6 5C 19 7E C9 11 C8 5C 18 F5 CD 08; -7E18: 3E 06 08 0E 04 70 3E 08 CD 9A 3D 3E 20 06 0B CD 44 3E 46 3E 01 CD 44 3E; -7E30: DB 1F E6 04 20 09 AF CD 44 3E DB 1F E6 04 C0 04 0D C8 18 D9 D3 7F 78 F6; -7E48: 18 C3 00 08 D3 7F C5 47 DB 3F B8 C1 F5 78 F6 18 CD 00 08 F1 C8 C5 CD FD; -7E60: 3D C1 C9 4F CD EB 1F CD 11 3E E6 02 C4 AA 3E C5 CB 7E 28 0F CB 46 20 0B; -7E78: DB 3F B9 28 05 07 D3 3F 79 07 4F CD 08 3E 47 DB 3F B9 C5 C4 FD 3D C1 79; -7E90: CD 4C 3E C1 79 D3 3F 3A CD 5C B7 C8 AF 32 CD 5C 06 03 3E FF CD FF 3D 10; -7EA8: F9 C9 79 B7 1F 4F D0 C3 F6 1F CD EB 1F DB 1F E6 80 32 CD 5C DB 3F 67 CD; -7EC0: 44 3E 0E 7F 16 01 F3 3E C0 D3 1F C5 06 03 DB FF E6 C0 20 1E 13 7B B2 20; -7ED8: F5 10 F3 C1 FB 3E D0 D3 1F 3A D1 5C FE FF C8 CD 2B 27 3E FF 32 17 5D C3; -7EF0: 1B 27 C1 ED 60 DB FF E6 C0 28 FA FB F8 F3 DB 7F 18 F3 32 FF 5C C9 22 00; -7F08: 5D C9 3E A0 18 02 3E 80 32 FE 5C 16 0A D5 F3 3A FF 5C 3C D3 5F 2A 00 5D; -7F20: 0E 7F 3A FE 5C D3 1F FE A0 F5 CC BA 3F F1 C4 D5 3F D1 FB DB 1F 47 E6 7F; -7F38: C8 21 D8 29 E6 40 20 0B 78 E6 04 28 5B 15 20 CD 21 E2 29 3E D0 D3 1F 78; -7F50: E6 01 C2 E7 3E DB 3F B7 20 05 DB 5F FE 0A C8 E5 CD 97 1D E1 DF 21 13 2A; -7F68: DF DB 3F CD A3 1D 21 18 2A DF DB 5F CD A3 1D 21 FE 29 DF CD 52 10 FE 49; -7F80: C8 FE 52 28 0F FE 41 20 F2 CD 2B 27 3E 07 32 0F 5D C3 D3 01 3A F5 5C CD; -7F98: 63 3E CD A0 3E C3 13 3F 15 CA 48 3F D5 CD 08 3E E6 02 20 01 34 CD 98 3D; -7FB0: 3A F5 5C CD 63 3E D1 C3 15 3F 06 04 DB FF E6 C0 20 0F 13 7B B2 20 F5 10; -7FC8: F3 C9 DB FF E6 C0 28 FA F8 ED A3 18 F5 06 04 DB FF E6 C0 20 0F 13 7B B2; -7FE0: 20 F5 10 F3 C9 DB FF E6 C0 28 FA F8 ED A2 18 F5 FF FF FF FF FF FF FF FF; -7FF8: FF FF FF FF FF FF FF FF F3 01 2B 69 0B 78 B1 20 FB C3 C7 00 00 00 00 00; -8010: EF 10 00 C9 00 00 00 00 EF 18 00 C9 00 00 00 00 EF 20 00 C9 00 00 00 00; -8028: E3 F5 7E 23 23 22 5A 5B 2B 66 6F F1 C3 5C 00 00 E5 21 48 00 E5 21 00 5B; -8040: E5 21 38 00 E5 C3 00 5B E1 C9 01 FD 7F AF F3 ED 79 32 5C 5B FB 3D FD 77; -8058: 00 C3 21 03 22 58 5B 21 14 5B E3 E5 2A 58 5B E3 C3 00 5B F5 C5 01 FD 7F; -8070: 3A 5C 5B EE 10 F3 32 5C 5B ED 79 FB C1 F1 C9 CD 00 5B E5 2A 5A 5B E3 C9; -8088: F3 3A 5C 5B E6 EF 32 5C 5B 01 FD 7F ED 79 FB C3 C3 00 21 D8 06 18 03 21; -80A0: CA 07 08 01 FD 7F 3A 5C 5B F5 E6 EF F3 32 5C 5B ED 79 C3 E6 05 08 F1 01; -80B8: FD 7F F3 32 5C 5B ED 79 FB 08 C9 2A 8B 5B E9 06 08 78 D9 3D 01 FD 7F ED; -80D0: 79 21 00 C0 11 01 C0 01 FF 3F 3E FF 77 BE 20 51 AF 77 BE 20 4C ED B0 D9; -80E8: 10 DF 32 88 5B 0E FD 16 FF 1E BF 42 3E 0E ED 79 43 3E FF ED 79 18 38 00; -8100: C3 AF 17 C3 38 18 C3 CF 1E C3 04 1F C3 4A 00 C3 A2 03 C3 2A 18 C3 A8 18; -8118: C3 2D 01 C3 05 0A C3 A3 11 C3 D8 06 C3 CA 07 C3 A3 08 C3 F0 08 EF 01 3B; -8130: C9 D9 78 D3 FE 18 FE 42 3E 07 ED 79 43 3E FF ED 79 11 00 5B 21 6B 00 01; -8148: 58 00 ED B0 3E CF 32 5D 5B 31 FF 5B 3E 04 CD 64 1C DD 21 EC EB DD 22 83; -8160: 5B DD 36 0A 00 DD 36 0B C0 DD 36 0C 00 21 EC 2B 3E 01 22 85 5B 32 87 5B; -8178: 3E 05 CD 64 1C 21 FF FF 22 B4 5C 11 AF 3E 01 A8 00 EB EF 61 16 EB 23 22; -8190: 7B 5C 2B 01 40 00 ED 43 38 5C 22 B2 5C 21 00 3C 22 36 5C 2A B2 5C 23 F9; -81A8: ED 56 FD 21 3A 5C FD CB 01 E6 FB 21 0B 00 22 5F 5B AF 32 61 5B 32 63 5B; -81C0: 32 65 5B 21 00 EC 22 24 FF 3E 50 32 64 5B 21 0A 00 22 94 5B 22 96 5B 21; -81D8: B6 5C 22 4F 5C 11 89 05 01 15 00 EB ED B0 EB 2B 22 57 5C 23 22 53 5C 22; -81F0: 4B 5C 36 80 23 22 59 5C 36 0D 23 36 80 23 22 61 5C 22 63 5C 22 65 5C 3E; -8208: 38 32 8D 5C 32 8F 5C 32 48 5C AF 32 13 EC 3E 07 D3 FE 21 23 05 22 09 5C; -8220: FD 35 C6 FD 35 CA 21 9E 05 11 10 5C 01 0E 00 ED B0 FD CB 01 8E FD 36 00; -8238: FF FD 36 31 02 EF 6B 0D EF 04 3C 11 61 05 CD 7D 05 FD 36 31 02 FD CB 02; -8250: EE 21 FF 5B 22 81 5B CD 45 1F 3E 38 32 11 EC 32 0F EC CD 84 25 CD 20 1F; -8268: C3 9F 25 21 66 5B CB C6 FD 36 00 FF FD 36 31 02 21 1D 5B E5 ED 73 3D 5C; -8280: 21 BA 02 22 8B 5B CD 8E 22 CD CB 22 CA F8 21 FE 28 CA F8 21 FE 2D CA F8; -8298: 21 FE 2B CA F8 21 CD E0 22 CA F8 21 CD 45 1F 3A 0E EC CD 20 1F FE 04 C2; -82B0: AF 17 CD 97 22 CA AF 17 E1 C9 FD CB 00 7E 20 01 C9 2A 59 5C 22 5D 5C EF; -82C8: FB 19 78 B1 C2 F7 03 DF FE 0D C8 CD EF 21 FD CB 02 76 20 03 EF 6E 0D FD; -82E0: CB 02 B6 CD 45 1F 21 0D EC CB 76 20 07 23 7E FE 00 CC 81 38 CD 20 1F 21; -82F8: 3C 5C CB 9E 3E 19 FD 96 4F 32 8C 5C FD CB 01 FE FD 36 0A 01 21 00 3E E5; -8310: 21 1D 5B E5 ED 73 3D 5C 21 21 03 22 8B 5B C3 38 18 ED 7B B2 5C 33 21 FF; -8328: 5B 22 81 5B 76 FD CB 01 AE 21 66 5B CB 56 28 12 CD 45 1F DD 2A 83 5B 01; -8340: 14 00 DD 09 CD 56 1D CD 20 1F 3A 3A 5C 3C F5 21 00 00 FD 74 37 FD 74 26; -8358: 22 0B 5C 21 01 00 22 16 5C EF B0 16 FD CB 37 AE EF 6E 0D FD CB 02 EE F1; -8370: 47 FE 0A 38 0A FE 1D 38 04 C6 14 18 02 C6 07 EF EF 15 3E 20 D7 78 FE 1D; -8388: 38 12 D6 1D 06 00 4F 21 6C 04 09 09 5E 23 56 CD 7D 05 18 06 11 91 13 EF; -83A0: 0A 0C AF 11 36 15 EF 0A 0C ED 4B 45 5C EF 1B 1A 3E 3A D7 FD 4E 0D 06 00; -83B8: EF 1B 1A EF 97 10 3A 3A 5C 3C 28 1B FE 09 28 04 FE 15 20 03 FD 34 0D 01; -83D0: 03 00 11 70 5C 21 44 5C CB 7E 28 01 09 ED B8 FD 36 0A FF FD CB 01 9E 21; -83E8: 66 5B CB 86 C3 CB 25 3E 10 01 00 00 C3 4E 03 ED 43 49 5C CD 45 1F 78 B1; -8400: 28 08 ED 43 49 5C ED 43 08 EC CD 20 1F 2A 5D 5C EB 21 EF 03 E5 2A 61 5C; -8418: 37 ED 52 E5 60 69 EF 6E 19 20 06 EF B8 19 EF E8 19 C1 79 3D B0 20 13 CD; -8430: 45 1F E5 2A 49 5C CD 4A 33 22 49 5C E1 CD 20 1F 18 28 C5 03 03 03 03 2B; -8448: ED 5B 53 5C D5 EF 55 16 E1 22 53 5C C1 C5 13 2A 61 5C 2B 2B ED B8 2A 49; -8460: 5C EB C1 70 2B 71 2B 73 2B 72 F1 C9 8C 04 97 04 A6 04 B0 04 C1 04 D4 04; -8478: E0 04 E0 04 F3 04 01 05 12 05 23 05 31 05 42 05 4E 05 61 05 4D 45 52 47; -8490: 45 20 65 72 72 6F F2 57 72 6F 6E 67 20 66 69 6C 65 20 74 79 70 E5 43 4F; -84A8: 44 45 20 65 72 72 6F F2 54 6F 6F 20 6D 61 6E 79 20 62 72 61 63 6B 65 74; -84C0: F3 46 69 6C 65 20 61 6C 72 65 61 64 79 20 65 78 69 73 74 F3 49 6E 76 61; -84D8: 6C 69 64 20 6E 61 6D E5 46 69 6C 65 20 64 6F 65 73 20 6E 6F 74 20 65 78; -84F0: 69 73 F4 49 6E 76 61 6C 69 64 20 64 65 76 69 63; -8500: E5 49 6E 76 61 6C 69 64 20 62 61 75 64 20 72 61 74 E5 49 6E 76 61 6C 69; -8518: 64 20 6E 6F 74 65 20 6E 61 6D E5 4E 75 6D 62 65 72 20 74 6F 6F 20 62 69; -8530: E7 4E 6F 74 65 20 6F 75 74 20 6F 66 20 72 61 6E 67 E5 4F 75 74 20 6F 66; -8548: 20 72 61 6E 67 E5 54 6F 6F 20 6D 61 6E 79 20 74 69 65 64 20 6E 6F 74 65; -8560: F3 7F 20 31 39 38 36 20 53 69 6E 63 6C 61 69 72 20 52 65 73 65 61 72 63; -8578: 68 20 4C 74 E4 1A E6 7F D5 D7 D1 1A 13 87 30 F5 C9 F4 09 A8 10 4B F4 09; -8590: C4 15 53 81 0F C4 15 52 34 5B 2F 5B 50 80 01 00 06 00 0B 00 01 00 01 00; -85A8: 06 00 10 00 E1 01 FD 7F AF F3 32 5C 5B ED 79 FB ED 7B 3D 5C 7E 32 5E 5B; -85C0: 3C FE 1E 30 03 EF 5D 5B 3D FD 77 00 2A 5D 5C 22 5F 5C EF C5 16 C9 3E 7F; -85D8: DB FE 1F D8 3E FE DB FE 1F D8 CD AC 05 14 FB 08 11 4A 5B D5 FD CB 02 9E; -85F0: E5 2A 3D 5C 5E 23 56 A7 21 7F 10 ED 52 20 38 E1 ED 7B 3D 5C D1 D1 ED 53; -8608: 3D 5C E5 11 10 06 D5 E9 38 09 28 04 CD AC 05 07 E1 18 EF FE 0D 28 0E 2A; -8620: 5A 5B E5 EF 85 0F E1 22 5A 5B E1 18 DD E1 3A 5C 5B F6 10 F5 C3 4A 5B E1; -8638: 11 3D 06 D5 E9 D8 C8 18 D3 EF 18 00 EF 8C 1C FD CB 01 7E 28 14 EF F1 2B; -8650: 79 3D B0 28 04 CD AC 05 24 1A E6 DF FE 50 C2 12 19 2A 5D 5C 7E FE 3B C2; -8668: 12 19 EF 20 00 EF 82 1C FD CB 01 7E 28 07 EF 99 1E ED 43 71 5B EF 18 00; -8680: FE 0D 28 05 FE 3A C2 12 19 CD A1 18 ED 4B 71 5B 78 B1 20 04 CD AC 05 25; -8698: 21 B8 06 5E 23 56 23 EB 7C FE 25 30 0A A7 ED 42 30 05 EB 23 23 18 EC EB; -86B0: 5E 23 56 ED 53 5F 5B C9 32 00 A5 0A 6E 00 D4 04 2C 01 C3 01 58 02 E0 00; -86C8: B0 04 6E 00 60 09 36 00 C0 12 19 00 80 25 0B 00 21 61 5B 7E A7 28 06 36; -86E0: 00 23 7E 37 C9 CD D6 05 F3 D9 ED 5B 5F 5B 2A 5F 5B CB 3C CB 1D B7 06 FA; -86F8: D9 0E FD 16 FF 1E BF 42 3E 0E ED 79 ED 78 F6 F0 E6 FB 43 ED 79 67 42 ED; -8710: 78 E6 80 28 09 D9 05 D9 20 F4 AF F5 18 39 ED 78 E6 80 20 F1 ED 78 E6 80; -8728: 20 EB D9 01 FD FF 3E 80 08 19 00 00 00 00 2B 7C B5 20 FB ED 78 E6 80 CA; -8740: 4B 07 08 37 1F 38 0D 08 C3 31 07 08 B7 1F 38 04 08 C3 31 07 37 F5 D9 7C; -8758: F6 04 43 ED 79 D9 62 6B 01 07 00 B7 ED 42 2B 7C B5 20 FB 01 FD FF 19 19; -8770: 19 ED 78 E6 80 28 08 2B 7C B5 20 F5 F1 FB C9 ED 78 E6 80 20 EC ED 78 E6; -8788: 80 20 E6 62 6B 01 02 00 CB 3C CB 1D B7 ED 42 01 FD FF 3E 80 08 00 00 00; -87A0: 00 19 2B 7C B5 20 FB ED 78 E6 80 CA B7 07 08 37 1F 38 0D 08 C3 9D 07 08; -87B8: B7 1F 38 04 08 C3 9D 07 21 61 5B 36 01 23 77 F1 FB C9 F5 3A 65 5B B7 28; -87D0: 0F 3D 32 65 5B 20 04 F1 C3 72 08 F1 32 0F 5C C9 F1 FE A3 38 0D 2A 5A 5B; -87E8: E5 EF 52 0B E1 22 5A 5B 37 C9 21 3B 5C CB 86 FE 20 20 02 CB C6 FE 7F 38; -8800: 02 3E 3F FE 20 38 17 F5 21 63 5B 34 3A 64 5B BE 30 08 CD 22 08 3E 01 32; -8818: 63 5B F1 C3 A3 08 FE 0D 20 0E AF 32 63 5B 3E 0D CD A3 08 3E 0A C3 A3 08; -8830: FE 06 20 1F ED 4B 63 5B 1E 00 1C 0C 79 B8 28 08 D6 08 28 04 30 FA 18 F2; -8848: D5 3E 20 CD CA 07 D1 1D C8 18 F5 FE 16 28 09 FE 17 28 05 FE 10 D8 18 09; -8860: 32 0E 5C 3E 02 32 65 5B C9 32 0E 5C 3E 02 32 65 5B C9 57 3A 0E 5C FE 16; -8878: 28 08 FE 17 3F C0 3A 0F 5C 57 3A 64 5B BA 28 02 30 06 47 7A 90 57 18 F2; -8890: 7A B7 CA 22 08 3A 63 5B BA C8 D5 3E 20 CD CA 07 D1 18 F2 F5 0E FD 16 FF; -88A8: 1E BF 42 3E 0E ED 79 CD D6 05 ED 78 E6 40 20 F7 2A 5F 5B 11 02 00 B7 ED; -88C0: 52 EB F1 2F 37 06 0B F3 C5 F5 3E FE 62 6B 01 FD BF D2 DA 08 E6 F7 ED 79; -88D8: 18 06 F6 08 ED 79 18 00 2B 7C B5 20 FB 00 00 00 F1 C1 B7 1F 10 DA FB C9; -88F0: 21 72 5B 36 2B 21 79 09 CD 5F 09 CD 15 09 21 80 09 CD 5F 09 21 72 5B AF; -8908: BE 28 03 35 18 E7 21 82 09 CD 5F 09 C9 21 71 5B 36 FF CD 26 09 21 71 5B; -8920: AF BE C8 35 18 F4 11 00 C0 ED 4B 71 5B 37 CB 10 37 CB 10 79 2F 4F AF F5; -8938: D5 C5 CD 6D 09 C1 D1 1E 00 28 01 5A F1 B3 F5 05 CB 3A CB 3A D5 C5 30 EA; -8950: C1 D1 F1 06 03 C5 F5 CD A3 08 F1 C1 10 F7 C9 46 23 7E E5 C5 CD A3 08 C1; -8968: E1 23 10 F5 C9 EF AA 22 47 04 AF 37 1F 10 FD A6 C9 06 1B 31 1B 4C 00 03; -8980: 01 0A 02 1B 32 F3 C5 11 37 00 21 3C 00 19 10 FD 4D 44 EF 30 00 F3 D5 FD; -8998: E1 E5 DD E1 FD 36 10 FF 01 C9 FF DD 09 DD 36 03 3C DD 36 01 FF DD 36 04; -89B0: 0F DD 36 05 05 DD 36 21 00 DD 36 0A 00 DD 36 0B 00 DD 36 16 FF DD 36 17; -89C8: 00 DD 36 18 00 EF F1 2B F3 DD 73 06 DD 72 07 DD 73 0C DD 72 0D EB 09 DD; -89E0: 75 08 DD 74 09 C1 C5 05 48 06 00 CB 21 FD E5 E1 09 DD E5 C1 71 23 70 B7; -89F8: FD CB 10 16 C1 05 C5 DD 70 02 20 9C C1 FD 36 27 1A FD 36 28 0B FD E5 E1; -8A10: 01 2B 00 09 EB 21 31 0A 01 0D 00 ED B0 16 07 1E F8 CD 7C 0E 16 0B 1E FF; -8A28: CD 7C 0E 14 CD 7C 0E 18 4C EF A4 01 05 34 DF 75 F4 38 75 05 38 C9 3E 7F; -8A40: DB FE 1F D8 3E FE DB FE 1F C9 01 11 00 18 03 01 00 00 FD E5 E1 09 FD 75; -8A58: 23 FD 74 24 FD 7E 10 FD 77 22 FD 36 21 01 C9 5E 23 56 D5 DD E1 C9 FD 6E; -8A70: 23 FD 66 24 23 23 FD 75 23 FD 74 24 C9 CD 4F 0A FD CB 22 1E 38 06 CD 67; -8A88: 0A CD 5C 0B FD CB 21 26 38 05 CD 6E 0A 18 E9 CD 91 0F D5 CD 42 0F D1 FD; -8AA0: 7E 10 FE FF 20 05 CD 93 0E FB C9 1B CD 76 0F CD C1 0F CD 91 0F 18 E8 48; -8AB8: 5A 59 58 57 55 56 4D 54 29 28 4E 4F 21 CD E3 0E D8 DD 34 06 C0 DD 34 07; -8AD0: C9 E5 0E 00 CD C5 0A 38 08 FE 26 20 0F 3E 80 E1 C9 FD 7E 21 FD B6 10 FD; -8AE8: 77 10 18 F3 FE 23 20 03 0C 18 E1 FE 24 20 03 0D 18 DA CB 6F 20 06 F5 3E; -8B00: 0C 81 4F F1 E6 DF D6 41 DA 22 0F FE 07 D2 22 0F C5 06 00 4F 21 F9 0D 09; -8B18: 7E C1 81 E1 C9 E5 D5 DD 6E 06 DD 66 07 11 00 00 7E FE 30 38 18 FE 3A 30; -8B30: 14 23 E5 CD 50 0B D6 30 26 00 6F 19 38 04 EB E1 18 E6 C3 1A 0F DD 75 06; -8B48: DD 74 07 D5 C1 D1 E1 C9 21 00 00 06 0A 19 38 EA 10 FB EB C9 CD 3E 0A 38; -8B60: 08 CD 93 0E FB CD AC 05 14 CD C5 0A DA A2 0D CD F0 0D 06 00 CB 21 21 CA; -8B78: 0D 09 5E 23 56 EB CD 84 0B 18 D9 C9 E9 CD C5 0A DA A1 0D FE 21 C8 18 F5; -8B90: CD 1D 0B 79 FE 09 D2 12 0F CB 27 CB 27 47 CB 27 80 DD 77 03 C9 C9 DD 7E; -8BA8: 0B 3C FE 05 CA 2A 0F DD 77 0B 11 0C 00 CD 27 0C DD 7E 06 77 23 DD 7E 07; -8BC0: 77 C9 DD 7E 16 11 17 00 B7 FA F0 0B CD 27 0C DD 7E 06 BE 20 1B 23 DD 7E; -8BD8: 07 BE 20 14 DD 35 16 DD 7E 16 B7 F0 DD CB 0A 46 C8 DD 36 16 00 AF 18 1B; -8BF0: DD 7E 16 3C FE 05 CA 2A 0F DD 77 16 CD 27 0C DD; -8C00: 7E 06 77 23 DD 7E 07 77 DD 7E 0B 11 0C 00 CD 27 0C 7E DD 77 06 23 7E DD; -8C18: 77 07 DD 35 0B F0 DD 36 0B 00 DD CB 0A C6 C9 DD E5 E1 19 06 00 4F CB 21; -8C30: 09 C9 CD 1D 0B 78 B7 C2 12 0F 79 FE 3C DA 12 0F FE F1 D2 12 0F DD 7E 02; -8C48: B7 C0 06 00 C5 E1 29 29 E5 C1 FD E5 EF 2B 2D F3 FD E1 FD E5 FD E5 E1 01; -8C60: 2B 00 09 FD 21 3A 5C E5 21 76 0C 22 5A 5B 21 14 5B E3 E5 C3 00 5B F3 EF; -8C78: A2 2D F3 FD E1 FD 71 27 FD 70 28 C9 CD 1D 0B 79 FE 40 D2 12 0F 2F 5F 16; -8C90: 07 CD 7C 0E C9 CD 1D 0B 79 FE 10 D2 12 0F DD 77 04 DD 5E 02 3E 08 83 57; -8CA8: 59 CD 7C 0E C9 DD 5E 02 3E 08 83 57 1E 1F DD 73 04 C9 CD 1D 0B 79 FE 08; -8CC0: D2 12 0F 06 00 21 E8 0D 09 7E FD 77 29 C9 CD 1D 0B 16 0B 59 CD 7C 0E 14; -8CD8: 58 CD 7C 0E C9 CD 1D 0B 79 3D FA 12 0F FE 10 D2 12 0F DD 77 01 C9 CD 1D; -8CF0: 0B 79 CD A3 11 C9 FD 36 10 FF C9 CD 19 0E DA 81 0D CD AC 0D CD B4 0D AF; -8D08: DD 77 21 CD C8 0E CD 1D 0B 79 B7 CA 12 0F FE 0D D2 12 0F FE 0A 38 13 CD; -8D20: 00 0E CD 74 0D 73 23 72 CD 74 0D 23 73 23 72 23 18 06 DD 71 05 CD 00 0E; -8D38: CD 74 0D CD E3 0E FE 5F 20 2C CD C5 0A CD 1D 0B 79 FE 0A 38 12 E5 D5 CD; -8D50: 00 0E E1 19 4B 42 EB E1 73 23 72 59 50 18 C9 DD 71 05 E5 D5 CD 00 0E E1; -8D68: 19 EB E1 C3 3B 0D 73 23 72 C3 9C 0D DD 7E 21 3C FE 0B CA 3A 0F DD 77 21; -8D80: C9 CD C8 0E DD 36 21 01 CD AC 0D CD B4 0D DD 4E 05 E5 CD 00 0E E1 73 23; -8D98: 72 C3 9C 0D E1 23 23 E5 C9 E1 FD 7E 21 FD B6 10 FD 77 10 C9 DD E5 E1 01; -8DB0: 22 00 09 C9 E5 FD E5 E1 01 11 00 09 06 00 DD 4E 02 CB 21 09 D1 73 23 72; -8DC8: EB C9 FB 0C 85 0B 90 0B A5 0B A6 0B C2 0B 32 0C 84 0C 95 0C AD 0C BA 0C; -8DE0: CE 0C DD 0C EE 0C F6 0C 00 04 0B 0D 08 0C 0E 0A 01 0F 00 21 B7 0A ED B1; -8DF8: C9 09 0B 00 02 04 05 07 E5 06 00 21 0C 0E 09 16 00 5E E1 C9 80 06 09 0C; -8E10: 12 18 24 30 48 60 04 08 10 FE 30 D8 FE 3A 3F C9 4F DD 7E 03 81 FE 80 D2; -8E28: 32 0F 4F DD 7E 02 B7 20 0E 79 2F E6 7F CB 3F CB 3F 16 06 5F CD 7C 0E DD; -8E40: 71 00 DD 7E 02 FE 03 D0 21 96 10 06 00 79 D6 15 30 05 11 BF 0F 18 07 4F; -8E58: CB 21 09 5E 23 56 EB DD 56 02 CB 22 5D CD 7C 0E 14 5C CD 7C 0E DD CB 04; -8E70: 66 C8 16 0D FD 7E 29 5F CD 7C 0E C9 C5 01 FD FF ED 51 01 FD BF ED 59 C1; -8E88: C9 C5 01 FD FF ED 79 ED 78 C1 C9 16 07 1E FF CD 7C 0E 16 08 1E 00 CD 7C; -8EA0: 0E 14 CD 7C 0E 14 CD 7C 0E CD 4F 0A FD CB 22 1E 38 06 CD 67 0A CD 8D 11; -8EB8: FD CB 21 26 38 05 CD 6E 0A 18 E9 FD 21 3A 5C C9 E5 D5 DD 6E 06 DD 66 07; -8ED0: 2B 7E FE 20 28 FA FE 0D 28 F6 DD 75 06 DD 74 07 D1 E1 C9 E5 D5 C5 DD 6E; -8EE8: 06 DD 66 07 7C DD BE 09 20 09 7D DD BE 08 20 03 37 18 0A 7E FE 20 28 09; -8F00: FE 0D 28 05 B7 C1 D1 E1 C9 23 DD 75 06 DD 74 07 18 DA CD 93 0E FB CD AC; -8F18: 05 29 CD 93 0E FB CD AC 05 27 CD 93 0E FB CD AC 05 26 CD 93 0E FB CD AC; -8F30: 05 1F CD 93 0E FB CD AC 05 28 CD 93 0E FB CD AC 05 2A CD 4F 0A FD CB 22; -8F48: 1E 38 21 CD 67 0A CD D1 0A FE 80 28 17 CD 20 0E DD 7E 02 FE 03 30 0A 16; -8F60: 08 82 57 DD 5E 04 CD 7C 0E CD 6E 11 FD CB 21 26 D8 CD 6E 0A 18 CF E5 FD; -8F78: 6E 27 FD 66 28 01 64 00 B7 ED 42 E5 C1 E1 0B 78 B1 20 FB 1B 7A B3 20 E6; -8F90: C9 11 FF FF CD 4A 0A FD CB 22 1E 38 12 D5 5E 23 56 EB 5E 23 56 D5 E1 C1; -8FA8: B7 ED 42 38 02 C5 D1 FD CB 21 26 38 05 CD 6E 0A 18 DD FD 73 25 FD 72 26; -8FC0: C9 AF FD 77 2A CD 4F 0A FD CB 22 1E DA 5A 10 CD 67 0A FD E5 E1 01 11 00; -8FD8: 09 06 00 DD 4E 02 CB 21 09 5E 23 56 EB E5 5E 23 56 EB FD 5E 25 FD 56 26; -8FF0: B7 ED 52 EB E1 28 05 73 23 72 18 5E DD 7E 02 FE 03 30 09 16 08 82 57 1E; -9008: 00 CD 7C 0E CD 8D 11 DD E5 E1 01 21 00 09 35 20 0D CD 5C 0B FD 7E 21 FD; -9020: A6 10 20 36 18 17 FD E5 E1 01 11 00 09 06 00 DD 4E 02 CB 21 09 5E 23 56; -9038: 13 13 72 2B 73 CD D1 0A 4F FD 7E 21 FD A6 10 20 11 79 FE 80 28 0C CD 20; -9050: 0E FD 7E 21 FD B6 2A FD 77 2A FD CB 21 26 38 06 CD 6E 0A C3 C8 0F 11 01; -9068: 00 CD 76 0F CD 4F 0A FD CB 2A 1E 30 17 CD 67 0A DD 7E 02 FE 03 30 0A 16; -9080: 08 82 57 DD 5E 04 CD 7C 0E CD 6E 11 FD CB 21 26 D8 CD 6E 0A 18 D9 BF 0F; -9098: DC 0E 07 0E 3D 0D 7F 0C CC 0B 22 0B 82 0A EB 09 5D 09 D6 08 57 08 DF 07; -90B0: 6E 07 03 07 9F 06 40 06 E6 05 91 05 41 05 F6 04 AE 04 6B 04 2C 04 F0 03; -90C8: B7 03 82 03 4F 03 20 03 F3 02 C8 02 A1 02 7B 02 57 02 36 02 16 02 F8 01; -90E0: DC 01 C1 01 A8 01 90 01 79 01 64 01 50 01 3D 01 2C 01 1B 01 0B 01 FC 00; -90F8: EE 00 E0 00 D4 00 C8 00 BD 00 B2 00 A8 00 9F 00 96 00 8D 00 85 00 7E 00; -9110: 77 00 70 00 6A 00 64 00 5E 00 59 00 54 00 4F 00 4B 00 47 00 43 00 3F 00; -9128: 3B 00 38 00 35 00 32 00 2F 00 2D 00 2A 00 28 00 25 00 23 00 21 00 1F 00; -9140: 1E 00 1C 00 1A 00 19 00 18 00 16 00 15 00 14 00 13 00 12 00 11 00 10 00; -9158: 0F 00 0E 00 0D 00 0C 00 0C 00 0B 00 0B 00 0A 00 09 00 09 00 08 00 DD 7E; -9170: 01 B7 F8 F6 90 CD A3 11 DD 7E 00 CD A3 11 DD 7E 04 CB A7 CB 27 CB 27 CB; -9188: 27 CD A3 11 C9 DD 7E 01 B7 F8 F6 80 CD A3 11 DD 7E 00 CD A3 11 3E 40 CD; -91A0: A3 11 C9 6F 01 FD FF 3E 0E ED 79 01 FD BF 3E FA ED 79 1E 03 1D 20 FD 00; -91B8: 00 00 00 7D 16 08 1F 6F D2 C9 11 3E FE ED 79 18 06 3E FA ED 79 18 00 1E; -91D0: 02 1D 20 FD 00 C6 00 7D 15 20 E3 00 00 C6 00 00 00 3E FE ED 79 1E 06 1D; -91E8: 20 FD C9 21 66 5B CB EE 18 13 21 66 5B CB E6 18 0C 21 66 5B CB FE 18 05; -9200: 21 66 5B CB F6 21 66 5B CB 9E DF FE 21 C2 BE 13 21 66 5B CB DE E7 C3 BE; -9218: 13 CD AC 05 0B 22 74 5B DD 7E 00 32 71 5B DD 6E 0B DD 66 0C 22 72 5B DD; -9230: 6E 0D DD 66 0E 22 78 5B DD 6E 0F DD 66 10 22 76 5B B7 28 0A FE 03 28 06; -9248: DD 7E 0E 32 76 5B DD E5 E1 23 11 67 5B 01 0A 00 ED B0 21 66 5B CB 6E C2; -9260: AD 1B 21 71 5B 11 7A 5B 01 07 00 ED B0 CD 2E 1C 3A 7A 5B 47 3A 71 5B B8; -9278: 20 06 FE 03 28 12 38 04 CD AC 05 1D 3A 66 5B CB 77 20 3A CB 7F CA DB 12; -9290: 3A 66 5B CB 77 28 04 CD AC 05 1C 2A 7B 5B ED 5B 72 5B 7C B5 28 08 ED 52; -92A8: 30 04 CD AC 05 1E 2A 7D 5B 7C B5 20 03 2A 74 5B 3A 71 5B A7 20 03 2A 53; -92C0: 5C CD 7E 13 C9 ED 4B 72 5B C5 03 EF 30 00 36 80 EB D1 E5 CD 7E 13 E1 EF; -92D8: CE 08 C9 ED 5B 72 5B 2A 7D 5B E5 7C B5 20 06 13 13 13 EB 18 09 2A 7B 5B; -92F0: EB 37 ED 52 38 09 11 05 00 19 44 4D EF 05 1F E1; -9300: 3A 71 5B A7 28 2F 7C B5 28 0B 2B 46 2B 4E 2B 03 03 03 EF E8 19 2A 59 5C; -9318: 2B ED 4B 72 5B C5 03 03 03 3A 7F 5B F5 EF 55 16 23 F1 77 D1 23 73 23 72; -9330: 23 CD 7E 13 C9 21 66 5B CB 8E ED 5B 53 5C 2A 59 5C 2B EF E5 19 ED 4B 72; -9348: 5B 2A 53 5C EF 55 16 23 ED 4B 76 5B 09 22 4B 5C 3A 79 5B 67 E6 C0 20 10; -9360: 3A 78 5B 6F 22 42 5C FD 36 0A 00 21 66 5B CB CE 2A 53 5C ED 5B 72 5B 2B; -9378: 22 57 5C 23 18 B3 7A B3 C8 CD 4B 1C C9 EF 8C 1C FD CB 01 7E C8 F5 EF F1; -9390: 2B F1 C9 E7 CD 85 13 C8 F5 79 B0 28 1D 21 0A 00 ED 42 38 16 D5 C5 21 67; -93A8: 5B 06 0A 3E 20 77 23 10 FC C1 E1 11 67 5B ED B0 F1 C9 CD AC 05 21 EF 8C; -93C0: 1C FD CB 01 7E 28 40 01 11 00 3A 74 5C A7 28 02 0E 22 EF 30 00 D5 DD E1; -93D8: 06 0B 3E 20 12 13 10 FC DD 36 01 FF EF F1 2B 21 F6 FF 0B 09 03 30 11 3A; -93F0: 74 5C A7 20 04 CD AC 05 0E 78 B1 28 0A 01 0A 00 DD E5 E1 23 EB ED B0 DF; -9408: FE E4 20 53 3A 74 5C FE 03 CA 19 12 E7 EF B2 28 30 15 21 00 00 FD CB 01; -9420: 76 28 02 CB F9 3A 74 5C 3D 28 19 CD AC 05 01 C2 19 12 FD CB 01 7E 28 19; -9438: 4E 23 7E DD 77 0B 23 7E DD 77 0C 23 DD 71 0E 3E 01 CB 71 28 01 3C DD 77; -9450: 00 EB E7 FE 29 20 D8 E7 CD A1 18 EB C3 19 15 FE AA 20 1F 3A 74 5C FE 03; -9468: CA 19 12 E7 CD A1 18 DD 36 0B 00 DD 36 0C 1B 21 00 40 DD 75 0D DD 74 0E; -9480: 18 4D FE AF 20 4F 3A 74 5C FE 03 CA 19 12 E7 EF 48 20 20 0C 3A 74 5C A7; -9498: CA 19 12 EF E6 1C 18 0F EF 82 1C DF FE 2C 28 0C 3A 74 5C A7 CA 19 12 EF; -94B0: E6 1C 18 04 E7 EF 82 1C CD A1 18 EF 99 1E DD 71 0B DD 70 0C EF 99 1E DD; -94C8: 71 0D DD 70 0E 60 69 DD 36 00 03 18 44 FE CA 28 09 CD A1 18 DD 36 0E 80; -94E0: 18 17 3A 74 5C A7 C2 19 12 E7 EF 82 1C CD A1 18 EF 99 1E DD 71 0D DD 70; -94F8: 0E DD 36 00 00 2A 59 5C ED 5B 53 5C 37 ED 52 DD 75 0B DD 74 0C 2A 4B 5C; -9510: ED 52 DD 75 0F DD 74 10 EB 3A 66 5B CB 5F C2 1D 12 3A 74 5C A7 20 04 EF; -9528: 70 09 C9 EF 61 07 C9 21 F5 EE CB 86 CB CE 2A 49 5C 7C B5 20 03 22 06 EC; -9540: 3A DB F9 F5 2A 9A FC CD 4A 33 22 D7 F9 CD 22 32 CD D6 30 F1 B7 28 0C F5; -9558: CD DF 30 EB CD 6A 32 F1 3D 18 F1 0E 00 CD B4 30 41 3A 15 EC 4F C5 D5 CD; -9570: DF 30 3A F5 EE CB 4F 28 1D D5 E5 11 20 00 19 CB 46 28 11 23 56 23 5E B7; -9588: 2A 49 5C ED 52 20 05 21 F5 EE CB C6 E1 D1 C5 E5 01 23 00 ED B0 E1 C1 D5; -95A0: C5 EB 21 F5 EE CB 46 28 2A 06 00 2A 06 EC 7C B5 28 0E E5 CD 41 2E E1 30; -95B8: 12 2B 04 22 06 EC 18 EB CD 41 2E D4 63 2E 21 F5 EE 36 00 78 C1 C5 48 47; -95D0: CD 11 2A C1 D1 79 04 B8 30 95 3A F5 EE CB 4F 28 21 CB 47 20 1D 2A 49 5C; -95E8: 7C B5 28 08 22 9A FC CD 22 32 18 09 22 9A FC CD 52 33 22 49 5C D1 C1 C3; -9600: 36 15 D1 C1 BF F5 79 48 CD B4 30 EB F5 CD 04 36 F1 11 23 00 19 0C B9 30; -9618: F3 F1 C8 CD 07 2A CD 78 2B 2A 06 EC 2B 7C B5 22 06 EC 20 F2 C3 11 2A C9; -9630: 06 00 3A 15 EC 57 C3 5E 3B 06 00 E5 48 CD B4 30 CD 6A 32 E1 D0 CD DF 30; -9648: C5 E5 21 23 00 19 3A 15 EC 4F B8 28 0E C5 C5 01 23 00 ED B0 C1 79 04 B8; -9660: 20 F4 C1 E1 CD 18 36 01 23 00 ED B0 37 C1 C9 06 00 CD 2B 32 D0 C5 E5 3A; -9678: 15 EC 4F CD B4 30 CD 1E 31 30 26 1B 21 23 00 19 EB C5 78 B9 28 0C C5 01; -9690: 23 00 ED B8 C1 78 0D B9 38 F4 EB 13 C1 E1 CD 2C 36 01 23 00 ED B0 37 C1; -96A8: C9 E1 C1 C9 D5 26 00 68 19 57 78 5E 72 53 23 3C FE 20 38 F7 7B FE 00 D1; -96C0: C9 D5 21 20 00 19 E5 57 3E 1F 18 07 5E 72 53 B8 28 04 3D 2B 18 F6 7B FE; -96D8: 00 E1 D1 C9 B1 C9 BC BE C3 AF B4 93 91 92 95 98 98 98 98 98 98 98 7F 81; -96F0: 2E 6C 6E 70 48 94 56 3F 41 2B 17 1F 37 77 44 0F 59 2B 43 2D 51 3A 6D 42; -9708: 0D 49 5C 44 15 5D 01 3D 02 06 00 67 1E 06 CB 0E 67 19 06 0C 53 1A 00 EE; -9720: 1C 0C 6F 1A 04 3D 06 CC 06 0E 81 19 04 00 AB 1D 0E 78 21 0E 8C 21 0E D5; -9738: 21 0E 62 18 0C AA 21 0D 02 1A 0E 75 1B 08 00 80 1E 03 4F 1E 00 5F 1E 0D; -9750: 0D 1A 00 6B 0D 09 00 DC 22 06 00 3A 1F 0E AB 19 0E EB 19 03 42 1E 09 0E; -9768: BE 21 0C A7 21 0E 74 21 0E 71 1B 0B 0B 0B 0B 08 00 F8 03 09 0E AE 21 07; -9780: 07 07 07 07 07 08 00 7A 1E 06 00 94 22 0E 8C 1A 06 2C 0A 00 36 17 06 00; -9798: E5 16 0E 41 06 0A 2C 0A 0C F0 1A 0E 0C 1C 0E E5 1B 0C 2B 1B 0E 17 23 FD; -97B0: CB 01 BE EF FB 19 AF 32 47 5C 3D 32 3A 5C 18 01 E7 EF BF 16 FD 34 0D FA; -97C8: 12 19 DF 06 00 FE 0D CA 63 18 FE 3A 28 EA 21 21 18 E5 4F E7 79 D6 CE 30; -97E0: 13 C6 CE 21 A9 17 FE A3 28 16 21 AC 17 FE A4 28 0F C3 12 19 4F 21 DC 16; -97F8: 09 4E 09 18 03 2A 74 5C 7E 23 22 74 5C 01 FD 17 C5 4F FE 20 30 0C 21 B5; -9810: 18 06 00 09 4E 09 E5 DF 05 C9 DF B9 C2 12 19 E7 C9 CD D6 05 38 04 CD AC; -9828: 05 14 FD CB 0A 7E C2 A8 18 2A 42 5C CB 7C 28 14 21 FE FF 22 45 5C 2A 61; -9840: 5C 2B ED 5B 59 5C 1B 3A 44 5C 18 36 EF 6E 19 3A 44 5C 28 1C A7 20 46 47; -9858: 7E E6 C0 78 28 12 CD AC 05 FF C1 FD CB 01 7E C8 2A 55 5C 3E C0 A6 C0 AF; -9870: FE 01 CE 00 56 23 5E ED 53 45 5C 23 5E 23 56 EB 19 23 22 55 5C EB 22 5D; -9888: 5C 57 1E 00 FD 36 0A FF 15 FD 72 0D CA C0 17 14 EF 8B 19 28 0B CD AC 05; -98A0: 16 FD CB 01 7E C0 C1 C1 DF FE 0D 28 B6 FE 3A CA C0 17 C3 12 19 24 43 46; -98B8: 1E 4C 20 53 5E 4D 86 57 88 06 02 05 EF DE 1C BF C1 CC A1 18 EB 2A 74 5C; -98D0: 4E 23 46 EB C5 C9 EF DE 1C BF C1 CC A1 18 EB 2A 74 5C 4E 23 46 EB E5 21; -98E8: F8 18 22 5A 5B 21 14 5B E3 E5 60 69 E3 C3 00 5B C9 EF 1F 1C C9 C1 EF 56; -9900: 1C CD A1 18 C9 EF 6C 1C C9 E7 EF 7A 1C C9 EF 82 1C C9 CD AC 05 0B EF 8C; -9918: 1C C9 FD CB 01 7E FD CB 02 86 28 03 EF 4D 0D F1 3A 74 5C D6 A7 EF FC 21; -9930: CD A1 18 2A 8F 5C 22 8D 5C 21 91 5C 7E 07 AE E6 AA AE 77 C9 EF BE 1C C9; -9948: F1 3A 66 5B E6 0F 32 66 5B 3A 74 5C D6 74 32 74 5C CA EB 11 3D CA F2 11; -9960: 3D CA F9 11 C3 00 12 C1 FD CB 01 7E 28 10 2A 65 5C 11 FB FF 19 22 65 5C; -9978: EF E9 34 DA 63 18 C3 C1 17 FE CD 20 09 E7 CD 0E 19 CD A1 18 18 18 CD A1; -9990: 18 2A 65 5C 36 00 23 36 00 23 36 01 23 36 00 23 36 00 23 22 65 5C EF 16; -99A8: 1D C9 E7 CD F9 18 FD CB 01 7E 28 2E DF 22 5F 5C 2A 57 5C 7E FE 2C 28 0B; -99C0: 1E E4 EF 86 1D 30 04 CD AC 05 0D 23 22 5D 5C 7E EF 56 1C DF 22 57 5C 2A; -99D8: 5F 5C FD 36 26 00 22 5D 5C 7E DF FE 2C 28 C3 CD A1 18 C9 FD CB 01 7E 20; -99F0: 0B EF FB 24 FE 2C C4 A1 18 E7 18 F5 3E E4 EF 39; -9A00: 1E C9 EF 67 1E 01 00 00 EF 45 1E 18 03 EF 99 1E 78 B1 20 04 ED 4B B2 5C; -9A18: C5 ED 5B 4B 5C 2A 59 5C 2B EF E5 19 EF 6B 0D 2A 65 5C 11 32 00 19 D1 ED; -9A30: 52 30 08 2A B4 5C A7 ED 52 30 04 CD AC 05 15 ED 53 B2 5C D1 E1 C1 ED 7B; -9A48: B2 5C 33 C5 E5 ED 73 3D 5C D5 C9 D1 FD 66 0D 24 E3 33 ED 4B 45 5C C5 E5; -9A60: ED 73 3D 5C D5 EF 67 1E 01 14 00 EF 05 1F C9 C1 E1 D1 7A FE 3E 28 0F 3B; -9A78: E3 EB ED 73 3D 5C C5 22 42 5C FD 72 0A C9 D5 E5 CD AC 05 06 FD CB 01 7E; -9A90: 28 05 3E CE C3 FE 19 FD CB 01 F6 EF 8D 2C 30 16 E7 FE 24 20 05 FD CB 01; -9AA8: B6 E7 FE 28 20 3C E7 FE 29 28 20 EF 8D 2C D2 12 19 EB E7 FE 24 20 02 EB; -9AC0: E7 EB 01 06 00 EF 55 16 23 23 36 0E FE 2C 20 03 E7 18 E0 FE 29 20 13 E7; -9AD8: FE 3D 20 0E E7 3A 3B 5C F5 EF FB 24 F1 FD AE 01 E6 40 C2 12 19 CD A1 18; -9AF0: C9 21 0E EC 36 FF CD 20 1F EF B0 16 2A 59 5C 01 03 00 EF 55 16 21 6E 1B; -9B08: ED 5B 59 5C 01 03 00 ED B0 CD 6B 02 CD 20 1F EF B0 16 2A 59 5C 01 01 00; -9B20: EF 55 16 2A 59 5C 36 E1 CD 6B 02 CD 53 1B ED 7B 3D 5C E1 21 03 13 E5 21; -9B38: 13 00 E5 21 08 00 E5 3E 20 32 5C 5B C3 00 5B 21 00 00 E5 3E 20 32 5C 5B; -9B50: C3 00 5B 2A 4F 5C 11 05 00 19 11 0A 00 EB 19 EB 01 04 00 ED B0 FD CB 30; -9B68: 9E FD CB 01 A6 C9 EF 22 22 3E 03 18 02 3E 02 FD 36 02 00 EF 30 25 28 03; -9B80: EF 01 16 EF 18 00 EF 70 20 38 18 EF 18 00 FE 3B 28 04 FE 2C 20 08 EF 20; -9B98: 00 CD 0E 19 18 08 EF E6 1C 18 03 EF DE 1C CD A1 18 EF 25 18 C9 ED 73 81; -9BB0: 5B 31 FF 5B CD 97 1C ED 4B 72 5B 21 F7 FF F6 FF ED 42 CD F3 1C 01 09 00; -9BC8: 21 71 5B CD AC 1D 2A 74 5B ED 4B 72 5B CD AC 1D CD 56 1D 3E 05 CD 64 1C; -9BE0: ED 7B 81 5B C9 EF 18 00 FE 21 C2 12 19 EF 20 00 CD A1 18 3E 02 EF 01 16; -9BF8: ED 73 81 5B 31 FF 5B CD D2 20 3E 05 CD 64 1C ED 7B 81 5B C9 EF 18 00 FE; -9C10: 21 C2 12 19 CD 93 13 CD A1 18 ED 73 81 5B 31 FF 5B CD 5F 1F 3E 05 CD 64; -9C28: 1C ED 7B 81 5B C9 ED 73 81 5B 31 FF 5B CD 35 1D 21 71 5B 01 09 00 CD 37; -9C40: 1E 3E 05 CD 64 1C ED 7B 81 5B C9 ED 73 81 5B 31 FF 5B 42 4B CD 37 1E CD; -9C58: 56 1D 3E 05 CD 64 1C ED 7B 81 5B C9 E5 C5 21 81 1C 06 00 4F 09 4E F3 3A; -9C70: 5C 5B E6 F8 B1 32 5C 5B 01 FD 7F ED 79 FB C1 E1 C9 01 03 04 06 07 00 11; -9C88: 67 5B DD E5 E1 06 0A 1A 13 BE 23 C0 10 F9 C9 CD 12 1D 28 04 CD AC 05 20; -9CA0: DD E5 01 EC 3F DD 09 DD E1 30 63 21 EC FF 3E FF CD F3 1C 21 66 5B CB D6; -9CB8: DD E5 D1 21 67 5B 01 0A 00 ED B0 DD CB 13 C6 DD 7E 0A DD 77 10 DD 7E 0B; -9CD0: DD 77 11 DD 7E 0C DD 77 12 AF DD 77 0D DD 77 0E DD 77 0F 3E 05 CD 64 1C; -9CE8: DD E5 E1 01 EC FF 09 22 83 5B C9 ED 5B 85 5B 08 3A 87 5B 4F 08 CB 7F 20; -9D00: 09 19 89 22 85 5B 32 87 5B C9 19 89 38 F5 CD AC 05 03 3E 04 CD 64 1C DD; -9D18: 21 EC EB ED 5B 83 5B B7 DD E5 E1 ED 52 C8 CD 87 1C 20 03 F6 FF C9 01 EC; -9D30: FF DD 09 18 E6 CD 12 1D 20 04 CD AC 05 23 DD 7E 0A DD 77 10 DD 7E 0B DD; -9D48: 77 11 DD 7E 0C DD 77 12 3E 05 CD 64 1C C9 3E 04 CD 64 1C DD CB 13 46 C8; -9D60: DD CB 13 86 21 66 5B CB 96 DD 6E 10 DD 66 11 DD 7E 12 DD 5E 0A DD 56 0B; -9D78: DD 46 0C B7 ED 52 98 CB 14 CB 14 CB 2F CB 1C CB 2F CB 1C DD 75 0D DD 74; -9D90: 0E DD 77 0F DD 6E 10 DD 66 11 DD 7E 12 01 EC FF DD 09 DD 75 0A DD 74 0B; -9DA8: DD 77 0C C9 78 B1 C8 E5 11 00 C0 EB ED 52 28 1D 38 1B E5 ED 42 30 0D 60; -9DC0: 69 C1 B7 ED 42 E3 11 00 C0 D5 18 28 E1 E1 11 00 00 D5 D5 18 1F 60 69 11; -9DD8: 20 00 B7 ED 52 38 05 E3 42 4B 18 05 E1 11 00 00 D5 C5 11 98 5B ED B0 C1; -9DF0: E5 21 98 5B 3E 04 CD 64 1C DD 5E 10 DD 56 11 DD 7E 12 CD 64 1C ED A0 7A; -9E08: B3 28 19 78 B1 C2 05 1E 3E 04 CD 64 1C DD 73 10 DD 72 11 3E 05 CD 64 1C; -9E20: E1 C1 18 88 3E 04 CD 64 1C DD 34 12 DD 7E 12 11 00 C0 CD 64 1C 18 D4 78; -9E38: B1 C8 E5 11 00 C0 EB ED 52 28 24 38 22 E5 ED 42 30 12 60 69 C1 B7 ED 42; -9E50: E3 11 00 00 D5 11 00 C0 D5 EB 18 24 E1 E1 11 00 00 D5 D5 D5 EB 18 19 60; -9E68: 69 11 20 00 B7 ED 52 38 05 E3 42 4B 18 05 E1 11 00 00 D5 C5 E5 11 98 5B; -9E80: 3E 04 CD 64 1C DD 6E 10 DD 66 11 DD 7E 12 CD 64 1C ED A0 7C B5 28 25 78; -9E98: B1 C2 91 1E 3E 04 CD 64 1C DD 75 10 DD 74 11 3E 05 CD 64 1C D1 C1 21 98; -9EB0: 5B 78 B1 28 02 ED B0 EB C1 C3 37 1E 3E 04 CD 64 1C DD 34 12 DD 7E 12 21; -9EC8: 00 C0 CD 64 1C 18 C8 F5 3A 5C 5B F5 E5 D5 C5 DD 21 6A 5B DD 73 10 DD 72; -9EE0: 11 DD 36 12 04 CD AC 1D 3E 05 CD 64 1C C1 D1 E1 09 EB 09 EB F1 01 FD 7F; -9EF8: F3 ED 79 32 5C 5B FB 01 00 00 F1 C9 F5 3A 5C 5B F5 E5 D5 C5 DD 21 6A 5B; -9F10: DD 75 10 DD 74 11 DD 36 12 04 EB CD 37 1E 18 C8 08 3E 00 F3 CD 3A 1F F1; -9F28: 22 58 5B 2A 81 5B ED 73 81 5B F9 FB 2A 58 5B F5 08 C9 C5 01 FD 7F ED 79; -9F40: 32 5C 5B C1 C9 08 F3 F1 22 58 5B 2A 81 5B ED 73 81 5B F9 2A 58 5B F5 3E; -9F58: 07 CD 3A 1F FB 08 C9 CD 12 1D 20 04 CD AC 05 23 DD 6E 0D DD 66 0E DD 7E; -9F70: 0F CD F3 1C FD E5 FD 2A 83 5B 01 EC FF DD 09 FD 6E 0A FD 66 0B FD 7E 0C; -9F88: FD E1 DD 5E 0A DD 56 0B DD 46 0C B7 ED 52 98 CB 14 CB 14 CB 2F CB 1C CB; -9FA0: 2F CB 1C 01 14 00 DD 09 DD 75 10 DD 74 11 DD 77 12 01 EC FF DD 09 DD 6E; -9FB8: 0A DD 66 0B DD 56 0C 01 14 00 DD 09 7A CD 64 1C 3A 5C 5B 5F 01 FD 7F 3E; -9FD0: 07 F3 ED 79 D9 DD 6E 0A DD 66 0B DD 56 0C 7A CD 64 1C 3A 5C 5B 5F 01 FD; -9FE8: 7F D9 3E 07 F3 ED 79 DD 7E 10 D6 01 DD 77 10 30 14 DD 7E 11 D6 01 DD 77; -A000: 11 30 0A DD 7E 12 D6 01 DD 77 12 38 31 ED 59 7E 2C 20 11 24 20 0E 08 14; -A018: 7A CD 64 1C 3A 5C 5B 5F 21 00 C0 08 D9 F3 ED 59 77 2C 20 0F 24 20 0C 14; -A030: 7A CD 64 1C 3A 5C 5B 5F 21 00 C0 D9 18 AC 3E 04 CD 64 1C 3E 00 21 14 00; -A048: CD F3 1C DD 5E 0D DD 56 0E DD 4E 0F 7A 07 CB 11 07 CB 11 7A E6 3F 57 DD; -A060: E5 D5 11 EC FF DD 19 D1 DD 6E 0A DD 66 0B DD 7E 0C B7 ED 52 91 CB 74 20; -A078: 03 CB F4 3D DD 75 0A DD 74 0B DD 77 0C DD 6E 10 DD 66 11 DD 7E 12 B7 ED; -A090: 52 91 CB 74 20 03 CB F4 3D DD 75 10 DD 74 11 DD 77 12 DD E5 E1 D5 ED 5B; -A0A8: 83 5B B7 ED 52 D1 20 B1 ED 5B 83 5B E1 E5 B7 ED 52 44 4D E1 E5 11 14 00; -A0C0: 19 EB E1 1B 2B ED B8 2A 83 5B 11 14 00 19 22 83 5B C9 3E 04 CD 64 1C 21; -A0D8: 21 21 01 2B 21 DD 21 EC EB CD D6 05 DD E5 E3 ED 5B 83 5B B7 ED 52 E1 28; -A0F0: 20 54 5D E5 C5 CD 8A 1C C1 E1 30 0E 50 59 E5 C5; -A100: CD 8A 1C C1 E1 38 03 DD E5 C1 11 EC FF DD 19 18 D0 E5 21 2B 21 B7 ED 42; -A118: E1 C8 60 69 CD 35 21 18 B9 00 00 00 00 00 00 00 00 00 00 FF FF FF FF FF; -A130: FF FF FF FF FF E5 C5 E1 11 67 5B 01 0A 00 ED B0 3E 05 CD 64 1C 2A 81 5B; -A148: ED 73 81 5B F9 21 67 5B 06 0A 7E E5 C5 EF 10 00 C1 E1 23 10 F5 3E 0D EF; -A160: 10 00 EF 4D 0D 2A 81 5B ED 73 81 5B F9 3E 04 CD 64 1C E1 C9 3E 03 18 02; -A178: 3E 02 EF 30 25 28 03 EF 01 16 EF 4D 0D EF DF 1F CD A1 18 C9 EF 30 25 28; -A190: 08 3E 01 EF 01 16 EF 6E 0D FD 36 02 01 EF C1 20 CD A1 18 EF A0 20 C9 C3; -A1A8: F0 08 F3 C3 9D 01 DF FE 2C 20 38 E7 EF 82 1C CD A1 18 EF 2D 23 C9 DF FE; -A1C0: 2C 28 07 CD A1 18 EF 77 24 C9 E7 EF 82 1C CD A1 18 EF 94 23 C9 EF B2 28; -A1D8: 20 11 EF 30 25 20 08 CB B1 EF 96 29 CD A1 18 EF 15 2C C9 CD AC 05 0B FD; -A1F0: CB 30 46 C8 EF AF 0D C9 21 FE FF 22 45 5C FD CB 01 BE CD 8E 22 EF FB 24; -A208: FD CB 01 76 28 2C DF FE 0D 20 27 FD CB 01 FE CD 8E 22 21 21 03 22 8B 5B; -A220: EF FB 24 FD CB 01 76 28 11 11 8D 5B 2A 65 5C 01 05 00 B7 ED 42 ED B0 C3; -A238: 3E 22 CD AC 05 19 3E 0D CD 6F 22 01 01 00 EF 30 00 22 5B 5C E5 2A 51 5C; -A250: E5 3E FF EF 01 16 EF E3 2D E1 EF 15 16 D1 2A 5B 5C A7 ED 52 1A CD 6F 22; -A268: 13 2B 7C B5 20 F6 C9 E5 D5 CD 45 1F 21 0D EC CB 9E F5 3E 02 EF 01 16 F1; -A280: CD 69 26 21 0D EC CB 9E CD 20 1F D1 E1 C9 2A 59 5C 2B 22 5D 5C E7 C9 CD; -A298: 8E 22 FE F1 C0 2A 5D 5C 7E 23 FE 0D C8 FE 3A 20 F7 B7 C9 47 21 BD 22 7E; -A2B0: 23 B7 28 05 B8 20 F8 78 C9 F6 FF 78 C9 2B 2D 2A 2F 5E 3D 3E 3C C7 C8 C9; -A2C8: C5 C6 00 FE A5 38 0E FE C4 30 0A FE AC 28 06 FE AD 28 02 BF C9 FE A5 C9; -A2E0: 47 F6 20 FE 61 38 06 FE 7B 30 02 BF C9 78 FE 2E C8 CD 0A 23 20 11 E7 CD; -A2F8: 0A 23 28 FA FE 2E C8 FE 45 C8 FE 65 C8 18 A4 F6 FF C9 FE 30 38 06 FE 3A; -A310: 30 02 BF C9 FE 30 C9 06 00 DF C5 EF 8C 1C C1 04 FE 2C 20 03 E7 18 F3 78; -A328: FE 09 38 04 CD AC 05 2B CD A1 18 C3 85 09 21 FF 5B 22 81 5B CD 45 1F C3; -A340: CB 25 A7 ED 52 44 4D 19 EB C9 01 01 00 E5 D5 CD 58 23 D1 E1 EF 55 16 C9; -A358: 2A 65 5C 09 38 0A EB 21 82 00 19 38 03 ED 72 D8 FD 36 00 03 C3 21 03 87; -A370: 87 6F 26 00 29 29 29 C9 21 00 00 39 ED 5B 65 5C B7 ED 52 C9 FD CB C7 86; -A388: CD 6F 23 E5 ED 5B 24 FF 19 54 5D E3 E5 D5 11 00 58 19 EB E1 01 20 00 3A; -A3A0: 8F 5C CD 9B 24 E1 7C 26 00 87 87 87 C6 40 57 5C 19 EB E1 06 20 C3 E1 23; -A3B8: 16 FF CD 6F 23 7A ED 5B 24 FF 19 5D 54 13 77 0B ED B0 C9 CD 88 24 11 00; -A3D0: 40 2A 24 FF 43 CD E1 23 16 48 CD E1 23 16 50 06 C0 7E E5 D5 FE FE 38 04; -A3E8: D6 FE 18 36 FE 20 30 07 21 27 25 A7 08 18 34 FE 80 30 0E CD 71 23 ED 5B; -A400: 36 5C 19 D1 CD 28 FF 18 47 FE 90 30 04 D6 7F 18 11 D6 90 CD 71 23 D1 CD; -A418: 20 1F D5 ED 5B 7B 5C 37 18 07 11 2F 25 CD 71 23 A7 08 19 D1 4A 7E 12 23; -A430: 14 7E 12 23 14 7E 12 23 14 7E 12 23 14 7E 12 23 14 7E 12 23 14 7E 12 23; -A448: 14 7E 12 51 08 DC 45 1F E1 23 13 10 8C C9 C5 F3 01 FD 7F 3A 5C 5B EE 10; -A460: ED 79 FB 08 08 F3 0E FD EE 10 ED 79 FB C1 C9 21 56 24 11 28 FF 01 0E 00; -A478: ED B0 E5 21 2C 24 0E 20 ED B0 E1 0E 0B ED B0 C9 FD CB C7 86 11 00 58 01; -A490: C0 02 2A 24 FF 3A 8D 5C 32 8F 5C 08 C5 7E FE FF 20 08 3A 8D 5C 12 23 13; -A4A8: 18 5D 08 12 13 08 23 FE 15 30 54 FE 10 38 50 2B 20 08 23 7E 4F 08 E6 F8; -A4C0: 18 43 FE 11 20 0B 23 7E 87 87 87 4F 08 E6 C7 18 34 FE 12 20 09 23 7E 0F; -A4D8: 4F 08 E6 7F 18 27 FE 13 20 0A 23 7E 0F 0F 4F 08 E6 BF 18 19 FE 14 23 20; -A4F0: 16 4E 3A 01 5C A9 1F 30 0E 3E 01 FD AE C7 32 01 5C 08 CD 13 25 B1 08 C1; -A508: 0B 78 B1 C2 9C 24 08 32 8F 5C C9 47 E6 C0 4F 78 87 87 87 E6 38 B1 4F 78; -A520: 1F 1F 1F E6 07 B1 C9 00 3C 62 60 6E 62 3E 00 00 6C 10 54 BA 38 54 82 15; -A538: 0B 94 2A 0A B5 2A 08 D7 2A 09 E3 2A AD 4F 2A AC 25 2A AF D4 29 AE E1 29; -A550: A6 83 29 A5 AB 29 A8 87 2A A7 7A 2A AA 1B 29 0C 2B 29 B3 17 30 B4 BC 2F; -A568: B0 72 30 B1 3E 30 0D 44 29 A9 9B 26 07 04 27 04 0B 2E 27 0A 31 27 07 17; -A580: 27 0D 17 27 CD BE 28 21 00 00 22 9A FC 3E 82 32 0D EC 21 00 00 22 49 5C; -A598: CD BC 35 CD 5E 36 C9 21 FF 5B 22 81 5B CD 45 1F 3E 02 EF 01 16 21 44 27; -A5B0: 22 EA F6 21 54 27 22 EC F6 E5 21 0D EC CB CE CB A6 2B 36 00 E1 CD A8 36; -A5C8: C3 53 26 DD 21 6C FD 21 FF 5B 22 81 5B CD 45 1F 3E 02 EF 01 16 CD 68 36; -A5E0: 21 3B 5C CB 6E 28 FC 21 0D EC CB 9E CB 76 20 14 3A 0E EC FE 04 28 0A FE; -A5F8: 00 C2 C7 28 CD 48 38 18 03 CD 4D 38 CD D6 30 CD 22 32 3A 0E EC FE 04 28; -A610: 42 2A 49 5C 7C B5 20 15 2A 53 5C ED 4B 4B 5C A7 ED 42 20 06 21 00 00 22; -A628: 08 EC 2A 08 EC CD 20 1F EF 6E 19 EF 95 16 CD 45 1F ED 53 49 5C 21 0D EC; -A640: CB 6E 20 0F 21 00 00 22 06 EC CD 2F 15 CD F2 29 CD 44 29 31 FF 5B CD 68; -A658: 36 CD 7F 36 F5 3A 39 5C CD EC 26 F1 CD 69 26 18 EA 21 0D EC CB 4E F5 21; -A670: 77 25 20 03 21 37 25 CD CE 3F 20 05 D4 E7 26 F1 C9 F1 28 05 AF 32 41 5C; -A688: C9 21 0D EC CB 46 28 04 CD E7 26 C9 FE A3 30 BB C3 F1 28 3A 0E EC FE 04; -A6A0: C8 CD 30 16 21 0D EC CB 9E 7E EE 40 77 E6 40 28 05 CD BB 26 18 03 CD CE; -A6B8: 26 37 C9 CD 81 38 21 0D EC CB F6 CD 2D 2E CD 88 3A CD DF 28 18 0B 21 0D; -A6D0: EC CB B6 CD BE 28 CD 48 38 2A 9A FC 7C B5 C4 4A 33 CD 2F 15 C3 F2 29 3A; -A6E8: 38 5C CB 3F DD E5 16 00 5F 21 80 0C EF B5 03 DD E1 C9 DD E5 11 30 00 21; -A700: 00 03 18 F0 CD EC 29 21 0D EC CB CE 2B 36 00 2A EC F6 CD A8 36 37 C9 21; -A718: 0D EC CB 8E 2B 7E 2A EA F6 E5 F5 CD 3E 37 F1 E1 CD CE 3F C3 F2 29 37 18; -A730: 01 A7 21 0C EC 7E E5 2A EC F6 DC A7 37 D4 B6 37 E1 77 37 C9 05 00 31 28; -A748: 01 6C 28 02 85 28 03 47 1B 04 16 28 06 31 32 38 20 20 20 20 20 FF 54 61; -A760: 70 65 20 4C 6F 61 64 65 F2 31 32 38 20 42 41 53 49 C3 43 61 6C 63 75 6C; -A778: 61 74 6F F2 34 38 20 42 41 53 49 C3 54 52 2D 44 4F D3 20 20 20 20 20 A0; -A790: 05 00 42 27 01 51 28 02 11 28 03 62 28 04 1C 28 06 4F 70 74 69 6F 6E 73; -A7A8: 20 FF 31 32 38 20 42 41 53 49 C3 52 65 6E 75 6D 62 65 F2 53 63 72 65 65; -A7C0: EE 50 72 69 6E F4 45 78 69 F4 A0 02 00 42 27 01 1C 28 03 4F 70 74 69 6F; -A7D8: 6E 73 20 FF 43 61 6C 63 75 6C 61 74 6F F2 45 78 69 F4 A0 16 01 00 10 00; -A7F0: 11 07 13 00 54 6F 20 63 61 6E 63 65 6C 20 2D 20; -A800: 70 72 65 73 73 20 42 52 45 41 4B 20 74 77 69 63 E5 CD 9B 26 18 5E CD 81; -A818: 38 C3 EC 3B 21 0D EC CB B6 CD BE 28 06 00 16 17 CD 5E 3B CD 20 1F C3 9F; -A830: 25 CD 52 38 21 3C 5C CB C6 11 EB 27 CD 7D 05 CB 86 CB F6 3E 07 32 0E EC; -A848: 01 00 00 CD 2B 37 C3 F1 1A CD 88 38 D4 E7 26 21 00 00 22 49 5C 22 08 EC; -A860: 18 03 CD 14 1B 21 0D EC CB 76 20 08 21 3C 5C CB 86 CD 48 38 21 0D EC CB; -A878: AE CB A6 3E 00 21 90 27 11 A0 27 18 2C 21 0D EC CB EE CB E6 CB B6 CD BE; -A890: 28 CD 4D 38 3E 04 32 0E EC 21 00 00 22 49 5C CD 2F 15 01 00 00 78 CD F8; -A8A8: 29 3E 04 21 CB 27 11 D2 27 32 0E EC 22 EA F6 ED 53 EC F6 C3 04 26 CD 1F; -A8C0: 2E CD 7F 3A C3 E8 28 06 00 16 17 CD 5E 3B C3 AD 25 06 00 00 00 04 10 14; -A8D8: 06 00 00 00 00 01 01 21 D8 28 11 EE F6 C3 BA 3F 21 D1 28 11 EE F6 C3 BA; -A8F0: 3F 21 0D EC B7 B7 CB 46 C2 F2 29 CB BE CB DE E5 F5 CD EC 29 F1 F5 CD 81; -A908: 2E F1 78 CD 78 2B E1 CB FE D2 F2 29 78 DA F8 29 C3 F2 29 21 0D EC CB DE; -A920: CD EC 29 CD 12 2F 37 78 C3 F8 29 21 0D EC CB 86 CB DE CD EC 29 CD 5B 2B; -A938: 3F DA F2 29 CD 12 2F 37 78 C3 F8 29 CD EC 29 F5 CD B4 30 C5 06 00 CD 41; -A950: 2E C1 38 0A 21 20 00 19 7E 2F E6 09 28 1C 3A 0D EC CB 5F 28 05 CD 8E 2C; -A968: 30 15 CD 4C 2C CD 78 2B CD CE 2E 06 00 F1 37 C3 F8 29 F1 37 C3 F2 29 F1; -A980: C3 F2 29 3A 0E EC FE 04 C8 CD EC 29 21 00 00 CD 20 1F EF 6E 19 EF 95 16; -A998: CD 45 1F ED 53 49 5C 3E 0F CD 96 3A CD 2F 15 37 C3 F2 29 3A 0E EC FE 04; -A9B0: C8 CD EC 29 21 0F 27 CD 20 1F EF 6E 19 EB EF 95 16 CD 45 1F ED 53 49 5C; -A9C8: 3E 0F CD 96 3A CD 2F 15 37 C3 F2 29 CD EC 29 CD EA 2B D2 F2 29 78 C3 F8; -A9E0: 29 CD EC 29 CD 09 2C 30 09 78 18 0C CD 07 2A C3 4F 36 CD 07 2A C3 40 36; -A9F8: CD 11 2A F5 C5 3E 0F CD 96 3A C1 F1 C3 40 36 21 EE F6 4E 23 46 23 7E 23; -AA10: C9 21 EE F6 71 23 70 23 77 C9 E5 CD B4 30 26 00 68 19 7E E1 C9 CD EC 29; -AA28: 5F 16 0A D5 CD 30 2B D1 30 C0 7B CD 11 2A 43 CD F9 2A 30 06 15 20 EC 7B; -AA40: 38 B6 D5 CD 0B 2B D1 43 CD F9 2A 7B B7 18 A9 CD EC 29 5F 16 0A D5 CD 0B; -AA58: 2B D1 30 96 7B CD 11 2A 43 CD 02 2B 30 07 15 20 EC 7B DA F8 29 F5 CD 30; -AA70: 2B 06 00 CD D4 2B F1 C3 F8 29 CD EC 29 CD 4C 2C D2 F2 29 78 C3 F8 29 CD; -AA88: EC 29 CD 31 2C D2 F2 29 78 C3 F8 29 CD EC 29 5F D5 CD 0B 2B D1 D2 F2 29; -AAA0: 43 CD 02 2B 7B DA F8 29 F5 CD 30 2B 06 00 CD F9 2A F1 C3 F8 29 CD EC 29; -AAB8: 5F D5 CD 30 2B D1 D2 F2 29 43 CD 02 2B 7B DA F8 29 D5 CD 0B 2B D1 43 CD; -AAD0: F9 2A 7B B7 C3 F8 29 CD EC 29 CD 5B 2B DA F8 29 C3 F2 29 CD EC 29 CD 78; -AAE8: 2B DA F8 29 F5 CD 0B 2B 06 1F CD DF 2B F1 C3 F8 29 D5 CD D4 2B D4 DF 2B; -AB00: D1 C9 D5 CD DF 2B D4 D4 2B D1 C9 CD 7C 2C 30 1F C5 CD B4 30 06 00 CD 41; -AB18: 2E D4 80 2F C1 21 F1 F6 7E B9 38 09 C5 CD 6F 16 C1 D8 79 B7 C8 0D 37 C9; -AB30: C5 CD B4 30 06 00 CD 41 2E C1 38 03 C3 80 2F CD 68 2C 30 16 21 F1 F6 23; -AB48: 79 BE 38 0C C5 E5 CD 39 16 E1 C1 D8 23 7E B9 C8 0C 37 C9 57 05 FA 66 2B; -AB60: 58 CD DF 2B 7B D8 D5 CD 0B 2B D1 7B D0 06 1F CD DF 2B 78 D8 7A 06 00 C9; -AB78: 57 04 3E 1F B8 38 06 58 CD D4 2B 7B D8 05 C5 E5 21 0D EC CB 7E 20 31 CD; -AB90: B4 30 21 20 00 19 7E CB 4F 20 25 CB CE CB 9E 21 23 00 19 EB E1 C1 F5 CD; -ABA8: 30 2B F1 CD B4 30 21 23 00 19 EB CB 87 CB DF CD D3 2E CD F4 35 78 37 C9; -ABC0: E1 C1 D5 CD 30 2B D1 78 D0 06 00 CD D4 2B 78 D8 7B 06 00 C9 D5 E5 CD B4; -ABD8: 30 CD 41 2E C3 65 2C D5 E5 CD B4 30 CD 63 2E C3 65 2C D5 E5 CD 5B 2B 30; -ABF0: 16 CD 1A 2A FE 20 28 F4 CD 5B 2B 30 0A CD 1A 2A FE 20 20 F4 CD 78 2B 18; -AC08: 5C D5 E5 CD 78 2B 30 1B CD 1A 2A FE 20 20 F4 CD 78 2B 30 0F CD 41 2E 30; -AC20: 0A CD 1A 2A FE 20 28 EF 37 18 3A D4 5B 2B B7 18 34 D5 E5 CD B4 30 21 20; -AC38: 00 19 CB 46 20 07 CD 0B 2B 38 F0 18 20 06 00 CD D4 2B 18 19 D5 E5 CD B4; -AC50: 30 21 20 00 19 CB 5E 20 07 CD 30 2B 38 F0 18 05 06 1F CD DF 2B E1 D1 C9; -AC68: 3A 0D EC CB 5F 37 C8 CD B4 30 21 20 00 19 CB 5E 37 C8 18 12 3A 0D EC CB; -AC80: 5F 37 C8 CD B4 30 21 20 00 19 CB 46 37 C8 3E 02 CD B4 30 21 20 00 19 CB; -AC98: 46 20 08 0D F2 90 2C 0E 00 3E 01 21 00 EC 11 03 EC F6 80 77 12 23 13 3E; -ACB0: 00 77 12 23 13 79 77 12 21 00 00 22 06 EC CD 5F 33 CD 67 3C DD E5 CD 20; -ACC8: 1F CD 6B 02 CD 45 1F DD E1 3A 3A 5C 3C 20 18 21 0D EC CB 9E CD 5E 36 3A; -ACE0: 0E EC FE 04 C4 2F 15 CD FA 26 CD 07 2A 37 C9 21 00 EC 11 03 EC 1A CB BF; -ACF8: 77 23 13 1A 77 23 13 1A 77 CD 63 3C 38 04 ED 4B 06 EC 2A 06 EC B7 ED 42; -AD10: F5 E5 CD 07 2A E1 F1 38 11 28 2A E5 78 CD 5B 2B E1 30 22 2B 7C B5 20 F3; -AD28: 18 1B E5 21 0D EC CB BE E1 EB 21 00 00 B7 ED 52 E5 78 CD 78 2B E1 30 05; -AD40: 2B 7C B5 20 F3 21 0D EC CB FE CD 11 2A 3E 17 CD 96 3A B7 C9 21 00 EC CB; -AD58: 7E 28 07 2A 06 EC 23 22 06 EC 21 00 EC 7E 23 46 23 4E E5 E6 0F 21 85 2D; -AD70: CD CE 3F 5D E1 28 02 3E 0D 71 2B 70 2B F5 7E E6 F0 B3 77 F1 C9 03 02 AC; -AD88: 2D 04 E9 2D 01 8F 2D CD B7 32 CD 0E 2E 30 07 FE 00 28 F7 2E 01 C9 0C 06; -ADA0: 00 2A DB F9 79 BE 38 E7 06 00 0E 00 E5 21 EE F6 7E B9 20 0A 23 7E B8 20; -ADB8: 05 21 00 EC CB BE E1 CD B4 30 CD 0E 2E 30 07 FE 00 28 E1 2E 02 C9 21 20; -ADD0: 00 19 CB 5E 28 05 2E 08 3E 0D C9 21 F3 F6 0C 7E B9 06 00 30 DA 06 00 0E; -ADE8: 01 CD C3 31 CD 0E 2E 30 07 FE 00 28 F7 2E 04 C9 21 20 00 19 CB 5E 20 09; -AE00: 0C 06 00 3A F5 F6 B9 30 E0 2E 08 3E 0D C9 3E 1F B8 3F D0 68 26 00 19 7E; -AE18: 04 37 C9 01 14 01 01 21 3C 5C CB 86 21 1B 2E 11 15 EC C3 BA 3F 21 3C 5C; -AE30: CB C6 01 00 00 CD 2B 37 21 1D 2E 11 15 EC C3 BA 3F 26 00 68 19 7E FE 00; -AE48: 37 C0 78 B7 28 0D E5 2B 7E FE 00 37 E1 C0 7E FE 00 37 C0 23 04 78 FE 1F; -AE60: 38 F4 C9 26 00 68 19 7E FE 00 37 C0 7E FE 00 20 07 78 B7 C8 2B 05 18 F4; -AE78: 04 37 C9 26 00 68 19 7E C9 21 0D EC B7 CB 46 C0 C5 F5 CD B4 30 F1 CD AC; -AE90: 16 F5 EB CD 04 36 EB F1 3F 28 31 F5 06 00 0C 3A 15 EC B9 38 23 7E 5F E6; -AEA8: D7 BE 77 7B CB CE F5 CD B4 30 F1 28 0D CB 87 CD D3 2E 30 10 CD F4 35 F1; -AEC0: 18 CC CD 41 2E F1 18 C6 F1 CD 6E 31 C1 C9 CD B4 30 3E 09 C5 D5 41 21 EF; -AED8: 2E 4F C5 CD 75 16 C1 79 30 0A 48 CD B4 30 21 20 00 19 77 37 D1 C1 C9 00; -AEF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00; -AF00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 09 00 00 C5 CD B4 30 C5 21; -AF18: 20 00 19 CB 4E 3E 00 28 10 0C 21 23 00 19 EB 3A 15 EC B9 30 EA 0D CD C9; -AF30: 31 E1 E5 CD B4 30 E1 47 79 BD 78 F5 20 03 44 18 09 F5 E5 06 00 CD 41 2E; -AF48: E1 F1 E5 21 F4 F6 CB C6 28 02 CB 86 CD C1 16 F5 C5 D5 21 F4 F6 CB 46 20; -AF60: 0E 06 00 CD D4 2B 38 07 CD 80 2F D1 C1 18 05 E1 C1 CD 04 36 F1 0D 47 E1; -AF78: F1 78 C2 32 2F 37 C1 C9 21 20 00 19 7E CB 46 20 29 F5 C5 79 B7 20 15 C5; -AF90: 2A 9A FC CD 4A 33 22 9A FC 3A DB F9 4F 0D CD B7 32 C1 18 04 0D CD B4 30; -AFA8: C1 F1 21 20 00 19 CB 8E B6 77 41 CD B4 30 CD DF 30 C3 48 16 CD 84 30 E5; -AFC0: CD 95 30 28 32 CD 5B 2B E1 30 2D CD 1A 2A F5 E5 CD 12 2F E1 F1 FE 20 28; -AFD8: E6 E5 CD 95 30 28 18 CD 5B 2B E1 30 13 CD 1A 2A FE 20 28 07 E5 CD 12 2F; -AFF0: E1 18 E6 E5 CD 78 2B E1 78 F5 E5 21 F5 EE CB 96 3A 15 EC C5 06 00 4F BF; -B008: CD 05 16 C1 21 0D EC CB DE E1 CD F8 29 F1 C9 CD 84 30 E5 CD 1A 2A E1 FE; -B020: 00 37 28 D4 F5 E5 CD 12 2F E1 F1 FE 20 20 EB CD 1A 2A FE 20 37 20 C1 E5; -B038: CD 12 2F E1 18 F1 CD 84 30 E5 CD B4 30 21 20 00 19 CB 46 20 0C CD 5B 2B; -B050: 30 1B CD 12 2F E1 18 E9 E5 78 FE 00 28 0F 05 CD 1A 2A 04 FE 00 28 06 05; -B068: CD 12 2F 18 EC E1 37 C3 F8 2F CD 84 30 CD 1A 2A FE 00 37 28 F1 E5 CD 12; -B080: 2F E1 18 F1 21 0D EC CB 86 CD EC 29 21 F5 EE CB D6 21 F1 F6 C9 CD B4 30; -B098: 21 20 00 19 CB 46 28 0E 78 FE 00 28 0D 05 CD 1A 2A 04 FE 00 28 04 3E 01; -B0B0: B7 C9 AF C9 21 16 EC F5 79 11 23 00 B7 28 04 19 3D 18 F9 EB F1 C9 D5 CD; -B0C8: B4 30 26 00 68 19 D1 C9 05 00 00 00 F8 F6 21 D0 30 11 F5 F6 C3 BA 3F C5; -B0E0: D5 21 F5 F6 E5 7E B7 20 18 E5 CD 5F 33 2A D7 F9 CD 52 33 30 03 22 D7 F9; -B0F8: 44 4D E1 CD D6 32 3D 18 15 21 0D EC CB 86 21 F8 F6 54 5D 01 23 00 09 01; -B110: BC 02 ED B0 3D 37 D1 12 21 F8 F6 D1 C1 C9 C5 D5 21 20 00 19 7E 2F E6 11; -B128: 20 15 E5 D5 23 56 23 5E D5 CD 5F 33 E1 CD 4A 33 30 03 22 D7 F9 D1 E1 CB; -B140: 46 21 F5 F6 E5 28 05 3E 00 37 18 CA 7E FE 14 28 C5 01 23 00 21 F8 F6 EB; -B158: ED B0 21 D6 F9 54 5D 01 23 00 B7 ED 42 01 BC 02 ED B8 3C 37 18 A8 C5 D5; -B170: F5 06 00 0E 01 E5 CD C3 31 E1 CB 5E CB 9E 20 20 CD 41 2E F1 CD AC 16 28; -B188: 31 F5 06 00 0C 79 FE 15 38 0E 2B 7E 23 FE 00 28 07 E5 21 0D EC CB C6 E1; -B1A0: CB 4E CB CE CB 9E CD C3 31 20 D5 C5 D5 CD E6 35 36 08 D1 C1 CD F4 35 F1; -B1B8: 18 CA 79 32 F5 F6 CB DE D1 C1 C9 21 F8 F6 C3 B7 30 C5 D5 21 0D EC CB 86; -B1D0: 3A F5 F6 4F B7 3E 00 28 42 CD C3 31 F5 06 00 CD 41 2E 30 0E F1 CD C1 16; -B1E8: F5 C5 06 00 CD 41 2E C1 38 24 23 7E F5 C5 79 FE 01 20 09 3A 15 EC 4F CD; -B200: B4 30 18 04 0D CD C3 31 C1 F1 21 20 00 19 CB 8E B6 77 21 F5 F6 35 F1 0D; -B218: 20 BF 37 D1 C1 C9 03 00 DE F9 21 1E 32 11 DB F9 C3 BA 3F C5 D5 21 DB F9; -B230: E5 7E B7 20 1E E5 CD 5F 33 2A 9A FC CD 4A 33 30 03 22 9A FC 44 4D E1 23; -B248: 23 23 30 11 CD D6 32 3D EB 18 0A 2A DC F9 01 23 00 ED 42 37 3D EB E1 30; -B260: 01 77 23 73 23 72 EB D1 C1 C9 C5 D5 21 20 00 19 7E 2F E6 11 20 0C D5 E5; -B278: 23 56 23 5E ED 53 9A FC E1 D1 CB 5E 21 DB F9 E5 28 16 E5 CD 5F 33 2A 9A; -B290: FC CD 52 33 22 9A FC E1 23 23 23 3E 00 37 18 BD 7E FE 14 28 0E 3C 2A DC; -B2A8: F9 01 23 00 EB ED B0 EB 37 18 AA E1 D1 C1 C9 21 DE F9 C3 B7 30 08 0D CC; -B2C0: 35 01 DA 35 12 5A 33 13 5A 33 14 5A 33 15 5A 33 10 5A 33 11 5A 33 54 5D; -B2D8: 13 13 13 D5 21 20 00 19 36 01 23 70 23 71 0E 01 06 00 C5 D5 3A 0E EC FE; -B2F0: 04 C4 17 35 D1 C1 38 0F 79 FE 01 3E 0D 20 08 78 B7 3E 01 28 02 3E 0D 21; -B308: BD 32 CD CE 3F 38 1D 28 D9 F5 3E 1F B8 30 0F 3E 12 CD 31 33 38 05 F1 3E; -B320: 0D 18 E4 CD F4 35 F1 CD C5 35 18 BE E1 79 C8 37 C9 F5 CD E6 35 F1 AE 77; -B338: 79 FE 14 D0 0C 21 23 00 19 EB 21 20 00 19 36 00 37 C9 CD B6 34 D8 21 00; -B350: 00 C9 CD 30 34 D8 21 00 00 C9 CD 17 35 3F D0 21 00 00 22 9F FC 22 A1 FC; -B368: 21 74 33 11 AE FC 01 BC 00 ED B0 C9 F3 01 FD 7F 16 17 ED 51 FE 50 30 31; -B380: FE 40 30 26 FE 30 30 1B FE 20 30 10 FE 10 30 05 21 96 00 18 21 D6 10 21; -B398: CF 00 18 1A D6 20 21 00 01 18 13 D6 30 21 3E 01 18 0C D6 40 21 8B 01 18; -B3B0: 05 D6 50 21 D4 01 47 B7 28 09 7E 23 E6 80 28 FA 05 18 F5 11 A3 FC ED 53; -B3C8: A1 FC 3A 9E FC B7 3E 00 32 9E FC 20 04 3E 20 12 13 7E 47 23 12 13 E6 80; -B3E0: 28 F7 78 E6 7F 1B 12 13 3E A0 12 3E 07 01 FD 7F ED 79 FB C9 F3 01 FD 7F; -B3F8: 16 17 ED 51 21 96 00 06 A5 11 74 FD 1A E6 7F FE 61 1A 38 02 E6 DF BE 20; -B410: 09 23 13 E6 80 28 ED 37 18 0C 04 28 08 7E E6 80 23 28 FA 18 DC B7 78 16; -B428: 07 01 FD 7F ED 51 FB C9 CD EA 34 B7 32 9E FC CD 20 1F CD F6 34 30 52 20; -B440: 0C 78 B1 28 08 CD CF 34 CD D9 34 30 44 56 23 5E CD 45 1F D5 E5 DD E5 DD; -B458: 21 A3 FC DD 22 A1 FC EB 06 00 11 18 FC CD 95 34 11 9C FF CD 95 34 11 F6; -B470: FF CD 95 34 11 FF FF CD 95 34 DD 2B DD 7E 00 F6 80 DD 77 00 DD E1 E1 D1; -B488: 23 23 23 22 9F FC EB 37 C9 CD 45 1F C9 AF 19 3C 38 FC ED 52 3D C6 30 DD; -B4A0: 77 00 FE 30 20 0B 78 B7 20 09 3E 00 DD 77 00 18 02 06 01 DD 23 C9 CD EA; -B4B8: 34 B7 32 9E FC CD 20 1F CD F6 34 30 CC EB 7D B4 37 C2 4D 34 3F 18 C2 E5; -B4D0: 23 23 5E 23 56 23 19 D1 C9 7E E6 C0 37 C8 3F C9 78 BE C0 79 23 BE 2B C0; -B4E8: 37 C9 E5 21 00 00 22 A1 FC 22 9F FC E1 C9 E5 C1 11 00 00 2A 53 5C CD D9; -B500: 34 D0 CD E0 34 D8 78 B1 37 C8 CD CF 34 CD D9 34 D0 CD E0 34 30 F4 C9 2A; -B518: A1 FC 7D B4 28 1E 7E 23 FE A0 47 3E 00 20 02 3E FF 32 9E FC 78 CB 7F 28; -B530: 03 21 00 00 22 A1 FC E6 7F C3 8F 35 2A 9F FC 7D B4 CA 91 35 CD 20 1F 7E; -B548: FE 0E 20 08 23 23 23 23 23 23 18 F3 CD 45 1F 23 22 9F FC FE A5 38 08 D6; -B560: A5 CD AE FC C3 17 35 FE A3 38 10 20 05 21 94 35 18 03 21 9C 35 CD FD FC; -B578: C3 17 35 F5 3E 00 32 9E FC F1 FE 0D 20 09 21 00 00 22 A1 FC 22 9F FC 37; -B590: C9 37 3F C9 53 50 45 43 54 52 55 CD 50 4C 41 D9 47 4F 54 CF 47 4F 53 55; -B5A8: C2 44 45 46 46 CE 4F 50 45 4E A3 43 4C 4F 53 45 A3 02 01 05 21 B9 35 11; -B5C0: 6A FD C3 BA 3F 68 26 00 19 77 04 C9 CD E6 35 7E F6 18 77 21 6A FD CB C6; -B5D8: 37 C9 CD E6 35 CB DE 21 6A FD CB C6 37 C9 68 26 00 19 3E 20 B8 C8 36 00; -B5F0: 23 04 18 F8 3A 6B FD 06 00 26 00 68 19 36 00 04; -B600: 3D 20 F6 C9 C5 D5 E5 E5 21 F5 EE CB 56 E1 20 04 41 CD 1E 3B E1 D1 C1 C9; -B618: C5 D5 E5 E5 21 F5 EE CB 56 E1 20 04 59 CD BF 3A E1 D1 C1 C9 C5 D5 E5 E5; -B630: 21 F5 EE CB 56 E1 20 04 59 CD C6 3A E1 D1 C1 C9 F5 C5 D5 E5 78 41 4F CD; -B648: 9D 3A E1 D1 C1 F1 C9 F5 C5 D5 E5 78 41 4F CD B2 3A E1 D1 C1 F1 C9 3E 00; -B660: 32 41 5C 3E 02 32 0A 5C 21 3B 5C 7E F6 0C 77 21 0D EC CB 66 21 66 5B 20; -B678: 03 CB 86 C9 CB C6 C9 E5 21 3B 5C CB 6E 28 FC CB AE 3A 08 5C 21 41 5C CB; -B690: 86 FE 20 30 0D FE 10 30 E7 FE 06 38 E3 CD A4 36 30 DE E1 C9 EF DB 10 C9; -B6A8: E5 CD 3B 37 21 3C 5C CB 86 E1 5E 23 E5 21 EC 37 CD 33 37 E1 CD 33 37 E5; -B6C0: CD 22 38 21 FA 37 CD 33 37 E1 D5 01 07 08 CD 2B 37 C5 06 0C 3E 20 D7 7E; -B6D8: 23 FE 80 30 03 D7 10 F7 E6 7F D7 3E 20 D7 10 FB C1 04 CD 2B 37 1D 20 E1; -B6F0: 21 38 6F D1 CB 23 CB 23 CB 23 53 15 1E 6F 01 00 FF 7A CD 19 37 01 01 00; -B708: 7B CD 19 37 01 00 01 7A 3C CD 19 37 AF CD CA 37 C9 F5 E5 D5 C5 44 4D EF; -B720: E9 22 C1 D1 E1 F1 09 3D 20 EF C9 3E 16 D7 78 D7 79 D7 C9 7E 23 FE FF C8; -B738: D7 18 F8 37 18 01 A7 11 F6 EE 21 3C 5C 38 01 EB ED A0 38 01 EB 21 7D 5C; -B750: 38 01 EB 01 14 00 ED B0 38 01 EB 08 01 07 07 CD 94 3B DD 7E 01 80 47 3E; -B768: 0C C5 F5 D5 EF 9B 0E 01 07 00 09 D1 CD 7E 37 F1 C1 05 3D 20 EC C9 01 0E; -B780: 08 C5 06 00 E5 08 38 01 EB ED B0 38 01 EB 08 E1 24 C1 10 ED C5 D5 EF 88; -B798: 0E EB D1 C1 08 38 01 EB ED B0 38 01 EB 08 C9 CD CA 37 3D F2 B1 37 7E 3D; -B7B0: 3D CD CA 37 37 C9 D5 CD CA 37 3C 57 7E 3D 3D BA 7A F2 C5 37 AF CD CA 37; -B7C8: D1 C9 F5 E5 D5 21 07 59 11 20 00 A7 28 04 19 3D 20 FC 3E 78 BE 20 02 3E; -B7E0: 68 16 0E 77 23 15 20 FB D1 E1 F1 C9 16 07 07 15 00 14 00 10 07 11 00 13; -B7F8: 01 FF 11 00 20 11 07 10 00 FF 01 03 07 0F 1F 3F 7F FF FE FC F8 F0 E0 C0; -B810: 80 00 10 02 20 11 06 21 10 04 20 11 05 21 10 00 20 FF C5 D5 E5 21 02 38; -B828: 11 98 5B 01 10 00 ED B0 2A 36 5C E5 21 98 5A 22 36 5C 21 12 38 CD 33 37; -B840: E1 22 36 5C E1 D1 C1 C9 21 69 27 18 0D 21 72 27 18 08 21 5E 27 18 03 21; -B858: 84 27 E5 CD 81 38 21 A0 5A 06 20 3E 40 77 23 10 FC 21 EC 37 CD 33 37 01; -B870: 00 15 CD 2B 37 D1 CD 7D 05 0E 1A CD 2B 37 C3 22 38 06 15 16 17 C3 5E 3B; -B888: CD 20 1F CD 05 3A 7A B3 CA C0 39 2A 96 5B EF A9 30 EB 2A 94 5B 19 11 10; -B8A0: 27 B7 ED 52 D2 C0 39 2A 53 5C EF B8 19 23 23 22 92 5B 23 23 ED 53 6B 5B; -B8B8: 7E EF B6 18 FE 0D 28 05 CD 0E 39 18 F3 ED 5B 6B 5B 2A 4B 5C A7 ED 52 EB; -B8D0: 20 D8 CD 05 3A 42 4B 11 00 00 2A 53 5C C5 D5 E5 2A 96 5B EF A9 30 ED 5B; -B8E8: 94 5B 19 EB E1 72 23 73 23 4E 23 46 23 09 D1 13 C1 0B 78 B1 20 DF CD 45; -B900: 1F ED 43 92 5B 37 C9 CA F0 E1 EC ED E5 F7 23 22 79 5B EB 01 07 00 21 07; -B918: 39 ED B1 EB C0 0E 00 7E FE 20 28 1B EF 1B 2D 30 16 FE 2E 28 12 FE 0E 28; -B930: 12 F6 20 FE 65 20 04 78 B1 20 04 2A 79 5B C9 03 23 18 DC ED 43 71 5B E5; -B948: EF B6 18 CD 36 3A 7E E1 FE 3A 28 03 FE 0D C0 23 EF B4 33 EF A2 2D 60 69; -B960: EF 6E 19 28 0A 7E FE 80 20 05 21 0F 27 18 11 22 77 5B CD 0B 3A 2A 96 5B; -B978: EF A9 30 ED 5B 94 5B 19 11 73 5B E5 CD 3C 3A 58 1C 16 00 D5 E5 6B 26 00; -B990: ED 4B 71 5B B7 ED 42 22 71 5B 28 33 38 27 44 4D 2A 79 5B E5 D5 2A 65 5C; -B9A8: 09 38 13 EB 21 82 00 19 38 0C ED 72 3F 38 07 D1 E1 EF 55 16 18 11 D1 E1; -B9C0: CD 45 1F A7 C9 0B 1D 20 FC 2A 79 5B EF E8 19 ED 5B 79 5B E1 C1 ED B0 EB; -B9D8: 36 0E C1 23 E5 EF 2B 2D D1 01 05 00 ED B0 EB E5 2A 92 5B E5 5E 23 56 2A; -B9F0: 71 5B 19 EB E1 73 23 72 2A 6B 5B ED 5B 71 5B 19 22 6B 5B E1 C9 2A 4B 5C; -BA08: 22 77 5B 2A 53 5C ED 5B 77 5B B7 ED 52 28 1A 2A 53 5C 01 00 00 C5 EF B8; -BA20: 19 2A 77 5B A7 ED 52 28 05 EB C1 03 18 EF D1 13 C9 11 00 00 C9 23 7E FE; -BA38: 20 28 FA C9 D5 01 18 FC CD 60 3A 01 9C FF CD 60 3A 0E F6 CD 60 3A 7D C6; -BA50: 30 12 13 06 03 E1 7E FE 30 C0 36 20 23 10 F7 C9 AF 09 3C 38 FC ED 42 3D; -BA68: C6 30 12 13 C9 08 00 00 14 00 00 00 0F 00 08 00 16 01 00 00 00 0F 00 DD; -BA80: 21 6C FD 21 6D 3A 18 03 21 76 3A 11 6C FD C3 BA 3F D7 7A D7 37 C9 E6 3F; -BA98: DD 77 06 37 C9 DD 7E 01 80 47 CD A0 3B 7E DD 77 07 2F E6 C0 DD B6 06 77; -BAB0: 37 C9 DD 7E 01 80 47 CD A0 3B DD 7E 07 77 C9 E5 26 00 7B 90 18 07 E5 7B; -BAC8: 58 47 93 26 FF 4F 78 BB 28 4B D5 CD 98 3B C5 4C EF 9B 0E EB AF B1 28 03; -BAE0: 04 18 01 05 D5 EF 9B 0E D1 79 0E 20 06 08 C5 E5 D5 06 00 ED B0 D1 E1 C1; -BAF8: 24 14 10 F2 F5 D5 EF 88 0E EB E3 EF 88 0E EB E3 D1 01 20 00 ED B0 F1 C1; -BB10: A7 28 03 04 18 01 05 0D 67 20 BB D1 43 E1 CD B8 3B EB 3A 3C 5C F5 21 0D; -BB28: EC CB 76 CB 87 28 02 CB C7 32 3C 5C 0E 00 CD 2B 37 EB 06 20 7E A7 20 02; -BB40: 3E 20 FE 90 30 0F EF 10 00 23 10 F0 F1 32 3C 5C CD B8 3B 37 C9 CD 20 1F; -BB58: D7 CD 45 1F 18 EB CD B8 3B 7A 90 3C 4F CD 98 3B C5 EF 9B 0E 0E 08 E5 06; -BB70: 20 AF 77 23 10 FC E1 24 0D 20 F3 06 20 C5 EF 88 0E EB C1 3A 8D 5C 77 23; -BB88: 10 FC C1 05 0D 20 D9 CD B8 3B 37 C9 3E 21 91 4F 3E 18 90 DD 96 01 47 C9; -BBA0: C5 AF 50 5F CB 1A CB 1B CB 1A CB 1B CB 1A CB 1B 21 00 58 47 09 19 C1 C9; -BBB8: F5 E5 D5 2A 8D 5C ED 5B 8F 5C D9 2A 0F EC ED 5B 11 EC 22 8D 5C ED 53 8F; -BBD0: 5C D9 22 0F EC ED 53 11 EC 21 13 EC 3A 91 5C 56 77 7A 32 91 5C D1 E1 F1; -BBE8: C9 CD 56 3C 21 3C 5C CB 86 CB F6 21 0E EC 36 FF CD 20 1F EF B0 16 2A 59; -BC00: 5C 01 0A 00 EF 55 16 21 16 3C ED 5B 59 5C 01 0A 00 ED B0 C3 11 1B F9 C0; -BC18: B0 22 31 35 36 31 36 22 28 09 DB FE E6 40 28 F5 23 18 F2 CB 15 CB 14 CB; -BC30: 15 CB 14 08 28 07 08 3E 20 94 6F 18 02 08 6C AF 67 11 1F 59 06 20 3E 48; -BC48: FB 76 F3 12 1B 10 FC 13 19 3E 68 77 18 A8 FB 06 19 76 10 FD 21 3B 5C CB; -BC60: AE 37 C9 3E 01 18 02 3E 00 32 8A FD 21 00 00 22 85 FD 22 87 FD 39 22 8B; -BC78: FD CD EA 34 3E 00 32 84 FD 21 74 FD 22 7D FD CD 20 1F EF B0 16 CD 45 1F; -BC90: 3E 00 32 81 FD 2A 59 5C 22 82 FD 21 00 00 22 7F FD 2A 85 FD 23 22 85 FD; -BCA8: CD 9D 3D 4F 3A 81 FD FE 00 20 41 79 E6 04 28 35 CD E9 3D 30 07 3E 01 32; -BCC0: 81 FD 18 DD 2A 7F FD 7D B4 C2 1E 3D C5 CD CD 3D C1 3E 00 32 81 FD 79 E6; -BCD8: 01 20 D8 78 CD 16 3E D0 2A 85 FD 23 22 85 FD CD 9D 3D 4F 18 E9 78 CD 16; -BCF0: 3E D0 18 AD FE 01 20 F5 79 E6 01 28 BB C5 CD 7E; -BD00: 3F C1 38 79 2A 7F FD 7C B5 20 13 79 E6 02 28 BC CD E9 3D 30 AF 2A 7D FD; -BD18: 2B 22 7F FD 18 83 C5 21 74 FD ED 5B 7F FD 7A BC 20 05 7B BD 20 01 13 1B; -BD30: 18 01 23 7E E6 7F E5 D5 CD 16 3E D1 E1 7C BA 20 F1 7D BB 20 ED ED 5B 7F; -BD48: FD 21 74 FD 22 7F FD ED 4B 7D FD 0B 7A BC 20 18 7B BD 20 14 13 E5 21 00; -BD60: 00 22 7F FD E1 78 BC 20 07 79 BD 20 03 C1 18 1F 1A 77 23 13 E6 80 28 F8; -BD78: 22 7D FD 18 81 C5 CD 16 3E C1 21 00 00 22 7F FD 3A 81 FD FE 04 28 05 3E; -BD90: 00 32 81 FD 21 74 FD 22 7D FD C3 B3 3C CD 54 2D 47 FE 3F 38 0A F6 20 CD; -BDA8: C6 3D 38 17 3E 01 C9 FE 20 28 0D FE 23 28 06 38 F3 FE 24 20 EF 3E 02 C9; -BDC0: 3E 03 C9 3E 06 C9 FE 7B D0 FE 61 3F C9 21 74 FD 22 7D FD 97 32 7F FD 32; -BDD8: 80 FD 7E E6 7F E5 CD 9C 3E E1 7E E6 80 C0 23 18 F1 2A 7D FD 11 7D FD 7A; -BDF0: BC 20 05 7B BD CA 13 3E 11 74 FD 7A BC 20 04 7B BD 28 06 2B 7E E6 7F 77; -BE08: 23 78 F6 80 77 23 22 7D FD 37 C9 37 3F C9 F5 3A 89 FD B7 20 12 F1 FE 3E; -BE20: 28 08 FE 3C 28 04 CD 64 3E C9 32 89 FD 37 C9 FE 3C 3E 00 32 89 FD 20 1A; -BE38: F1 FE 3E 20 04 3E C9 18 E5 FE 3D 20 04 3E C7 18 DD F5 3E 3C CD 64 3E F1; -BE50: 18 D4 F1 FE 3D 20 04 3E C8 18 CB F5 3E 3E CD 64 3E F1 18 C2 FE 0D 28 20; -BE68: FE EA 47 20 07 3E 04 32 81 FD 18 0E FE 22 20 0A 3A 81 FD E6 FE EE 02 32; -BE80: 81 FD 78 CD 9C 3E 37 C9 3A 8A FD FE 00 28 0A ED 4B 85 FD 2A 8B FD F9 37; -BE98: C9 37 3F C9 5F 3A 84 FD 57 7B FE 20 20 20 7A E6 01 20 14 7A E6 02 20 07; -BEB0: 7A F6 02 32 84 FD C9 7B CD FB 3E 3A 84 FD C9 7A E6 FE 32 84 FD C9 FE A3; -BEC8: 30 24 7A E6 02 20 0B 7A E6 FE 32 84 FD 7B CD FB 3E C9 D5 3E 20 CD FB 3E; -BEE0: D1 7A E6 FE E6 FD 32 84 FD 7B CD FB 3E C9 7A E6 FD F6 01 32 84 FD 7B CD; -BEF8: FB 3E C9 2A 87 FD 23 22 87 FD 2A 82 FD 47 3A 8A FD FE 00 78 28 25 ED 5B; -BF10: 5F 5C 7C BA 20 1A 7D BB 20 16 ED 4B 85 FD 2A 87 FD A7 ED 42 30 04 ED 4B; -BF28: 87 FD 2A 8B FD F9 37 C9 37 18 02 37 3F CD 20 1F 30 0D 7E EB FE 0E 20 1D; -BF40: 13 13 13 13 13 18 16 F5 01 01 00 E5 D5 CD 66 3F D1 E1 EF 64 16 2A 65 5C; -BF58: EB ED B8 F1 12 13 CD 45 1F ED 53 82 FD C9 2A 65 5C 09 38 0A EB 21 82 00; -BF70: 19 38 03 ED 72 D8 3E 03 32 3A 5C C3 21 03 CD 2E FD D8 06 F9 11 74 FD 21; -BF88: 94 35 CD 3B FD D0 FE FF 20 04 3E D4 18 22 FE FE 20 04 3E D3 18 1A FE FD; -BFA0: 20 04 3E CE 18 12 FE FC 20 04 3E ED 18 0A FE FB 20 04 3E EC 18 02 D6 56; -BFB8: 37 C9 46 23 7E 12 13 23 10 FA C9 FE 30 3F D0 FE 3A D0 D6 30 37 C9 C5 D5; -BFD0: 46 23 BE 23 5E 23 56 28 08 23 10 F6 37 3F D1 C1 C9 EB D1 C1 CD EE 3F 38; -BFE8: 02 BF C9 BF 37 C9 E9 00 4D 42 00 53 42 00 41 43 00 52 47 00 4B 4D 00 01; -C000: F3 AF 11 FF FF C3 CB 11 2A 5D 5C 22 5F 5C 18 43 C3 F2 15 FF FF FF FF FF; -C018: 2A 5D 5C 7E CD 7D 00 D0 CD 74 00 18 F7 FF FF FF C3 5B 33 FF FF FF FF FF; -C030: C5 2A 61 5C E5 C3 9E 16 F5 E5 2A 78 5C 23 22 78 5C 7C B5 20 03 FD 34 40; -C048: C5 D5 CD 6E 38 D1 C1 E1 F1 FB C9 E1 6E FD 75 00 ED 7B 3D 5C C3 C5 16 FF; -C060: FF FF FF FF FF FF F5 E5 2A B0 5C 7C B5 20 01 E9 E1 F1 ED 45 2A 5D 5C 23; -C078: 22 5D 5C 7E C9 FE 21 D0 FE 0D C8 FE 10 D8 FE 18 3F D8 23 FE 16 38 01 23; -C090: 37 22 5D 5C C9 BF 52 4E C4 49 4E 4B 45 59 A4 50 C9 46 CE 50 4F 49 4E D4; -C0A8: 53 43 52 45 45 4E A4 41 54 54 D2 41 D4 54 41 C2 56 41 4C A4 43 4F 44 C5; -C0C0: 56 41 CC 4C 45 CE 53 49 CE 43 4F D3 54 41 CE 41 53 CE 41 43 D3 41 54 CE; -C0D8: 4C CE 45 58 D0 49 4E D4 53 51 D2 53 47 CE 41 42 D3 50 45 45 CB 49 CE 55; -C0F0: 53 D2 53 54 52 A4 43 48 52 A4 4E 4F D4 42 49 CE 4F D2 41 4E C4 3C BD 3E; -C108: BD 3C BE 4C 49 4E C5 54 48 45 CE 54 CF 53 54 45 D0 44 45 46 20 46 CE 43; -C120: 41 D4 46 4F 52 4D 41 D4 4D 4F 56 C5 45 52 41 53 C5 4F 50 45 4E 20 A3 43; -C138: 4C 4F 53 45 20 A3 4D 45 52 47 C5 56 45 52 49 46 D9 42 45 45 D0 43 49 52; -C150: 43 4C C5 49 4E CB 50 41 50 45 D2 46 4C 41 53 C8 42 52 49 47 48 D4 49 4E; -C168: 56 45 52 53 C5 4F 56 45 D2 4F 55 D4 4C 50 52 49 4E D4 4C 4C 49 53 D4 53; -C180: 54 4F D0 52 45 41 C4 44 41 54 C1 52 45 53 54 4F 52 C5 4E 45 D7 42 4F 52; -C198: 44 45 D2 43 4F 4E 54 49 4E 55 C5 44 49 CD 52 45 CD 46 4F D2 47 4F 20 54; -C1B0: CF 47 4F 20 53 55 C2 49 4E 50 55 D4 4C 4F 41 C4 4C 49 53 D4 4C 45 D4 50; -C1C8: 41 55 53 C5 4E 45 58 D4 50 4F 4B C5 50 52 49 4E D4 50 4C 4F D4 52 55 CE; -C1E0: 53 41 56 C5 52 41 4E 44 4F 4D 49 5A C5 49 C6 43 4C D3 44 52 41 D7 43 4C; -C1F8: 45 41 D2 52 45 54 55 52 CE 43 4F 50 D9 42 48 59 36 35 54 47 56 4E 4A 55; -C210: 37 34 52 46 43 4D 4B 49 38 33 45 44 58 0E 4C 4F 39 32 57 53 5A 20 0D 50; -C228: 30 31 51 41 E3 C4 E0 E4 B4 BC BD BB AF B0 B1 C0 A7 A6 BE AD B2 BA E5 A5; -C240: C2 E1 B3 B9 C1 B8 7E DC DA 5C B7 7B 7D D8 BF AE AA AB DD DE DF 7F B5 D6; -C258: 7C D5 5D DB B6 D9 5B D7 0C 07 06 04 05 08 0A 0B 09 0F E2 2A 3F CD C8 CC; -C270: CB 5E AC 2D 2B 3D 2E 2C 3B 22 C7 3C C3 3E C5 2F C9 60 C6 3A D0 CE A8 CA; -C288: D3 D4 D1 D2 A9 CF 2E 2F 11 FF FF 01 FE FE ED 78 2F E6 1F 28 0E 67 7D 14; -C2A0: C0 D6 08 CB 3C 30 FA 53 5F 20 F4 2D CB 00 38 E6 7A 3C C8 FE 28 C8 FE 19; -C2B8: C8 7B 5A 57 FE 18 C9 CD 8E 02 C0 21 00 5C CB 7E 20 07 23 35 2B 20 02 36; -C2D0: FF 7D 21 04 5C BD 20 EE CD 1E 03 D0 21 00 5C BE 28 2E EB 21 04 5C BE 28; -C2E8: 27 CB 7E 20 04 EB CB 7E C8 5F 77 23 36 05 23 3A 09 5C 77 23 FD 4E 07 FD; -C300: 56 01 E5 CD 33 03 E1 77 32 08 5C FD CB 01 EE C9 23 36 05 23 35 C0 3A 0A; -C318: 5C 77 23 7E 18 EA 42 16 00 7B FE 27 D0 FE 18 20 03 CB 78 C0 21 05 02 19; -C330: 7E 37 C9 7B FE 3A 38 2F 0D FA 4F 03 28 03 C6 4F C9 21 EB 01 04 28 03 21; -C348: 05 02 16 00 19 7E C9 21 29 02 CB 40 28 F4 CB 5A 28 0A FD CB 30 5E C0 04; -C360: C0 C6 20 C9 C6 A5 C9 FE 30 D8 0D FA 9D 03 20 19 21 54 02 CB 68 28 D3 FE; -C378: 38 30 07 D6 20 04 C8 C6 08 C9 D6 36 04 C8 C6 FE C9 21 30 02 FE 39 28 BA; -C390: FE 30 28 B6 E6 07 C6 80 04 C8 EE 0F C9 04 C8 CB 68 21 30 02 20 A4 D6 10; -C3A8: FE 22 28 06 FE 20 C0 3E 5F C9 3E 40 C9 F3 7D CB 3D CB 3D 2F E6 03 4F 06; -C3C0: 00 DD 21 D1 03 DD 09 3A 48 5C E6 38 0F 0F 0F F6 08 00 00 00 04 0C 0D 20; -C3D8: FD 0E 3F 05 C2 D6 03 EE 10 D3 FE 44 4F CB 67 20 09 7A B3 28 09 79 4D 1B; -C3F0: DD E9 4D 0C DD E9 FB C9 EF 31 27 C0 03 34 EC 6C; -C400: 98 1F F5 04 A1 0F 38 21 92 5C 7E A7 20 5E 23 4E 23 46 78 17 9F B9 20 54; -C418: 23 BE 20 50 78 C6 3C F2 25 04 E2 6C 04 06 FA 04 D6 0C 30 FB C6 0C C5 21; -C430: 6E 04 CD 06 34 CD B4 33 EF 04 38 F1 86 77 EF C0 02 31 38 CD 94 1E FE 0B; -C448: 30 22 EF E0 04 E0 34 80 43 55 9F 80 01 05 34 35 71 03 38 CD 99 1E C5 CD; -C460: 99 1E E1 50 59 7A B3 C8 1B C3 B5 03 CF 0A 89 02 D0 12 86 89 0A 97 60 75; -C478: 89 12 D5 17 1F 89 1B 90 41 02 89 24 D0 53 CA 89 2E 9D 36 B1 89 38 FF 49; -C490: 3E 89 43 FF 6A 73 89 4F A7 00 54 89 5C 00 00 00 89 69 14 F6 24 89 76 F1; -C4A8: 10 05 CD FB 24 3A 3B 5C 87 FA 8A 1C E1 D0 E5 CD F1 2B 62 6B 0D F8 09 CB; -C4C0: FE C9 21 3F 05 E5 21 80 1F CB 7F 28 03 21 98 0C 08 13 DD 2B F3 3E 02 47; -C4D8: 10 FE D3 FE EE 0F 06 A4 2D 20 F5 05 25 F2 D8 04 06 2F 10 FE D3 FE 3E 0D; -C4F0: 06 37 10 FE D3 FE 01 0E 3B 08 6F C3 07 05 7A B3 28 0C DD 6E 00 7C AD 67; -C508: 3E 01 37 C3 25 05 6C 18 F4 79 CB 78 10 FE 30 04 06 42 10 FE D3 FE 06 3E; -C520: 20 EF 05 AF 3C CB 15 C2 14 05 1B DD 23 06 31 3E 7F DB FE 1F D0 7A 3C C2; -C538: FE 04 06 3B 10 FE C9 F5 3A 48 5C E6 38 0F 0F 0F D3 FE 3E 7F DB FE 1F FB; -C550: 38 02 CF 0C F1 C9 14 08 15 F3 3E 0F D3 FE 21 3F 05 E5 DB FE 1F E6 20 F6; -C568: 02 4F BF C0 CD E7 05 30 FA 21 15 04 10 FE 2B 7C B5 20 F9 CD E3 05 30 EB; -C580: 06 9C CD E3 05 30 E4 3E C6 B8 30 E0 24 20 F1 06 C9 CD E7 05 30 D5 78 FE; -C598: D4 30 F4 CD E7 05 D0 79 EE 03 4F 26 00 06 B0 18 1F 08 20 07 30 0F DD 75; -C5B0: 00 18 0F CB 11 AD C0 79 1F 4F 13 18 07 DD 7E 00 AD C0 DD 23 1B 08 06 B2; -C5C8: 2E 01 CD E3 05 D0 3E CB B8 CB 15 06 B0 D2 CA 05 7C AD 67 7A B3 20 CA 7C; -C5E0: FE 01 C9 CD E7 05 D0 3E 16 3D 20 FD A7 04 C8 3E 7F DB FE 1F D0 A9 E6 20; -C5F8: 28 F3 79 2F 4F E6 07 F6 08 D3 FE 37 C9 F1 3A 74 5C D6 E0 32 74 5C CD 8C; -C610: 1C CD 30 25 28 3C 01 11 00 3A 74 5C A7 28 02 0E 22 F7 D5 DD E1 06 0B 3E; -C628: 20 12 13 10 FC DD 36 01 FF CD F1 2B 21 F6 FF 0B 09 03 30 0F 3A 74 5C A7; -C640: 20 02 CF 0E 78 B1 28 0A 01 0A 00 DD E5 E1 23 EB ED B0 DF FE E4 20 49 3A; -C658: 74 5C FE 03 CA 8A 1C E7 CD B2 28 CB F9 30 0B 21 00 00 3A 74 5C 3D 28 15; -C670: CF 01 C2 8A 1C CD 30 25 28 18 23 7E DD 77 0B 23 7E DD 77 0C 23 DD 71 0E; -C688: 3E 01 CB 71 28 01 3C DD 77 00 EB E7 FE 29 20 DA E7 CD EE 1B EB C3 5A 07; -C6A0: FE AA 20 1F 3A 74 5C FE 03 CA 8A 1C E7 CD EE 1B DD 36 0B 00 DD 36 0C 1B; -C6B8: 21 00 40 DD 75 0D DD 74 0E 18 4D FE AF 20 4F 3A 74 5C FE 03 CA 8A 1C E7; -C6D0: CD 48 20 20 0C 3A 74 5C A7 CA 8A 1C CD E6 1C 18 0F CD 82 1C DF FE 2C 28; -C6E8: 0C 3A 74 5C A7 CA 8A 1C CD E6 1C 18 04 E7 CD 82 1C CD EE 1B CD 99 1E DD; -C700: 71 0B DD 70 0C CD 99 1E DD 71 0D DD 70 0E 60 69 DD 36 00 03 18 44 FE CA; -C718: 28 09 CD EE 1B DD 36 0E 80 18 17 3A 74 5C A7 C2 8A 1C E7 CD 82 1C CD EE; -C730: 1B CD 99 1E DD 71 0D DD 70 0E DD 36 00 00 2A 59 5C ED 5B 53 5C 37 ED 52; -C748: DD 75 0B DD 74 0C 2A 4B 5C ED 52 DD 75 0F DD 74 10 EB 3A 74 5C A7 CA 70; -C760: 09 E5 01 11 00 DD 09 DD E5 11 11 00 AF 37 CD 56 05 DD E1 30 F2 3E FE CD; -C778: 01 16 FD 36 52 03 0E 80 DD 7E 00 DD BE EF 20 02 0E F6 FE 04 30 D9 11 C0; -C790: 09 C5 CD 0A 0C C1 DD E5 D1 21 F0 FF 19 06 0A 7E 3C 20 03 79 80 4F 13 1A; -C7A8: BE 23 20 01 0C D7 10 F6 CB 79 20 B3 3E 0D D7 E1 DD 7E 00 FE 03 28 0C 3A; -C7C0: 74 5C 3D CA 08 08 FE 02 CA B6 08 E5 DD 6E FA DD 66 FB DD 5E 0B DD 56 0C; -C7D8: 7C B5 28 0D ED 52 38 26 28 07 DD 7E 00 FE 03 20 1D E1 7C B5 20 06 DD 6E; -C7F0: 0D DD 66 0E E5 DD E1 3A 74 5C FE 02 37 20 01 A7 3E FF CD 56 05 D8 CF 1A; -C808: DD 5E 0B DD 56 0C E5 7C B5 20 06 13 13 13 EB 18 0C DD 6E FA DD 66 FB EB; -C820: 37 ED 52 38 09 11 05 00 19 44 4D CD 05 1F E1 DD 7E 00 A7 28 3E 7C B5 28; -C838: 13 2B 46 2B 4E 2B 03 03 03 DD 22 5F 5C CD E8 19 DD 2A 5F 5C 2A 59 5C 2B; -C850: DD 4E 0B DD 46 0C C5 03 03 03 DD 7E FD F5 CD 55 16 23 F1 77 D1 23 73 23; -C868: 72 23 E5 DD E1 37 3E FF C3 02 08 EB 2A 59 5C 2B DD 22 5F 5C DD 4E 0B DD; -C880: 46 0C C5 CD E5 19 C1 E5 C5 CD 55 16 DD 2A 5F 5C 23 DD 4E 0F DD 46 10 09; -C898: 22 4B 5C DD 66 0E 7C E6 C0 20 0A DD 6E 0D 22 42 5C FD 36 0A 00 D1 DD E1; -C8B0: 37 3E FF C3 02 08 DD 4E 0B DD 46 0C C5 03 F7 36 80 EB D1 E5 E5 DD E1 37; -C8C8: 3E FF CD 02 08 E1 ED 5B 53 5C 7E E6 C0 20 19 1A 13 BE 23 20 02 1A BE 1B; -C8E0: 2B 30 08 E5 EB CD B8 19 E1 18 EC CD 2C 09 18 E2 7E 4F FE 80 C8 E5 2A 4B; -C8F8: 5C 7E FE 80 28 25 B9 28 08 C5 CD B8 19 C1 EB 18 F0 E6 E0 FE A0 20 12 D1; -C910: D5 E5 23 13 1A BE 20 06 17 30 F7 E1 18 03 E1 18 E0 3E FF D1 EB 3C 37 CD; -C928: 2C 09 18 C4 20 10 08 22 5F 5C EB CD B8 19 CD E8 19 EB 2A 5F 5C 08 08 D5; -C940: CD B8 19 22 5F 5C 2A 53 5C E3 C5 08 38 07 2B CD 55 16 23 18 03 CD 55 16; -C958: 23 C1 D1 ED 53 53 5C ED 5B 5F 5C C5 D5 EB ED B0 E1 C1 D5 CD E8 19 D1 C9; -C970: E5 3E FD CD 01 16 AF 11 A1 09 CD 0A 0C FD CB 02 EE CD D4 15 DD E5 11 11; -C988: 00 AF CD C2 04 DD E1 06 32 76 10 FD DD 5E 0B DD 56 0C 3E FF DD E1 C3 C2; -C9A0: 04 80 53 74 61 72 74 20 74 61 70 65 2C 20 74 68 65 6E 20 70 72 65 73 73; -C9B8: 20 61 6E 79 20 6B 65 79 AE 0D 50 72 6F 67 72 61 6D 3A A0 0D 4E 75 6D 62; -C9D0: 65 72 20 61 72 72 61 79 3A A0 0D 43 68 61 72 61 63 74 65 72 20 61 72 72; -C9E8: 61 79 3A A0 0D 42 79 74 65 73 3A A0 CD 03 0B FE 20 D2 D9 0A FE 06 38 69; -CA00: FE 18 30 65 21 0B 0A 5F 16 00 19 5E 19 E5 C3 03 0B 4E 57 10 29 54 53 52; -CA18: 37 50 4F 5F 5E 5D 5C 5B 5A 54 53 0C 3E 22 B9 20 11 FD CB 01 4E 20 09 04; -CA30: 0E 02 3E 18 B8 20 03 05 0E 21 C3 D9 0D 3A 91 5C F5 FD 36 57 01 3E 20 CD; -CA48: 65 0B F1 32 91 5C C9 FD CB 01 4E C2 CD 0E 0E 21 CD 55 0C 05 C3 D9 0D CD; -CA60: 03 0B 79 3D 3D E6 10 18 5A 3E 3F 18 6C 11 87 0A 32 0F 5C 18 0B 11 6D 0A; -CA78: 18 03 11 87 0A 32 0E 5C 2A 51 5C 73 23 72 C9 11 F4 09 CD 80 0A 2A 0E 5C; -CA90: 57 7D FE 16 DA 11 22 20 29 44 4A 3E 1F 91 38 0C C6 02 4F FD CB 01 4E 20; -CAA8: 16 3E 16 90 DA 9F 1E 3C 47 04 FD CB 02 46 C2 55 0C FD BE 31 DA 86 0C C3; -CAC0: D9 0D 7C CD 03 0B 81 3D E6 1F C8 57 FD CB 01 C6 3E 20 CD 3B 0C 15 20 F8; -CAD8: C9 CD 24 0B FD CB 01 4E 20 1A FD CB 02 46 20 08 ED 43 88 5C 22 84 5C C9; -CAF0: ED 43 8A 5C ED 43 82 5C 22 86 5C C9 FD 71 45 22; -CB00: 80 5C C9 FD CB 01 4E 20 14 ED 4B 88 5C 2A 84 5C FD CB 02 46 C8 ED 4B 8A; -CB18: 5C 2A 86 5C C9 FD 4E 45 2A 80 5C C9 FE 80 38 3D FE 90 30 26 47 CD 38 0B; -CB30: CD 03 0B 11 92 5C 18 47 21 92 5C CD 3E 0B CB 18 9F E6 0F 4F CB 18 9F E6; -CB48: F0 B1 0E 04 77 23 0D 20 FB C9 C3 9F 3B 00 C6 15 C5 ED 4B 7B 5C 18 0B CD; -CB60: 10 0C C3 03 0B C5 ED 4B 36 5C EB 21 3B 5C CB 86 FE 20 20 02 CB C6 26 00; -CB78: 6F 29 29 29 09 C1 EB 79 3D 3E 21 20 0E 05 4F FD CB 01 4E 28 06 D5 CD CD; -CB90: 0E D1 79 B9 D5 CC 55 0C D1 C5 E5 3A 91 5C 06 FF 1F 38 01 04 1F 1F 9F 4F; -CBA8: 3E 08 A7 FD CB 01 4E 28 05 FD CB 30 CE 37 EB 08 1A A0 AE A9 12 08 38 13; -CBC0: 14 23 3D 20 F2 EB 25 FD CB 01 4E CC DB 0B E1 C1 0D 23 C9 08 3E 20 83 5F; -CBD8: 08 18 E6 7C 0F 0F 0F E6 03 F6 58 67 ED 5B 8F 5C 7E AB A2 AB FD CB 57 76; -CBF0: 28 08 E6 C7 CB 57 20 02 EE 38 FD CB 57 66 28 08 E6 F8 CB 6F 20 02 EE 07; -CC08: 77 C9 E5 26 00 E3 18 04 11 95 00 F5 CD 41 0C 38 09 3E 20 FD CB 01 46 CC; -CC20: 3B 0C 1A E6 7F CD 3B 0C 1A 13 87 30 F5 D1 FE 48 28 03 FE 82 D8 7A FE 03; -CC38: D8 3E 20 D5 D9 D7 D9 D1 C9 F5 EB 3C CB 7E 23 28 FB 3D 20 F8 EB F1 FE 20; -CC50: D8 1A D6 41 C9 FD CB 01 4E C0 11 D9 0D D5 78 FD CB 02 46 C2 02 0D FD BE; -CC68: 31 38 1B C0 FD CB 02 66 28 16 FD 5E 2D 1D 28 5A 3E 00 CD 01 16 ED 7B 3F; -CC80: 5C FD CB 02 A6 C9 CF 04 FD 35 52 20 45 3E 18 90 32 8C 5C 2A 8F 5C E5 3A; -CC98: 91 5C F5 3E FD CD 01 16 AF 11 F8 0C CD 0A 0C FD CB 02 EE 21 3B 5C CB DE; -CCB0: CB AE D9 CD D4 15 D9 FE 20 28 45 FE E2 28 41 F6 20 FE 6E 28 3B 3E FE CD; -CCC8: 01 16 F1 32 91 5C E1 22 8F 5C CD FE 0D FD 46 31 04 0E 21 C5 CD 9B 0E 7C; -CCE0: 0F 0F 0F E6 03 F6 58 67 11 E0 5A 1A 4E 06 20 EB 12 71 13 23 10 FA C1 C9; -CCF8: 80 73 63 72 6F 6C 6C BF CF 0C FE 02 38 80 FD 86 31 D6 19 D0 ED 44 C5 47; -CD10: 2A 8F 5C E5 2A 91 5C E5 CD 4D 0D 78 F5 21 6B 5C 46 78 3C 77 21 89 5C BE; -CD28: 38 03 34 06 18 CD 00 0E F1 3D 20 E8 E1 FD 75 57 E1 22 8F 5C ED 4B 88 5C; -CD40: FD CB 02 86 CD D9 0D FD CB 02 C6 C1 C9 AF 2A 8D 5C FD CB 02 46 28 04 67; -CD58: FD 6E 0E 22 8F 5C 21 91 5C 20 02 7E 0F AE E6 55 AE 77 C9 CD AF 0D 21 3C; -CD70: 5C CB AE CB C6 CD 4D 0D FD 46 31 CD 44 0E 21 C0 5A 3A 8D 5C 05 18 07 0E; -CD88: 20 2B 77 0D 20 FB 10 F7 FD 36 31 02 3E FD CD 01 16 2A 51 5C 11 F4 09 A7; -CDA0: 73 23 72 23 11 A8 10 3F 38 F6 01 21 17 18 2A 21 00 00 22 7D 5C FD CB 30; -CDB8: 86 CD 94 0D 3E FE CD 01 16 CD 4D 0D 06 18 CD 44 0E 2A 51 5C 11 F4 09 73; -CDD0: 23 72 FD 36 52 01 01 21 18 21 00 5B FD CB 01 4E 20 12 78 FD CB 02 46 28; -CDE8: 05 FD 86 31 D6 18 C5 47 CD 9B 0E C1 3E 21 91 5F 16 00 19 C3 DC 0A 06 17; -CE00: CD 9B 0E 0E 08 C5 E5 78 E6 07 78 20 0C EB 21 E0 F8 19 EB 01 20 00 3D ED; -CE18: B0 EB 21 E0 FF 19 EB 47 E6 07 0F 0F 0F 4F 78 06 00 ED B0 06 07 09 E6 F8; -CE30: 20 DB E1 24 C1 0D 20 CD CD 88 0E 21 E0 FF 19 EB ED B0 06 01 C5 CD 9B 0E; -CE48: 0E 08 C5 E5 78 E6 07 0F 0F 0F 4F 78 06 00 0D 54 5D 36 00 13 ED B0 11 01; -CE60: 07 19 3D E6 F8 47 20 E5 E1 24 C1 0D 20 DC CD 88 0E 62 6B 13 3A 8D 5C FD; -CE78: CB 02 46 28 03 3A 48 5C 77 0B ED B0 C1 0E 21 C9 7C 0F 0F 0F 3D F6 50 67; -CE90: EB 61 68 29 29 29 29 29 44 4D C9 3E 18 90 57 0F 0F 0F E6 E0 6F 7A E6 18; -CEA8: F6 40 67 C9 F3 06 B0 21 00 40 E5 C5 CD F4 0E C1 E1 24 7C E6 07 20 0A 7D; -CEC0: C6 20 6F 3F 9F E6 F8 84 67 10 E7 18 0D F3 21 00 5B 06 08 C5 CD F4 0E C1; -CED8: 10 F9 3E 04 D3 FB FB 21 00 5B FD 75 46 AF 47 77 23 10 FC FD CB 30 8E 0E; -CEF0: 21 C3 D9 0D 78 FE 03 9F E6 02 D3 FB 57 CD 54 1F 38 0A 3E 04 D3 FB FB CD; -CF08: DF 0E CF 0C DB FB 87 F8 30 EB 0E 20 5E 23 06 08 CB 12 CB 13 CB 1A DB FB; -CF20: 1F 30 FB 7A D3 FB 10 F0 0D 20 E9 C9 2A 3D 5C E5 21 7F 10 E5 ED 73 3D 5C; -CF38: CD D4 15 F5 16 00 FD 5E FF 21 C8 00 CD B5 03 F1 21 38 0F E5 FE 18 30 31; -CF50: FE 07 38 2D FE 10 38 3A 01 02 00 57 FE 16 38 0C 03 FD CB 37 7E CA 1E 10; -CF68: CD D4 15 5F CD D4 15 D5 2A 5B 5C FD CB 07 86 CD 55 16 C1 23 70 23 71 18; -CF80: 0A FD CB 07 86 2A 5B 5C CD 52 16 12 13 ED 53 5B 5C C9 5F 16 00 21 99 0F; -CF98: 19 5E 19 E5 2A 5B 5C C9 09 66 6A 50 B5 70 7E CF D4 2A 49 5C FD CB 37 6E; -CFB0: C2 97 10 CD 6E 19 CD 95 16 7A B3 CA 97 10 E5 23 4E 23 46 21 0A 00 09 44; -CFC8: 4D CD 05 1F CD 97 10 2A 51 5C E3 E5 3E FF CD 01 16 E1 2B FD 35 0F CD 55; -CFE0: 18 FD 34 0F 2A 59 5C 23 23 23 23 22 5B 5C E1 CD 15 16 C9 FD CB 37 6E 20; -CFF8: 08 21 49 5C CD 0F 19 18 6D FD 36 00 10 18 1D CD 31 10 18 05 7E FE 0D C8; -D010: 23 22 5B 5C C9 CD 31 10 01 01 00 C3 E8 19 CD D4 15 CD D4 15 E1 E1 E1 22; -D028: 3D 5C FD CB 00 7E C0 F9 C9 37 CD 95 11 ED 52 19 23 C1 D8 C5 44 4D 62 6B; -D040: 23 1A E6 F0 FE 10 20 09 23 1A D6 17 CE 00 20 01 23 A7 ED 42 09 EB 38 E6; -D058: C9 FD CB 37 6E C0 2A 49 5C CD 6E 19 EB CD 95 16 21 4A 5C CD 1C 19 CD 95; -D070: 17 3E 00 C3 01 16 FD CB 37 7E 28 A8 C3 81 0F FD CB 30 66 28 A1 FD 36 00; -D088: FF 16 00 FD 5E FE 21 90 1A CD B5 03 C3 30 0F E5 CD 90 11 2B CD E5 19 22; -D0A0: 5B 5C FD 36 07 00 E1 C9 FD CB 02 5E C4 1D 11 A7 FD CB 01 6E C8 3A 08 5C; -D0B8: FD CB 01 AE F5 FD CB 02 6E C4 6E 0D F1 FE 20 30 52 FE 10 30 2D FE 06 30; -D0D0: 0A 47 E6 01 4F 78 1F C6 12 18 2A 20 09 21 6A 5C 3E 08 AE 77 18 0E FE 0E; -D0E8: D8 D6 0D 21 41 5C BE 77 20 02 36 00 FD CB 02 DE BF C9 47 E6 07 4F 3E 10; -D100: CB 58 20 01 3C FD 71 D3 11 0D 11 18 06 3A 0D 5C 11 A8 10 2A 4F 5C 23 23; -D118: 73 23 72 37 C9 CD 4D 0D FD CB 02 9E FD CB 02 AE 2A 8A 5C E5 2A 3D 5C E5; -D130: 21 67 11 E5 ED 73 3D 5C 2A 82 5C E5 37 CD 95 11 EB CD 7D 18 EB CD E1 18; -D148: 2A 8A 5C E3 EB CD 4D 0D 3A 8B 5C 92 38 26 20 06 7B FD 96 50 30 1E 3E 20; -D160: D5 CD F4 09 D1 18 E9 16 00 FD 5E FE 21 90 1A CD B5 03 FD 36 00 FF ED 5B; -D178: 8A 5C 18 02 D1 E1 E1 22 3D 5C C1 D5 CD D9 0D E1 22 82 5C FD 36 26 00 C9; -D190: 2A 61 5C 2B A7 ED 5B 59 5C FD CB 37 6E C8 ED 5B 61 5C D8 2A 63 5C C9 7E; -D1A8: FE 0E 01 06 00 CC E8 19 7E 23 FE 0D 20 F1 C9 F3 3E FF ED 5B B2 5C D9 ED; -D1C0: 4B B4 5C ED 5B 38 5C 2A 7B 5C D9 47 3E 07 D3 FE 3E 3F ED 47 00 00 00 00; -D1D8: 00 00 62 6B 36 02 2B BC 20 FA A7 ED 52 19 23 30 06 35 28 03 35 28 F3 2B; -D1F0: D9 ED 43 B4 5C ED 53 38 5C 22 7B 5C D9 04 28 19; -D200: 22 B4 5C 11 AF 3E 01 A8 00 EB ED B8 EB 23 22 7B 5C 2B 01 40 00 ED 43 38; -D218: 5C 22 B2 5C 21 00 3C 22 36 5C 2A B2 5C 36 3E 2B F9 2B 2B 22 3D 5C ED 56; -D230: FD 21 3A 5C FB 21 B6 5C 22 4F 5C 11 AF 15 01 15 00 EB ED B0 EB 2B 22 57; -D248: 5C 23 22 53 5C 22 4B 5C 36 80 23 22 59 5C 36 0D 23 36 80 23 22 61 5C 22; -D260: 63 5C 22 65 5C 3E 38 32 8D 5C 32 8F 5C 32 48 5C 21 23 05 22 09 5C FD 35; -D278: C6 FD 35 CA 21 C6 15 11 10 5C 01 0E 00 ED B0 FD CB 01 CE CD DF 0E FD 36; -D290: 31 02 CD 6B 0D AF 11 38 15 CD 0A 0C FD CB 02 EE 18 07 FD 36 31 02 CD 95; -D2A8: 17 CD B0 16 3E 00 CD 01 16 CD 2C 0F CD 17 1B FD CB 00 7E 20 12 FD CB 30; -D2C0: 66 28 40 2A 59 5C CD A7 11 FD 36 00 FF 18 DD 2A 59 5C 22 5D 5C CD FB 19; -D2D8: 78 B1 C2 5D 15 DF FE 0D 28 C0 FD CB 30 46 C4 AF 0D CD 6E 0D 3E 19 FD 96; -D2F0: 4F 32 8C 5C FD CB 01 FE FD 36 00 FF FD 36 0A 01 CD 8A 1B 76 FD CB 01 AE; -D308: FD CB 30 4E C4 CD 0E 3A 3A 5C 3C F5 21 00 00 FD 74 37 FD 74 26 22 0B 5C; -D320: 21 01 00 22 16 5C CD B0 16 FD CB 37 AE CD 6E 0D FD CB 02 EE F1 47 FE 0A; -D338: 38 02 C6 07 CD EF 15 3E 20 D7 78 11 91 13 CD 0A 0C CD 3B 3B 00 CD 0A 0C; -D350: ED 4B 45 5C CD 1B 1A 3E 3A D7 FD 4E 0D 06 00 CD 1B 1A CD 97 10 3A 3A 5C; -D368: 3C 28 1B FE 09 28 04 FE 15 20 03 FD 34 0D 01 03 00 11 70 5C 21 44 5C CB; -D380: 7E 28 01 09 ED B8 FD 36 0A FF FD CB 01 9E C3 AC 12 80 4F CB 4E 45 58 54; -D398: 20 77 69 74 68 6F 75 74 20 46 4F D2 56 61 72 69 61 62 6C 65 20 6E 6F 74; -D3B0: 20 66 6F 75 6E E4 53 75 62 73 63 72 69 70 74 20 77 72 6F 6E E7 4F 75 74; -D3C8: 20 6F 66 20 6D 65 6D 6F 72 F9 4F 75 74 20 6F 66 20 73 63 72 65 65 EE 4E; -D3E0: 75 6D 62 65 72 20 74 6F 6F 20 62 69 E7 52 45 54 55 52 4E 20 77 69 74 68; -D3F8: 6F 75 74 20 47 4F 53 55 C2 45 6E 64 20 6F 66 20 66 69 6C E5 53 54 4F 50; -D410: 20 73 74 61 74 65 6D 65 6E F4 49 6E 76 61 6C 69 64 20 61 72 67 75 6D 65; -D428: 6E F4 49 6E 74 65 67 65 72 20 6F 75 74 20 6F 66 20 72 61 6E 67 E5 4E 6F; -D440: 6E 73 65 6E 73 65 20 69 6E 20 42 41 53 49 C3 42 52 45 41 4B 20 2D 20 43; -D458: 4F 4E 54 20 72 65 70 65 61 74 F3 4F 75 74 20 6F 66 20 44 41 54 C1 49 6E; -D470: 76 61 6C 69 64 20 66 69 6C 65 20 6E 61 6D E5 4E 6F 20 72 6F 6F 6D 20 66; -D488: 6F 72 20 6C 69 6E E5 53 54 4F 50 20 69 6E 20 49 4E 50 55 D4 46 4F 52 20; -D4A0: 77 69 74 68 6F 75 74 20 4E 45 58 D4 49 6E 76 61 6C 69 64 20 49 2F 4F 20; -D4B8: 64 65 76 69 63 E5 49 6E 76 61 6C 69 64 20 63 6F 6C 6F 75 F2 42 52 45 41; -D4D0: 4B 20 69 6E 74 6F 20 70 72 6F 67 72 61 ED 52 41 4D 54 4F 50 20 6E 6F 20; -D4E8: 67 6F 6F E4 53 74 61 74 65 6D 65 6E 74 20 6C 6F 73 F4 49 6E 76 61 6C 69; -D500: 64 20 73 74 72 65 61 ED 46 4E 20 77 69 74 68 6F 75 74 20 44 45 C6 50 61; -D518: 72 61 6D 65 74 65 72 20 65 72 72 6F F2 54 61 70 65 20 6C 6F 61 64 69 6E; -D530: 67 20 65 72 72 6F F2 2C A0 7F 20 31 39 38 32 20 53 69 6E 63 6C 61 69 72; -D548: 20 52 65 73 65 61 72 63 68 20 4C 74 E4 3E 10 01 00 00 C3 13 13 ED 43 49; -D560: 5C 2A 5D 5C EB 21 55 15 E5 2A 61 5C 37 ED 52 E5 60 69 CD 6E 19 20 06 CD; -D578: B8 19 CD E8 19 C1 79 3D B0 28 28 C5 03 03 03 03 2B ED 5B 53 5C D5 CD 55; -D590: 16 E1 22 53 5C C1 C5 13 2A 61 5C 2B 2B ED B8 2A 49 5C EB C1 70 2B 71 2B; -D5A8: 73 2B 72 F1 C3 A2 12 F4 09 A8 10 4B F4 09 C4 15 53 81 0F C4 15 52 F4 09; -D5C0: C4 15 50 80 CF 12 01 00 06 00 0B 00 01 00 01 00 06 00 10 00 FD CB 02 6E; -D5D8: 20 04 FD CB 02 DE CD E6 15 D8 28 FA CF 07 D9 E5 2A 51 5C 23 23 18 08 1E; -D5F0: 30 83 D9 E5 2A 51 5C 5E 23 56 EB CD 2C 16 E1 D9 C9 87 C6 16 6F 26 5C 5E; -D608: 23 56 7A B3 20 02 CF 17 1B 2A 4F 5C 19 22 51 5C FD CB 30 A6 23 23 23 23; -D620: 4E 21 2D 16 CD DC 16 D0 16 00 5E 19 E9 4B 06 53 12 50 1B 00 FD CB 02 C6; -D638: FD CB 01 AE FD CB 30 E6 18 04 FD CB 02 86 FD CB 01 8E C3 4D 0D FD CB 01; -D650: CE C9 01 01 00 E5 CD 05 1F E1 CD 64 16 2A 65 5C EB ED B8 C9 F5 E5 21 4B; -D668: 5C 3E 0E 5E 23 56 E3 A7 ED 52 19 E3 30 09 D5 EB 09 EB 72 2B 73 23 D1 23; -D680: 3D 20 E8 EB D1 F1 A7 ED 52 44 4D 03 19 EB C9 00 00 EB 11 8F 16 7E E6 C0; -D698: 20 F7 56 23 5E C9 2A 63 5C 2B CD 55 16 23 23 C1 ED 43 61 5C C1 EB 23 C9; -D6B0: 2A 59 5C 36 0D 22 5B 5C 23 36 80 23 22 61 5C 2A 61 5C 22 63 5C 2A 63 5C; -D6C8: 22 65 5C E5 21 92 5C 22 68 5C E1 C9 ED 5B 59 5C C3 E5 19 23 7E A7 C8 B9; -D6E0: 23 20 F8 37 C9 CD 1E 17 CD 01 17 01 00 00 11 E2 A3 EB 19 38 07 01 D4 15; -D6F8: 09 4E 23 46 EB 71 23 70 C9 E5 2A 4F 5C 09 23 23 23 4E EB 21 16 17 CD DC; -D710: 16 4E 06 00 09 E9 4B 05 53 03 50 01 E1 C9 CD 94 1E FE 10 38 02 CF 17 C6; -D728: 03 07 21 10 5C 4F 06 00 09 4E 23 46 2B C9 EF 01 38 CD 1E 17 78 B1 28 16; -D740: EB 2A 4F 5C 09 23 23 23 7E EB FE 4B 28 08 FE 53 28 04 FE 50 20 CF CD 5D; -D758: 17 73 23 72 C9 E5 CD F1 2B 78 B1 20 02 CF 0E C5 1A E6 DF 4F 21 7A 17 CD; -D770: DC 16 30 F1 4E 06 00 09 C1 E9 4B 06 53 08 50 0A 00 1E 01 18 06 1E 06 18; -D788: 02 1E 10 0B 78 B1 20 D5 57 E1 C9 18 90 ED 73 3F 5C FD 36 02 10 CD AF 0D; -D7A0: FD CB 02 C6 FD 46 31 CD 44 0E FD CB 02 86 FD CB 30 C6 2A 49 5C ED 5B 6C; -D7B8: 5C A7 ED 52 19 38 22 D5 CD 6E 19 11 C0 02 EB ED 52 E3 CD 6E 19 C1 C5 CD; -D7D0: B8 19 C1 09 38 0E EB 56 23 5E 2B ED 53 6C 5C 18 ED 22 6C 5C 2A 6C 5C CD; -D7E8: 6E 19 28 01 EB CD 33 18 FD CB 02 A6 C9 3E 03 18 02 3E 02 FD 36 02 00 CD; -D800: 30 25 C4 01 16 DF CD 70 20 38 14 DF FE 3B 28 04 FE 2C 20 06 E7 CD 82 1C; -D818: 18 08 CD E6 1C 18 03 CD DE 1C CD EE 1B CD 99 1E 78 E6 3F 67 69 22 49 5C; -D830: CD 6E 19 1E 01 CD 55 18 D7 FD CB 02 66 28 F6 3A 6B 5C FD 96 4F 20 EE AB; -D848: C8 E5 D5 21 6C 5C CD 0F 19 D1 E1 18 E0 ED 4B 49 5C CD 80 19 16 3E 28 05; -D860: 11 00 00 CB 13 FD 73 2D 7E FE 40 C1 D0 C5 CD 28 1A 23 23 23 FD CB 01 86; -D878: 7A A7 28 05 D7 FD CB 01 C6 D5 EB FD CB 30 96 21 3B 5C CB 96 FD CB 37 6E; -D890: 28 02 CB D6 2A 5F 5C A7 ED 52 20 05 3E 3F CD C1 18 CD E1 18 EB 7E CD B6; -D8A8: 18 23 FE 0D 28 06 EB CD 37 19 18 E0 D1 C9 FE 0E C0 23 23 23 23 23 23 7E; -D8C0: C9 D9 2A 8F 5C E5 CB BC CB FD 22 8F 5C 21 91 5C 56 D5 36 00 CD F4 09 E1; -D8D8: FD 74 57 E1 22 8F 5C D9 C9 2A 5B 5C A7 ED 52 C0 3A 41 5C CB 07 28 04 C6; -D8F0: 43 18 16 21 3B 5C CB 9E 3E 4B CB 56 28 0B CB DE; -D900: 3C FD CB 30 5E 28 02 3E 43 D5 CD C1 18 D1 C9 5E 23 56 E5 EB 23 CD 6E 19; -D918: CD 95 16 E1 FD CB 37 6E C0 72 2B 73 C9 7B A7 F8 18 0D AF 09 3C 38 FC ED; -D930: 42 3D 28 F1 C3 EF 15 CD 1B 2D 30 30 FE 21 38 2C FD CB 01 96 FE CB 28 24; -D948: FE 3A 20 0E FD CB 37 6E 20 16 FD CB 30 56 28 14 18 0E FE 22 20 0A F5 3A; -D960: 6A 5C EE 04 32 6A 5C F1 FD CB 01 D6 D7 C9 E5 2A 53 5C 54 5D C1 CD 80 19; -D978: D0 C5 CD B8 19 EB 18 F4 7E B8 C0 23 7E 2B B9 C9 23 23 23 22 5D 5C 0E 00; -D990: 15 C8 E7 BB 20 04 A7 C9 23 7E CD B6 18 22 5D 5C FE 22 20 01 0D FE 3A 28; -D9A8: 04 FE CB 20 04 CB 41 28 DF FE 0D 20 E3 15 37 C9 E5 7E FE 40 38 17 CB 6F; -D9C0: 28 14 87 FA C7 19 3F 01 05 00 30 02 0E 12 17 23 7E 30 FB 18 06 23 23 4E; -D9D8: 23 46 23 09 D1 A7 ED 52 44 4D 19 EB C9 CD DD 19 C5 78 2F 47 79 2F 4F 03; -D9F0: CD 64 16 EB E1 19 D5 ED B0 E1 C9 2A 59 5C 2B 22 5D 5C E7 21 92 5C 22 65; -DA08: 5C CD 3B 2D CD A2 2D 38 04 21 F0 D8 09 DA 8A 1C C3 C5 16 D5 E5 AF CB 78; -DA20: 20 20 60 69 1E FF 18 08 D5 56 23 5E E5 EB 1E 20 01 18 FC CD 2A 19 01 9C; -DA38: FF CD 2A 19 0E F6 CD 2A 19 7D CD EF 15 E1 D1 C9 B1 CB BC BF C4 AF B4 93; -DA50: 91 92 95 98 98 98 98 98 98 98 7F 81 2E 6C 6E 70 48 94 56 3F 41 2B 17 1F; -DA68: 37 77 44 0F 59 2B 43 2D 51 3A 6D 42 0D 49 5C 44 15 5D 01 3D 02 06 00 67; -DA80: 1E 06 CB 05 F0 1C 06 00 ED 1E 00 EE 1C 00 23 1F 04 3D 06 CC 06 05 03 1D; -DA98: 04 00 AB 1D 05 CD 1F 05 89 20 05 02 2C 05 B2 1B 00 B7 11 03 A1 1E 05 F9; -DAB0: 17 08 00 80 1E 03 4F 1E 00 5F 1E 03 AC 1E 00 6B 0D 09 00 DC 22 06 00 3A; -DAC8: 1F 05 ED 1D 05 27 1E 03 42 1E 09 05 82 23 00 AC 0E 05 C9 1F 05 F5 17 0B; -DAE0: 0B 0B 0B 08 00 F8 03 09 05 20 23 07 07 07 07 07 07 08 00 7A 1E 06 00 94; -DAF8: 22 05 60 1F 06 2C 0A 00 36 17 06 00 E5 16 0A 00 93 17 0A 2C 0A 00 93 17; -DB10: 0A 00 93 17 00 93 17 FD CB 01 BE CD FB 19 AF 32 47 5C 3D 32 3A 5C 18 01; -DB28: E7 CD BF 16 FD 34 0D FA 8A 1C DF 06 00 FE 0D 28 7A FE 3A 28 EB 21 76 1B; -DB40: E5 4F E7 79 D6 CE DA 8A 1C 4F 21 48 1A 09 4E 09 18 03 2A 74 5C 7E 23 22; -DB58: 74 5C 01 52 1B C5 4F FE 20 30 0C 21 01 1C 06 00 09 4E 09 E5 DF 05 C9 DF; -DB70: B9 C2 8A 1C E7 C9 CD 54 1F 38 02 CF 14 CD 4D 3B 00 20 71 2A 42 5C CB 7C; -DB88: 28 14 21 FE FF 22 45 5C 2A 61 5C 2B ED 5B 59 5C 1B 3A 44 5C 18 33 CD 6E; -DBA0: 19 3A 44 5C 28 19 A7 20 43 47 7E E6 C0 78 28 0F CF FF C1 CD 30 25 C8 2A; -DBB8: 55 5C 3E C0 A6 C0 AF FE 01 CE 00 56 23 5E ED 53 45 5C 23 5E 23 56 EB 19; -DBD0: 23 22 55 5C EB 22 5D 5C 57 1E 00 FD 36 0A FF 15 FD 72 0D CA 28 1B 14 CD; -DBE8: 8B 19 28 08 CF 16 CD 30 25 C0 C1 C1 CD 5D 3B 28 BA FE 3A CA 28 1B C3 8A; -DC00: 1C 0F 1D 4B 09 67 0B 7B 8E 71 B4 81 CF CD DE 1C BF C1 CC EE 1B EB 2A 74; -DC18: 5C 4E 23 46 EB C5 C9 CD B2 28 FD 36 37 00 30 08 FD CB 37 CE 20 18 CF 01; -DC30: CC 96 29 FD CB 01 76 20 0D AF CD 30 25 C4 F1 2B 21 71 5C B6 77 EB ED 43; -DC48: 72 5C 22 4D 5C C9 C1 CD 56 1C CD EE 1B C9 3A 3B 5C F5 CD FB 24 F1 FD 56; -DC60: 01 AA E6 40 20 24 CB 7A C2 FF 2A C9 CD B2 28 F5 79 F6 9F 3C 20 14 F1 18; -DC78: A9 E7 CD 82 1C FE 2C 20 09 E7 CD FB 24 FD CB 01 76 C0 CF 0B CD FB 24 FD; -DC90: CB 01 76 C8 18 F4 FD CB 01 7E FD CB 02 86 C4 4D 0D F1 3A 74 5C D6 13 CD; -DCA8: FC 21 CD EE 1B 2A 8F 5C 22 8D 5C 21 91 5C 7E 07 AE E6 AA AE 77 C9 CD 30; -DCC0: 25 28 13 FD CB 02 86 CD 4D 0D 21 90 5C 7E F6 F8 77 FD CB 57 B6 DF CD E2; -DCD8: 21 18 9F C3 05 06 FE 0D 28 04 FE 3A 20 9C CD 30 25 C8 EF A0 38 C9 CF 08; -DCF0: C1 CD 30 25 28 0A EF 02 38 EB CD E9 34 DA B3 1B C3 29 1B FE CD 20 09 E7; -DD08: CD 82 1C CD EE 1B 18 06 CD EE 1B EF A1 38 EF C0 02 01 E0 01 38 CD FF 2A; -DD20: 22 68 5C 2B 7E CB FE 01 06 00 09 07 38 06 0E 0D CD 55 16 23 E5 EF 02 02; -DD38: 38 E1 EB 0E 0A ED B0 2A 45 5C EB 73 23 72 FD 56 0D 14 23 72 CD DA 1D D0; -DD50: FD 46 38 2A 45 5C 22 42 5C 3A 47 5C ED 44 57 2A 5D 5C 1E F3 C5 ED 4B 55; -DD68: 5C CD 86 1D ED 43 55 5C C1 38 11 E7 F6 20 B8 28 03 E7 18 E8 E7 3E 01 92; -DD80: 32 44 5C C9 CF 11 7E FE 3A 28 18 23 7E E6 C0 37 C0 46 23 4E ED 43 42 5C; -DD98: 23 4E 23 46 E5 09 44 4D E1 16 00 C5 CD 8B 19 C1 D0 18 E0 FD CB 37 4E C2; -DDB0: 2E 1C 2A 4D 5C CB 7E 28 1F 23 22 68 5C EF E0 E2 0F C0 02 38 CD DA 1D D8; -DDC8: 2A 68 5C 11 0F 00 19 5E 23 56 23 66 EB C3 73 1E CF 00 EF E1 E0 E2 36 00; -DDE0: 02 01 03 37 00 04 38 A7 C9 38 37 C9 E7 CD 1F 1C CD 30 25 28 29 DF 22 5F; -DDF8: 5C 2A 57 5C 7E FE 2C 28 09 1E E4 CD 86 1D 30 02 CF 0D CD 77 00 CD 56 1C; -DE10: DF 22 57 5C 2A 5F 5C FD 36 26 00 CD 78 00 DF FE 2C 28 C9 CD EE 1B C9 CD; -DE28: 30 25 20 0B CD FB 24 FE 2C C4 EE 1B E7 18 F5 3E E4 47 ED B9 11 00 02 C3; -DE40: 8B 19 CD 99 1E 60 69 CD 6E 19 2B 22 57 5C C9 CD 99 1E 78 B1 20 04 ED 4B; -DE58: 78 5C ED 43 76 5C C9 2A 6E 5C FD 56 36 18 0C CD 99 1E 60 69 16 00 7C FE; -DE70: F0 30 2C 22 42 5C FD 72 0A C9 CD 85 1E ED 79 C9 CD 85 1E 02 C9 CD D5 2D; -DE88: 38 15 28 02 ED 44 F5 CD 99 1E F1 C9 CD D5 2D 18 03 CD A2 2D 38 01 C8 CF; -DEA0: 0A CD 67 1E 01 00 00 CD 45 1E 18 03 CD 99 1E 78 B1 20 04 ED 4B B2 5C C5; -DEB8: ED 5B 4B 5C 2A 59 5C 2B CD E5 19 CD 6B 0D 2A 65 5C 11 32 00 19 D1 ED 52; -DED0: 30 08 2A B4 5C A7 ED 52 30 02 CF 15 EB 22 B2 5C D1 C1 36 3E 2B F9 C5 ED; -DEE8: 73 3D 5C EB E9 D1 FD 66 0D 24 E3 33 ED 4B 45 5C C5 E5 ED 73 3D 5C D5 CD; -DF00: 67 1E 01 14 00 2A 65 5C 09 38 0A EB 21 50 00 19 38 03 ED 72 D8 2E 03 C3; -DF18: 55 00 01 00 00 CD 05 1F 44 4D C9 C1 E1 D1 7A FE 3E 28 0B 3B E3 EB ED 73; -DF30: 3D 5C C5 C3 73 1E D5 E5 CF 06 CD 99 1E 76 0B 78 B1 28 0C 78 A1 3C 20 01; -DF48: 03 FD CB 01 6E 28 EE FD CB 01 AE C9 3E 7F DB FE 1F D8 3E FE DB FE 1F C9; -DF60: CD 30 25 28 05 3E CE C3 39 1E FD CB 01 F6 CD 8D 2C 30 16 E7 FE 24 20 05; -DF78: FD CB 01 B6 E7 FE 28 20 3C E7 FE 29 28 20 CD 8D 2C D2 8A 1C EB E7 FE 24; -DF90: 20 02 EB E7 EB 01 06 00 CD 55 16 23 23 36 0E FE 2C 20 03 E7 18 E0 FE 29; -DFA8: 20 13 E7 FE 3D 20 0E E7 3A 3B 5C F5 CD FB 24 F1 FD AE 01 E6 40 C2 8A 1C; -DFC0: CD EE 1B CD 30 25 E1 C8 E9 3E 03 18 02 3E 02 CD 30 25 C4 01 16 CD 4D 0D; -DFD8: CD DF 1F CD EE 1B C9 DF CD 45 20 28 0D CD 4E 20 28 FB CD FC 1F CD 4E 20; -DFF0: 28 F3 FE 29 C8 CD C3 1F 3E 0D D7 C9 DF FE AC 20; -E000: 0D CD 79 1C CD C3 1F CD 07 23 3E 16 18 10 FE AD 20 12 E7 CD 82 1C CD C3; -E018: 1F CD 99 1E 3E 17 D7 79 D7 78 D7 C9 CD F2 21 D0 CD 70 20 D0 CD FB 24 CD; -E030: C3 1F FD CB 01 76 CC F1 2B C2 E3 2D 78 B1 0B C8 1A 13 D7 18 F7 FE 29 C8; -E048: FE 0D C8 FE 3A C9 DF FE 3B 28 14 FE 2C 20 0A CD 30 25 28 0B 3E 06 D7 18; -E060: 06 FE 27 C0 CD F5 1F E7 CD 45 20 20 01 C1 BF C9 FE 23 37 C0 E7 CD 82 1C; -E078: A7 CD C3 1F CD 94 1E FE 10 D2 0E 16 CD 01 16 A7 C9 CD 30 25 28 08 3E 01; -E090: CD 01 16 CD 6E 0D FD 36 02 01 CD C1 20 CD EE 1B ED 4B 88 5C 3A 6B 5C B8; -E0A8: 38 03 0E 21 47 ED 43 88 5C 3E 19 90 32 8C 5C FD CB 02 86 CD D9 0D C3 6E; -E0C0: 0D CD 4E 20 28 FB FE 28 20 0E E7 CD DF 1F DF FE 29 C2 8A 1C E7 C3 B2 21; -E0D8: FE CA 20 11 E7 CD 1F 1C FD CB 37 FE FD CB 01 76 C2 8A 1C 18 0D CD 8D 2C; -E0F0: D2 AF 21 CD 1F 1C FD CB 37 BE CD 30 25 CA B2 21 CD BF 16 21 71 5C CB B6; -E108: CB EE 01 01 00 CB 7E 20 0B 3A 3B 5C E6 40 20 02 0E 03 B6 77 F7 36 0D 79; -E120: 0F 0F 30 05 3E 22 12 2B 77 22 5B 5C FD CB 37 7E 20 2C 2A 5D 5C E5 2A 3D; -E138: 5C E5 21 3A 21 E5 FD CB 30 66 28 04 ED 73 3D 5C 2A 61 5C CD A7 11 FD 36; -E150: 00 FF CD 2C 0F FD CB 01 BE CD B9 21 18 03 CD 2C 0F FD 36 22 00 CD D6 21; -E168: 20 0A CD 1D 11 ED 4B 82 5C CD D9 0D 21 71 5C CB AE CB 7E CB BE 20 1C E1; -E180: E1 22 3D 5C E1 22 5F 5C FD CB 01 FE CD B9 21 2A 5F 5C FD 36 26 00 22 5D; -E198: 5C 18 17 2A 63 5C ED 5B 61 5C 37 ED 52 44 4D CD B2 2A CD FF 2A 18 03 CD; -E1B0: FC 1F CD 4E 20 CA C1 20 C9 2A 61 5C 22 5D 5C DF FE E2 28 0C 3A 71 5C CD; -E1C8: 59 1C DF FE 0D C8 CF 0B CD 30 25 C8 CF 10 2A 51 5C 23 23 23 23 7E FE 4B; -E1E0: C9 E7 CD F2 21 D8 DF FE 2C 28 F6 FE 3B 28 F2 C3 8A 1C FE D9 D8 FE DF 3F; -E1F8: D8 F5 E7 F1 D6 C9 F5 CD 82 1C F1 A7 CD C3 1F F5 CD 94 1E 57 F1 D7 7A D7; -E210: C9 D6 11 CE 00 28 1D D6 02 CE 00 28 56 FE 01 7A 06 01 20 04 07 07 06 04; -E228: 4F 7A FE 02 30 16 79 21 91 5C 18 38 7A 06 07 38 05 07 07 07 06 38 4F 7A; -E240: FE 0A 38 02 CF 13 21 8F 5C FE 08 38 0B 7E 28 07 B0 2F E6 24 28 01 78 4F; -E258: 79 CD 6C 22 3E 07 BA 9F CD 6C 22 07 07 E6 50 47 3E 08 BA 9F AE A0 AE 77; -E270: 23 78 C9 9F 7A 0F 06 80 20 03 0F 06 40 4F 7A FE 08 28 04 FE 02 30 BD 79; -E288: 21 8F 5C CD 6C 22 79 0F 0F 0F 18 D8 CD 94 1E FE 08 30 A9 D3 FE 07 07 07; -E2A0: CB 6F 20 02 EE 07 32 48 5C C9 3E AF 90 DA F9 24 47 A7 1F 37 1F A7 1F A8; -E2B8: E6 F8 A8 67 79 07 07 07 A8 E6 C7 A8 07 07 6F 79 E6 07 C9 CD 07 23 CD AA; -E2D0: 22 47 04 7E 07 10 FD E6 01 C3 28 2D CD 07 23 CD E5 22 C3 4D 0D ED 43 7D; -E2E8: 5C CD AA 22 47 04 3E FE 0F 10 FD 47 7E FD 4E 57 CB 41 20 01 A0 CB 51 20; -E300: 02 A8 2F 77 C3 DB 0B CD 14 23 47 C5 CD 14 23 59 C1 51 4F C9 CD D5 2D DA; -E318: F9 24 0E 01 C8 0E FF C9 DF FE 2C C2 8A 1C E7 CD 82 1C CD EE 1B EF 2A 3D; -E330: 38 7E FE 81 30 05 EF 02 38 18 A1 EF A3 38 36 83 EF C5 02 38 CD 7D 24 C5; -E348: EF 31 E1 04 38 7E FE 80 30 08 EF 02 02 38 C1 C3 DC 22 EF C2 01 C0 02 03; -E360: 01 E0 0F C0 01 31 E0 01 31 E0 A0 C1 02 38 FD 34 62 CD 94 1E 6F E5 CD 94; -E378: 1E E1 67 22 7D 5C C1 C3 20 24 DF FE 2C 28 06 CD EE 1B C3 77 24 E7 CD 82; -E390: 1C CD EE 1B EF C5 A2 04 1F 31 30 30 00 06 02 38 C3 77 24 C0 02 C1 02 31; -E3A8: 2A E1 01 E1 2A 0F E0 05 2A E0 01 3D 38 7E FE 81 30 07 EF 02 02 38 C3 77; -E3C0: 24 CD 7D 24 C5 EF 02 E1 01 05 C1 02 01 31 E1 04 C2 02 01 31 E1 04 E2 E5; -E3D8: E0 03 A2 04 31 1F C5 02 20 C0 02 C2 02 C1 E5 04 E0 E2 04 0F E1 01 C1 02; -E3F0: E0 04 E2 E5 04 03 C2 2A E1 2A 0F 02 38 1A FE 81 C1 DA 77 24 C5 EF 01 38; -E408: 3A 7D 5C CD 28 2D EF C0 0F 01 38 3A 7E 5C CD 28 2D EF C5 0F E0 E5 38 C1; -E420: 05 28 3C 18 14 EF E1 31 E3 04 E2 E4 04 03 C1 02 E4 04 E2 E3 04 0F C2 02; -E438: 38 C5 EF C0 02 E1 0F 31 38 3A 7D 5C CD 28 2D EF 03 E0 E2 0F C0 01 E0 38; -E450: 3A 7E 5C CD 28 2D EF 03 38 CD B7 24 C1 10 C6 EF 02 02 01 38 3A 7D 5C CD; -E468: 28 2D EF 03 01 38 3A 7E 5C CD 28 2D EF 03 38 CD B7 24 C3 4D 0D EF 31 28; -E480: 34 32 00 01 05 E5 01 05 2A 38 CD D5 2D 38 06 E6 FC C6 04 30 02 3E FC F5; -E498: CD 28 2D EF E5 01 05 31 1F C4 02 31 A2 04 1F C1 01 C0 02 31 04 31 0F A1; -E4B0: 03 1B C3 02 38 C1 C9 CD 07 23 79 B8 30 06 69 D5 AF 5F 18 07 B1 C8 68 41; -E4C8: D5 16 00 60 78 1F 85 38 03 BC 38 07 94 4F D9 C1 C5 18 04 4F D5 D9 C1 2A; -E4E0: 7D 5C 78 84 47 79 3C 85 38 0D 28 0D 3D 4F CD E5 22 D9 79 10 D9 D1 C9 28; -E4F8: F3 CF 0A DF 06 00 C5 4F 21 96 25 CD DC 16 79 D2 84 26 06 00 4E 09 E9 CD; -E510: 74 00 03 FE 0D CA 8A 1C FE 22 20 F3 CD 74 00 FE 22 C9 E7 FE 28 20 06 CD; -E528: 79 1C DF FE 29 C2 8A 1C FD CB 01 7E C9 CD 07 23 2A 36 5C 11 00 01 19 79; -E540: 0F 0F 0F E6 E0 A8 5F 79 E6 18 EE 40 57 06 60 C5 D5 E5 1A AE 28 04 3C 20; -E558: 1A 3D 4F 06 07 14 23 1A AE A9 20 0F 10 F7 C1 C1 C1 3E 80 90 01 01 00 F7; -E570: 12 18 0A E1 11 08 00 19 D1 C1 10 D3 48 C3 B2 2A CD 07 23 79 0F 0F 0F 4F; -E588: E6 E0 A8 6F 79 E6 03 EE 58 67 7E C3 28 2D 22 1C 28 4F 2E F2 2B 12 A8 56; -E5A0: A5 57 A7 84 A6 8F C4 E6 AA BF AB C7 A9 CE 00 E7 C3 FF 24 DF 23 E5 01 00; -E5B8: 00 CD 0F 25 20 1B CD 0F 25 28 FB CD 30 25 28 11 F7 E1 D5 7E 23 12 13 FE; -E5D0: 22 20 F8 7E 23 FE 22 28 F2 0B D1 21 3B 5C CB B6 CB 7E C4 B2 2A C3 12 27; -E5E8: E7 CD FB 24 FE 29 C2 8A 1C E7 C3 12 27 C3 BD 27 CD 30 25 28 28 ED 4B 76; -E600: 5C CD 2B 2D EF A1 0F 34 37 16 04 34 80 41 00 00 80 32 02 A1 03 31 38 CD; -E618: A2 2D ED 43 76 5C 7E A7 28 03 D6 10 77 18 09 CD 30 25 28 04 EF A3 38 34; -E630: E7 C3 C3 26 01 5A 10 E7 FE 23 CA 0D 27 21 3B 5C CB B6 CB 7E 28 1F C3 6C; -E648: 3B 0E 00 20 13 CD 1E 03 30 0E 15 5F CD 33 03 F5 01 01 00 F7 F1 12 0E 01; -E660: 06 00 CD B2 2A C3 12 27 CD 22 25 C4 35 25 E7 C3 DB 25 CD 22 25 C4 80 25; -E678: E7 18 48 CD 22 25 C4 CB 22 E7 18 3F CD 88 2C 30 56 FE 41 30 3C CD 30 25; -E690: 20 23 CD 9B 2C DF 01 06 00 CD 55 16 23 36 0E 23 EB 2A 65 5C 0E 05 A7 ED; -E6A8: 42 22 65 5C ED B0 EB 2B CD 77 00 18 0E DF 23 7E FE 0E 20 FA 23 CD B4 33; -E6C0: 22 5D 5C FD CB 01 F6 18 14 CD B2 28 DA 2E 1C CC 96 29 3A 3B 5C FE C0 38; -E6D8: 04 23 CD B4 33 18 33 01 DB 09 FE 2D 28 27 01 18 10 FE AE 28 20 D6 AF DA; -E6F0: 8A 1C 01 F0 04 FE 14 28 14 D2 8A 1C 06 10 C6 DC; -E700: 4F FE DF 30 02 CB B1 FE EE 38 02 CB B9 C5 E7 C3 FF 24 DF FE 28 20 0C FD; -E718: CB 01 76 20 17 CD 52 2A E7 18 F0 06 00 4F 21 95 27 CD DC 16 30 06 4E 21; -E730: ED 26 09 46 D1 7A B8 38 3A A7 CA 18 00 C5 21 3B 5C 7B FE ED 20 06 CB 76; -E748: 20 02 1E 99 D5 CD 30 25 28 09 7B E6 3F 47 EF 3B 38 18 09 7B FD AE 01 E6; -E760: 40 C2 8A 1C D1 21 3B 5C CB F6 CB 7B 20 02 CB B6 C1 18 C1 D5 79 FD CB 01; -E778: 76 20 15 E6 3F C6 08 4F FE 10 20 04 CB F1 18 08 38 D7 FE 17 28 02 CB F9; -E790: C5 E7 C3 FF 24 2B CF 2D C3 2A C4 2F C5 5E C6 3D CE 3E CC 3C CD C7 C9 C8; -E7A8: CA C9 CB C5 C7 C6 C8 00 06 08 08 0A 02 03 05 05 05 05 05 05 06 CD 30 25; -E7C0: 20 35 E7 CD 8D 2C D2 8A 1C E7 FE 24 F5 20 01 E7 FE 28 20 12 E7 FE 29 28; -E7D8: 10 CD FB 24 DF FE 2C 20 03 E7 18 F5 FE 29 C2 8A 1C E7 21 3B 5C CB B6 F1; -E7F0: 28 02 CB F6 C3 12 27 E7 E6 DF 47 E7 D6 24 4F 20 01 E7 E7 E5 2A 53 5C 2B; -E808: 11 CE 00 C5 CD 86 1D C1 30 02 CF 18 E5 CD AB 28 E6 DF B8 20 08 CD AB 28; -E820: D6 24 B9 28 0C E1 2B 11 00 02 C5 CD 8B 19 C1 18 D7 A7 CC AB 28 D1 D1 ED; -E838: 53 5D 5C CD AB 28 E5 FE 29 28 42 23 7E FE 0E 16 40 28 07 2B CD AB 28 23; -E850: 16 00 23 E5 D5 CD FB 24 F1 FD AE 01 E6 40 20 2B E1 EB 2A 65 5C 01 05 00; -E868: ED 42 22 65 5C ED B0 EB 2B CD AB 28 FE 29 28 0D E5 DF FE 2C 20 0D E7 E1; -E880: CD AB 28 18 BE E5 DF FE 29 28 02 CF 19 D1 EB 22 5D 5C 2A 0B 5C E3 22 0B; -E898: 5C D5 E7 E7 CD FB 24 E1 22 5D 5C E1 22 0B 5C E7 C3 12 27 23 7E FE 21 38; -E8B0: FA C9 FD CB 01 F6 DF CD 8D 2C D2 8A 1C E5 E6 1F 4F E7 E5 FE 28 28 28 CB; -E8C8: F1 FE 24 28 11 CB E9 CD 88 2C 30 0F CD 88 2C 30 16 CB B1 E7 18 F6 E7 FD; -E8E0: CB 01 B6 3A 0C 5C A7 28 06 CD 30 25 C2 51 29 41 CD 30 25 20 08 79 E6 E0; -E8F8: CB FF 4F 18 37 2A 4B 5C 7E E6 7F 28 2D B9 20 22 17 87 F2 3F 29 38 30 D1; -E910: D5 E5 23 1A 13 FE 20 28 FA F6 20 BE 28 F4 F6 80 BE 20 06 1A CD 88 2C 30; -E928: 15 E1 C5 CD B8 19 EB C1 18 CE CB F8 D1 DF FE 28 28 09 CB E8 18 0D D1 D1; -E940: D1 E5 DF CD 88 2C 30 03 E7 18 F8 E1 CB 10 CB 70 C9 2A 0B 5C 7E FE 29 CA; -E958: EF 28 7E F6 60 47 23 7E FE 0E 28 07 2B CD AB 28 23 CB A8 78 B9 28 12 23; -E970: 23 23 23 23 CD AB 28 FE 29 CA EF 28 CD AB 28 18 D9 CB 69 20 0C 23 ED 5B; -E988: 65 5C CD C0 33 EB 22 65 5C D1 D1 AF 3C C9 AF 47 CB 79 20 4B CB 7E 20 0E; -E9A0: 3C 23 4E 23 46 23 EB CD B2 2A DF C3 49 2A 23 23 23 46 CB 71 28 0A 05 28; -E9B8: E8 EB DF FE 28 20 61 EB EB 18 24 E5 DF E1 FE 2C 28 20 CB 79 28 52 CB 71; -E9D0: 20 06 FE 29 20 3C E7 C9 FE 29 28 6C FE CC 20 32 DF 2B 22 5D 5C 18 5E 21; -E9E8: 00 00 E5 E7 E1 79 FE C0 20 09 DF FE 29 28 51 FE CC 28 E5 C5 E5 CD EE 2A; -EA00: E3 EB CD CC 2A 38 19 0B CD F4 2A 09 D1 C1 10 B3 CB 79 20 66 E5 CB 71 20; -EA18: 13 42 4B DF FE 29 28 02 CF 02 E7 E1 11 05 00 CD F4 2A 09 C9 CD EE 2A E3; -EA30: CD F4 2A C1 09 23 42 4B EB CD B1 2A DF FE 29 28 07 FE 2C 20 DB CD 52 2A; -EA48: E7 FE 28 28 F8 FD CB 01 B6 C9 CD 30 25 C4 F1 2B E7 FE 29 28 50 D5 AF F5; -EA60: C5 11 01 00 DF E1 FE CC 28 17 F1 CD CD 2A F5 50 59 E5 DF E1 FE CC 28 09; -EA78: FE 29 C2 8A 1C 62 6B 18 13 E5 E7 E1 FE 29 28 0C F1 CD CD 2A F5 DF 60 69; -EA90: FE 29 20 E6 F1 E3 19 2B E3 A7 ED 52 01 00 00 38 07 23 A7 FA 20 2A 44 4D; -EAA8: D1 FD CB 01 B6 CD 30 25 C8 AF FD CB 01 B6 C5 CD A9 33 C1 2A 65 5C 77 23; -EAC0: 73 23 72 23 71 23 70 23 22 65 5C C9 AF D5 E5 F5 CD 82 1C F1 CD 30 25 28; -EAD8: 12 F5 CD 99 1E D1 78 B1 37 28 05 E1 E5 A7 ED 42 7A DE 00 E1 D1 C9 EB 23; -EAF0: 5E 23 56 C9 CD 30 25 C8 CD A9 30 DA 15 1F C9 2A 4D 5C FD CB 37 4E 28 5E; -EB08: 01 05 00 03 23 7E FE 20 28 FA 30 0B FE 10 38 11 FE 16 30 0D 23 18 ED CD; -EB20: 88 2C 38 E7 FE 24 CA C0 2B 79 2A 59 5C 2B CD 55 16 23 23 EB D5 2A 4D 5C; -EB38: 1B D6 06 47 28 11 23 7E FE 21 38 FA F6 20 13 12 10 F4 F6 80 12 3E C0 2A; -EB50: 4D 5C AE F6 20 E1 CD EA 2B E5 EF 02 38 E1 01 05 00 A7 ED 42 18 40 FD CB; -EB68: 01 76 28 06 11 06 00 19 18 E7 2A 4D 5C ED 4B 72 5C FD CB 37 46 20 30 78; -EB80: B1 C8 E5 F7 D5 C5 54 5D 23 36 20 ED B8 E5 CD F1 2B E1 E3 A7 ED 42 09 30; -EB98: 02 44 4D E3 EB 78 B1 28 02 ED B0 C1 D1 E1 EB 78 B1 C8 D5 ED B0 E1 C9 2B; -EBB0: 2B 2B 7E E5 C5 CD C6 2B C1 E1 03 03 03 C3 E8 19 3E DF 2A 4D 5C A6 F5 CD; -EBC8: F1 2B EB 09 C5 2B 22 4D 5C 03 03 03 2A 59 5C 2B CD 55 16 2A 4D 5C C1 C5; -EBE0: 03 ED B8 EB 23 C1 70 2B 71 F1 2B 77 2A 59 5C 2B C9 2A 65 5C 2B 46 2B 4E; -EBF8: 2B 56 2B 5E 2B 7E 22 65 5C C9 CD B2 28 C2 8A 1C CD 30 25 20 08 CB B1 CD; -EC10: 96 29 CD EE 1B 38 08 C5 CD B8 19 CD E8 19 C1 CB F9 06 00 C5 21 01 00 CB; -EC28: 71 20 02 2E 05 EB E7 26 FF CD CC 2A DA 20 2A E1 C5 24 E5 60 69 CD F4 2A; -EC40: EB DF FE 2C 28 E8 FE 29 20 BB E7 C1 79 68 26 00 23 23 29 19 DA 15 1F D5; -EC58: C5 E5 44 4D 2A 59 5C 2B CD 55 16 23 77 C1 0B 0B 0B 23 71 23 70 C1 78 23; -EC70: 77 62 6B 1B 36 00 CB 71 28 02 36 20 C1 ED B8 C1 70 2B 71 2B 3D 20 F8 C9; -EC88: CD 1B 2D 3F D8 FE 41 3F D0 FE 5B D8 FE 61 3F D0 FE 7B C9 FE C4 20 19 11; -ECA0: 00 00 E7 D6 31 CE 00 20 0A EB 3F ED 6A DA AD 31 EB 18 EF 42 4B C3 2B 2D; -ECB8: FE 2E 28 0F CD 3B 2D FE 2E 20 28 E7 CD 1B 2D 38 22 18 0A E7 CD 1B 2D DA; -ECD0: 8A 1C EF A0 38 EF A1 C0 02 38 DF CD 22 2D 38 0B EF E0 A4 05 C0 04 0F 38; -ECE8: E7 18 EF FE 45 28 03 FE 65 C0 06 FF E7 FE 2B 28 05 FE 2D 20 02 04 E7 CD; -ED00: 1B 2D 38 CB C5 CD 3B 2D CD D5 2D C1 DA AD 31 A7 FA AD 31 04 28 02 ED 44; -ED18: C3 4F 2D FE 30 D8 FE 3A 3F C9 CD 1B 2D D8 D6 30 4F 06 00 FD 21 3A 5C AF; -ED30: 5F 51 48 47 CD B6 2A EF 38 A7 C9 F5 EF A0 38 F1 CD 22 2D D8 EF 01 A4 04; -ED48: 0F 38 CD 74 00 18 F1 07 0F 30 02 2F 3C F5 21 92 5C CD 0B 35 EF A4 38 F1; -ED60: CB 3F 30 0D F5 EF C1 E0 00 04 04 33 02 05 E1 38 F1 28 08 F5 EF 31 04 38; -ED78: F1 18 E5 EF 02 38 C9 23 4E 23 7E A9 91 5F 23 7E 89 A9 57 C9 0E 00 E5 36; -ED90: 00 23 71 23 7B A9 91 77 23 7A 89 A9 77 23 36 00 E1 C9 EF 38 7E A7 28 05; -EDA8: EF A2 0F 27 38 EF 02 38 E5 D5 EB 46 CD 7F 2D AF 90 CB 79 42 4B 7B D1 E1; -EDC0: C9 57 17 9F 5F 4F AF 47 CD B6 2A EF 34 EF 1A 20 9A 85 04 27 38 CD A2 2D; -EDD8: D8 F5 05 04 28 03 F1 37 C9 F1 C9 EF 31 36 00 0B 31 37 00 0D 02 38 3E 30; -EDF0: D7 C9 2A 38 3E 2D D7 EF A0 C3 C4 C5 02 38 D9 E5; -EE00: D9 EF 31 27 C2 03 E2 01 C2 02 38 7E A7 20 47 CD 7F 2D 06 10 7A A7 20 06; -EE18: B3 28 09 53 06 08 D5 D9 D1 D9 18 57 EF E2 38 7E D6 7E CD C1 2D 57 3A AC; -EE30: 5C 92 32 AC 5C 7A CD 4F 2D EF 31 27 C1 03 E1 38 CD D5 2D E5 32 A1 5C 3D; -EE48: 17 9F 3C 21 AB 5C 77 23 86 77 E1 C3 CF 2E D6 80 FE 1C 38 13 CD C1 2D D6; -EE60: 07 47 21 AC 5C 86 77 78 ED 44 CD 4F 2D 18 92 EB CD BA 2F D9 CB FA 7D D9; -EE78: D6 80 47 CB 23 CB 12 D9 CB 13 CB 12 D9 21 AA 5C 0E 05 7E 8F 27 77 2B 0D; -EE90: 20 F8 10 E7 AF 21 A6 5C 11 A1 5C 06 09 ED 6F 0E FF ED 6F 20 04 0D 0C 20; -EEA8: 0A 12 13 FD 34 71 FD 34 72 0E 00 CB 40 28 01 23 10 E7 3A AB 5C D6 09 38; -EEC0: 0A FD 35 71 3E 04 FD BE 6F 18 41 EF 02 E2 38 EB CD BA 2F D9 3E 80 95 2E; -EED8: 00 CB FA D9 CD DD 2F FD 7E 71 FE 08 38 06 D9 CB 12 D9 18 20 01 00 02 7B; -EEF0: CD 8B 2F 5F 7A CD 8B 2F 57 C5 D9 C1 10 F1 21 A1 5C 79 FD 4E 71 09 77 FD; -EF08: 34 71 18 D3 F5 21 A1 5C FD 4E 71 06 00 09 41 F1 2B 7E CE 00 77 A7 28 05; -EF20: FE 0A 3F 30 08 10 F1 36 01 04 FD 34 72 FD 70 71 EF 02 38 D9 E1 D9 ED 4B; -EF38: AB 5C 21 A1 5C 78 FE 09 38 04 FE FC 38 26 A7 CC EF 15 AF 90 FA 52 2F 47; -EF50: 18 0C 79 A7 28 03 7E 23 0D CD EF 15 10 F4 79 A7 C8 04 3E 2E D7 3E 30 10; -EF68: FB 41 18 E6 50 15 06 01 CD 4A 2F 3E 45 D7 4A 79 A7 F2 83 2F ED 44 4F 3E; -EF80: 2D 18 02 3E 2B D7 06 00 C3 1B 1A D5 6F 26 00 5D 54 29 29 19 29 59 19 4C; -EF98: 7D D1 C9 7E 36 00 A7 C8 23 CB 7E CB FE 2B C8 C5 01 05 00 09 41 4F 37 2B; -EFB0: 7E 2F CE 00 77 10 F8 79 C1 C9 E5 F5 4E 23 46 77 23 79 4E C5 23 4E 23 46; -EFC8: EB 57 5E D5 23 56 23 5E D5 D9 D1 E1 C1 D9 23 56 23 5E F1 E1 C9 A7 C8 FE; -EFE0: 21 30 16 C5 47 D9 CB 2D CB 1A CB 1B D9 CB 1A CB 1B 10 F2 C1 D0 CD 04 30; -EFF8: C0 D9 AF 2E 00 57 5D D9 11 00 00 C9 1C C0 14 C0 D9 1C 20 01 14 D9 C9 EB; -F010: CD 6E 34 EB 1A B6 20 26 D5 23 E5 23 5E 23 56 23 23 23 7E 23 4E 23 46 E1; -F028: EB 09 EB 8E 0F CE 00 20 0B 9F 77 23 73 23 72 2B 2B 2B D1 C9 2B D1 CD 93; -F040: 32 D9 E5 D9 D5 E5 CD 9B 2F 47 EB CD 9B 2F 4F B8 30 03 78 41 EB F5 90 CD; -F058: BA 2F CD DD 2F F1 E1 77 E5 68 61 19 D9 EB ED 4A EB 7C 8D 6F 1F AD D9 EB; -F070: E1 1F 30 08 3E 01 CD DD 2F 34 28 23 D9 7D E6 80 D9 23 77 2B 28 1F 7B ED; -F088: 44 3F 5F 7A 2F CE 00 57 D9 7B 2F CE 00 5F 7A 2F CE 00 30 07 1F D9 34 CA; -F0A0: AD 31 D9 57 D9 AF C3 55 31 C5 06 10 7C 4D 21 00 00 29 38 0A CB 11 17 30; -F0B8: 03 19 38 02 10 F3 C1 C9 CD E9 34 D8 23 AE CB FE 2B C9 1A B6 20 22 D5 E5; -F0D0: D5 CD 7F 2D EB E3 41 CD 7F 2D 78 A9 4F E1 CD A9 30 EB E1 38 0A 7A B3 20; -F0E8: 01 4F CD 8E 2D D1 C9 D1 CD 93 32 AF CD C0 30 D8 D9 E5 D9 D5 EB CD C0 30; -F100: EB 38 5A E5 CD BA 2F 78 A7 ED 62 D9 E5 ED 62 D9 06 21 18 11 30 05 19 D9; -F118: ED 5A D9 D9 CB 1C CB 1D D9 CB 1C CB 1D D9 CB 18 CB 19 D9 CB 19 1F 10 E4; -F130: EB D9 EB D9 C1 E1 78 81 20 01 A7 3D 3F 17 3F 1F F2 46 31 30 68 A7 3C 20; -F148: 08 38 06 D9 CB 7A D9 20 5C 77 D9 78 D9 30 15 7E A7 3E 80 28 01 AF D9 A2; -F160: CD FB 2F 07 77 38 2E 23 77 2B 18 29 06 20 D9 CB 7A D9 20 12 07 CB 13 CB; -F178: 12 D9 CB 13 CB 12 D9 35 28 D7 10 EA 18 D7 17 30 0C CD 04 30 20 07 D9 16; -F190: 80 D9 34 28 18 E5 23 D9 D5 D9 C1 78 17 CB 16 1F 77 23 71 23 72 23 73 E1; -F1A8: D1 D9 E1 D9 C9 CF 05 CD 93 32 EB AF CD C0 30 38 F4 EB CD C0 30 D8 D9 E5; -F1C0: D9 D5 E5 CD BA 2F D9 E5 60 69 D9 61 68 AF 06 DF 18 10 17 CB 11 D9 CB 11; -F1D8: CB 10 D9 29 D9 ED 6A D9 38 10 ED 52 D9 ED 52 D9 30 0F 19 D9 ED 5A D9 A7; -F1F0: 18 08 A7 ED 52 D9 ED 52 D9 37 04 FA D2 31 F5 28 E1 5F 51 D9 59 50 F1 CB; -F208: 18 F1 CB 18 D9 C1 E1 78 91 C3 3D 31 7E A7 C8 FE 81 30 06 36 00 3E 20 18; -F220: 51 FE 91 20 1A 23 23 23 3E 80 A6 2B B6 2B 20 03 3E 80 AE 2B 20 36 77 23; -F238: 36 FF 2B 3E 18 18 33 30 2C D5 2F C6 91 23 56 23 5E 2B 2B 0E 00 CB 7A 28; -F250: 01 0D CB FA 06 08 90 80 38 04 5A 16 00 90 28 07 47 CB 3A CB 1B 10 FA CD; -F268: 8E 2D D1 C9 7E D6 A0 F0 ED 44 D5 EB 2B 47 CB 38 CB 38 CB 38 28 05 36 00; -F280: 2B 10 FB E6 07 28 09 47 3E FF CB 27 10 FC A6 77 EB D1 C9 CD 96 32 EB 7E; -F298: A7 C0 D5 CD 7F 2D AF 23 77 2B 77 06 91 7A A7 20 08 B3 42 28 10 53 58 06; -F2B0: 89 EB 05 29 30 FC CB 09 CB 1C CB 1D EB 2B 73 2B 72 2B 70 D1 C9 00 B0 00; -F2C8: 40 B0 00 01 30 00 F1 49 0F DA A2 40 B0 00 0A 8F 36 3C 34 A1 33 0F 30 CA; -F2E0: 30 AF 31 51 38 1B 35 24 35 3B 35 3B 35 3B 35 3B 35 3B 35 3B 35 14 30 2D; -F2F8: 35 3B 35 3B 35 3B 35 3B 35 3B 35 3B 35 9C 35 DE 35 BC 34 45 36 6E 34 69; -F310: 36 DE 35 74 36 B5 37 AA 37 DA 37 33 38 43 38 E2 37 13 37 C4 36 AF 36 4A; -F328: 38 92 34 6A 34 AC 34 A5 34 B3 34 1F 36 C9 35 01 35 C0 33 A0 36 86 36 C6; -F340: 33 7A 36 06 35 F9 34 9B 36 83 37 14 32 A2 33 4F 2D 97 32 49 34 1B 34 2D; -F358: 34 0F 34 CD BF 35 78 32 67 5C D9 E3 D9 ED 53 65 5C D9 7E 23 E5 A7 F2 80; -F370: 33 57 E6 60 0F 0F 0F 0F C6 7C 6F 7A E6 1F 18 0E FE 18 30 08 D9 01 FB FF; -F388: 54 5D 09 D9 07 6F 11 D7 32 26 00 19 5E 23 56 21 65 33 E3 D5 D9 ED 4B 66; -F3A0: 5C C9 F1 3A 67 5C D9 18 C3 D5 E5 01 05 00 CD 05 1F E1 D1 C9 ED 5B 65 5C; -F3B8: CD C0 33 ED 53 65 5C C9 CD A9 33 ED B0 C9 62 6B CD A9 33 D9 E5 D9 E3 C5; -F3D0: 7E E6 C0 07 07 4F 0C 7E E6 3F 20 02 23 7E C6 50 12 3E 05 91 23 13 06 00; -F3E8: ED B0 C1 E3 D9 E1 D9 47 AF 05 C8 12 13 18 FA A7 C8 F5 D5 11 00 00 CD C8; -F400: 33 D1 F1 3D 18 F2 4F 07 07 81 4F 06 00 09 C9 D5 2A 68 5C CD 06 34 CD C0; -F418: 33 E1 C9 62 6B D9 E5 21 C5 32 D9 CD F7 33 CD C8 33 D9 E1 D9 C9 E5 EB 2A; -F430: 68 5C CD 06 34 EB CD C0 33 EB E1 C9 06 05 1A 4E EB 12 71 23 13 10 F7 EB; -F448: C9 47 CD 5E 33 31 0F C0 02 A0 C2 31 E0 04 E2 C1 03 38 CD C6 33 CD 62 33; -F460: 0F 01 C2 02 35 EE E1 03 38 C9 06 FF 18 06 CD E9 34 D8 06 00 7E A7 28 0B; -F478: 23 78 E6 80 B6 17 3F 1F 77 2B C9 D5 E5 CD 7F 2D E1 78 B1 2F 4F CD 8E 2D; -F490: D1 C9 CD E9 34 D8 D5 11 01 00 23 CB 16 2B 9F 4F CD 8E 2D D1 C9 CD 99 1E; -F4A8: ED 78 18 04 CD 99 1E 0A C3 28 2D CD 99 1E 21 2B 2D E5 C5 C9 CD F1 2B 0B; -F4C0: 78 B1 20 23 1A CD 8D 2C 38 09 D6 90 38 19 FE 15 30 15 3C 3D 87 87 87 FE; -F4D8: A8 30 0C ED 4B 7B 5C 81 4F 30 01 04 C3 2B 2D CF 09 E5 C5 47 7E 23 B6 23; -F4F0: B6 23 B6 78 C1 E1 C0 37 C9 CD E9 34 D8 3E FF 18; -F500: 06 CD E9 34 18 05 AF 23 AE 2B 07 E5 3E 00 77 23 77 23 17 77 1F 23 77 23; -F518: 77 E1 C9 EB CD E9 34 EB D8 37 18 E7 EB CD E9 34 EB D0 A7 18 DE EB CD E9; -F530: 34 EB D0 D5 1B AF 12 1B 12 D1 C9 78 D6 08 CB 57 20 01 3D 0F 30 08 F5 E5; -F548: CD 3C 34 D1 EB F1 CB 57 20 07 0F F5 CD 0F 30 18 33 0F F5 CD F1 2B D5 C5; -F560: CD F1 2B E1 7C B5 E3 78 20 0B B1 C1 28 04 F1 3F 18 16 F1 18 13 B1 28 0D; -F578: 1A 96 38 09 20 ED 0B 13 23 E3 2B 18 DF C1 F1 A7 F5 EF A0 38 F1 F5 DC 01; -F590: 35 F1 F5 D4 F9 34 F1 0F D4 01 35 C9 CD F1 2B D5 C5 CD F1 2B E1 E5 D5 C5; -F5A8: 09 44 4D F7 CD B2 2A C1 E1 78 B1 28 02 ED B0 C1 E1 78 B1 28 02 ED B0 2A; -F5C0: 65 5C 11 FB FF E5 19 D1 C9 CD D5 2D 38 0E 20 0C F5 01 01 00 F7 F1 12 CD; -F5D8: B2 2A EB C9 CF 0A 2A 5D 5C E5 78 C6 E3 9F F5 CD F1 2B D5 03 F7 E1 ED 53; -F5F0: 5D 5C D5 ED B0 EB 2B 36 0D FD CB 01 BE CD FB 24 DF FE 0D 20 07 E1 F1 FD; -F608: AE 01 E6 40 C2 8A 1C 22 5D 5C FD CB 01 FE CD FB 24 E1 22 5D 5C 18 A0 01; -F620: 01 00 F7 22 5B 5C E5 2A 51 5C E5 3E FF CD 01 16 CD E3 2D E1 CD 15 16 D1; -F638: 2A 5B 5C A7 ED 52 44 4D CD B2 2A EB C9 CD 94 1E FE 10 D2 9F 1E 2A 51 5C; -F650: E5 CD 01 16 CD E6 15 01 00 00 30 03 0C F7 12 CD B2 2A E1 CD 15 16 C3 BF; -F668: 35 CD F1 2B 78 B1 28 01 1A C3 28 2D CD F1 2B C3 2B 2D D9 E5 21 67 5C 35; -F680: E1 20 04 23 D9 C9 D9 5E 7B 17 9F 57 19 D9 C9 13 13 1A 1B 1B A7 20 EF D9; -F698: 23 D9 C9 F1 D9 E3 D9 C9 EF C0 02 31 E0 05 27 E0 01 C0 04 03 E0 38 C9 EF; -F6B0: 31 36 00 04 3A 38 C9 31 3A C0 03 E0 01 30 00 03 A1 03 38 C9 EF 3D 34 F1; -F6C8: 38 AA 3B 29 04 31 27 C3 03 31 0F A1 03 88 13 36 58 65 66 9D 78 65 40 A2; -F6E0: 60 32 C9 E7 21 F7 AF 24 EB 2F B0 B0 14 EE 7E BB 94 58 F1 3A 7E F8 CF E3; -F6F8: 38 CD D5 2D 20 07 38 03 86 30 09 CF 05 38 07 96 30 04 ED 44 77 C9 EF 02; -F710: A0 38 C9 EF 3D 31 37 00 04 38 CF 09 A0 02 38 7E 36 80 CD 28 2D EF 34 38; -F728: 00 03 01 31 34 F0 4C CC CC CD 03 37 00 08 01 A1 03 01 38 34 EF 01 34 F0; -F740: 31 72 17 F8 04 01 A2 03 A2 03 31 34 32 20 04 A2 03 8C 11 AC 14 09 56 DA; -F758: A5 59 30 C5 5C 90 AA 9E 70 6F 61 A1 CB DA 96 A4 31 9F B4 E7 A0 FE 5C FC; -F770: EA 1B 43 CA 36 ED A7 9C 7E 5E F0 6E 23 80 93 04 0F 38 C9 EF 3D 34 EE 22; -F788: F9 83 6E 04 31 A2 0F 27 03 31 0F 31 0F 31 2A A1 03 31 37 C0 00 04 02 38; -F7A0: C9 A1 03 01 36 00 02 1B 38 C9 EF 39 2A A1 03 E0 00 06 1B 33 03 EF 39 31; -F7B8: 31 04 31 0F A1 03 86 14 E6 5C 1F 0B A3 8F 38 EE E9 15 63 BB 23 EE 92 0D; -F7D0: CD ED F1 23 5D 1B EA 04 38 C9 EF 31 1F 01 20 05 38 C9 CD 97 32 7E FE 81; -F7E8: 38 0E EF A1 1B 01 05 31 36 A3 01 00 06 1B 33 03 EF A0 01 31 31 04 31 0F; -F800: A1 03 8C 10 B2 13 0E 55 E4 8D 58 39 BC 5B 98 FD 9E 00 36 75 A0 DB E8 B4; -F818: 63 42 C4 E6 B5 09 36 BE E9 36 73 1B 5D EC D8 DE 63 BE F0 61 A1 B3 0C 04; -F830: 0F 38 C9 EF 31 31 04 A1 03 1B 28 A1 0F 05 24 31 0F 38 C9 EF 22 A3 03 1B; -F848: 38 C9 EF 31 30 00 1E A2 38 EF 01 31 30 00 07 25 04 38 C3 C4 36 02 31 30; -F860: 00 09 A0 01 37 00 06 A1 01 05 02 A1 38 C9 DD E5 FD CB 01 66 28 03 CD 42; -F878: 3A CD BF 02 DD E1 C9 0E FD 16 FF 1E BF 42 3E 07 ED 79 ED 60 3E 0E ED 79; -F890: ED 78 F6 F0 6F C9 42 3E 0E ED 79 43 ED 69 C9 42 3E 0E ED 79 ED 78 C9 7D; -F8A8: E6 FE 6F 18 E9 7D F6 01 6F 18 E3 10 FE C9 C5 06 10 CD B3 38 C1 10 F7 C9; -F8C0: C5 CD 9F 38 C1 E6 20 28 02 10 F5 C9 C5 CD 9F 38 C1 E6 20 20 02 10 F5 C9; -F8D8: CD 7F 38 06 01 18 05 CD 7F 38 06 04 C5 CD 9F 38 C1 E6 20 28 40 AF C5 F5; -F8F0: CD AD 38 06 A3 CD C0 38 20 31 CD A7 38 18 02 FF FF 06 2B CD B3 38 CD 9F; -F908: 38 CB 6F 28 04 F1 37 18 03 F1 37 3F 1F F5 CD AD 38 06 26 CD B3 38 CD A7; -F920: 38 06 23 CD B3 38 F1 C1 10 C4 C9 F1 C1 CD AD 38 AF 32 88 5B 3C 37 3F C9; -F938: CD 7F 38 3A 88 5B E6 80 20 57 CD 9F 38 E6 20 28 E4 3A 88 5B A7 20 0B 3C; -F950: 32 88 5B 3E 4C 32 89 5B 18 42 3A 89 5B 3D 32 89 5B 20 39 AF 32 88 5B 32; -F968: 89 5B 32 8A 5B CD A7 38 06 21 CD C0 38 20 B6 CD AD 38 06 24 CD CC 38 28; -F980: AC CD A7 38 06 0F CD B6 38 CD DF 38 20 9F CB FF E6 F0 32 88 5B AF CB 3F; -F998: C9 AF 37 C9 AF 3C 37 C9 CD 38 39 3A 88 5B 2F E6 C0 C0 DD 21 8A 5B 06 05; -F9B0: C5 CD D8 38 C2 3A 3A CB 7F 28 21 CD DF 38 20 7A C1 C5 4F DD 7E 00 CB 40; -F9C8: 28 0C CB 39 CB 39 CB 39 CB 39 E6 F0 18 02 E6 0F B1 DD 77 00 C1 CB 40 20; -F9E0: 02 DD 2B 10 CB 1E 80 DD 21 88 5B 21 3F 3A 06 03 DD 7E 00 A6 28 21 CB 7B; -F9F8: 28 42 C5 F5 78 18 02 FF FF 3D CB 27 CB 27 CB 27 F6 07 47 F1 CB 27 DA 13; -FA10: 3A 10 F9 58 C1 20 25 DD 23 23 10 D4 CB 7B 20 07 7B E6 FC 28 02 1D 1D 3A; -FA28: 8A 5B E6 08 28 06 7B E6 7F C6 12 5F 7B C6 5A 5F AF C9 C1 C9 AF 3C C9 0F; -FA40: FF F2 1E 80 3A 78 5C E6 01 20 04 CD A0 39 C0 21 00 5C CB 7E 20 0C 7E FE; -FA58: 5B 38 07 23 35 2B 20 02 36 FF 7D 21 04 5C BD 20 E9 CD AE 3A C0 7B 21 00; -FA70: 5C BE 28 2A EB 21 04 5C BE 28 23 CB 7E 20 04 EB CB 7E C8 5F 77 23 36 0A; -FA88: 23 3A 09 5C CB 3F 77 23 CD D7 3A 73 7B 32 08 5C 21 3B 5C CB EE C9 23 36; -FAA0: 0A 23 35 C0 3A 0A 5C CB 3F 77 23 5E 18 E6 7B 21 66 5B CB 46 28 06 FE 6D; -FAB8: 30 1A AF C9 FE 80 30 14 FE 6C 20 F6 00 00 00 00 00 00 00 00 00 00 00 00; -FAD0: 00 00 00 00 AF 3C C9 E5 7B D6 5B 16 00 5F 21 66 5B CB 46 28 05 21 13 3B; -FAE8: 18 25 21 25 3B FE 11 38 1E 21 21 3B FE 15 28 17 FE 16 28 13 18 03 00 FF; -FB00: FF FE 17 28 0A 21 18 3B FE 21 30 03 21 13 3B 19 5E E1 C9 2E 0D 33 32 31; -FB18: 29 28 2A 2F 2D 39 38 37 2B 36 35 34 30 A5 0D A6 A7 A8 A9 AA 0B 0C 07 09; -FB30: 0A 08 AC AD AE AF B0 B1 B2 B3 B4 FD CB 01 66 20 05 AF 11 36 15 C9 21 0F; -FB48: 01 E3 C3 00 5B FD CB 01 66 20 05 FD CB 0A 7E C9 21 12 01 18 EC FD CB 01; -FB60: 66 20 04 DF FE 0D C9 21 15 01 18 DD CD 8E 02 0E 00 20 0D CD 1E 03 30 08; -FB78: 15 5F CD 33 03 C3 57 26 FD CB 01 66 CA 60 26 F3 CD A0 39 FB 20 0C CD AE; -FB90: 3A 20 07 CD D7 3A 7B C3 57 26 0E 00 C3 60 26 FE A3 28 0C FE A4 28 08 D6; -FBA8: A5 D2 5F 0B C3 56 0B FD CB 01 66 28 F2 11 C9 3B D5 D6 A3 11 D2 3B 28 03; -FBC0: 11 DA 3B 3E 04 F5 C3 17 0C 37 FD CB 01 4E C0 C3 03 0B 53 50 45 43 54 52; -FBD8: 55 CD 50 4C 41 D9 C3 01 3C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00; -FBF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 FF; -FC00: FF C3 A0 39 C3 10 3C C3 10 3C C3 10 3C C3 10 3C 3E 7F DB FE 1F D8 3E FE; -FC18: DB FE 1F D8 3E 07 D3 FE 3E 02 CD 01 16 AF 32 3C 5C 3E 16 D7 AF D7 AF D7; -FC30: 1E 08 43 50 78 3D CB 17 CB 17 CB 17 82 3D 32 8F 5C 21 8F 3C 4B 7E D7 23; -FC48: 0D 20 FA 10 E7 43 15 20 E3 21 00 48 54 5D 13 AF 77 01 FF 0F ED B0 EB 11; -FC60: 00 59 01 00 02 ED B0 F3 11 70 03 2E 07 01 99 00 0B 78 B1 20 FB 7D EE 10; -FC78: 6F D3 FE 1B 7A B3 20 ED 01 00 00 0B 78 B1 20 FB 0B 78 B1 20 FB 18 D9 13; -FC90: 00 31 39 13 01 38 36 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00; -FCA8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00; -FCC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00; -FCD8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00; -FCF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00; -FD08: 00 10 10 10 10 00 10 00 00 24 24 00 00 00 00 00 00 24 7E 24 24 7E 24 00; -FD20: 00 08 3E 28 3E 0A 3E 08 00 62 64 08 10 26 46 00 00 10 28 10 2A 44 3A 00; -FD38: 00 08 10 00 00 00 00 00 00 04 08 08 08 08 04 00 00 20 10 10 10 10 20 00; -FD50: 00 00 14 08 3E 08 14 00 00 00 08 08 3E 08 08 00 00 00 00 00 00 08 08 10; -FD68: 00 00 00 00 3E 00 00 00 00 00 00 00 00 18 18 00 00 00 02 04 08 10 20 00; -FD80: 00 3C 46 4A 52 62 3C 00 00 18 28 08 08 08 3E 00 00 3C 42 02 3C 40 7E 00; -FD98: 00 3C 42 0C 02 42 3C 00 00 08 18 28 48 7E 08 00 00 7E 40 7C 02 42 3C 00; -FDB0: 00 3C 40 7C 42 42 3C 00 00 7E 02 04 08 10 10 00 00 3C 42 3C 42 42 3C 00; -FDC8: 00 3C 42 42 3E 02 3C 00 00 00 00 10 00 00 10 00 00 00 10 00 00 10 10 20; -FDE0: 00 00 04 08 10 08 04 00 00 00 00 3E 00 3E 00 00 00 00 10 08 04 08 10 00; -FDF8: 00 3C 42 04 08 00 08 00 00 3C 4A 56 5E 40 3C 00 00 3C 42 42 7E 42 42 00; -FE10: 00 7C 42 7C 42 42 7C 00 00 3C 42 40 40 42 3C 00 00 78 44 42 42 44 78 00; -FE28: 00 7E 40 7C 40 40 7E 00 00 7E 40 7C 40 40 40 00 00 3C 42 40 4E 42 3C 00; -FE40: 00 42 42 7E 42 42 42 00 00 3E 08 08 08 08 3E 00 00 02 02 02 42 42 3C 00; -FE58: 00 44 48 70 48 44 42 00 00 40 40 40 40 40 7E 00 00 42 66 5A 42 42 42 00; -FE70: 00 42 62 52 4A 46 42 00 00 3C 42 42 42 42 3C 00 00 7C 42 42 7C 40 40 00; -FE88: 00 3C 42 42 52 4A 3C 00 00 7C 42 42 7C 44 42 00 00 3C 40 3C 02 42 3C 00; -FEA0: 00 FE 10 10 10 10 10 00 00 42 42 42 42 42 3C 00 00 42 42 42 42 24 18 00; -FEB8: 00 42 42 42 42 5A 24 00 00 42 24 18 18 24 42 00 00 82 44 28 10 10 10 00; -FED0: 00 7E 04 08 10 20 7E 00 00 0E 08 08 08 08 0E 00 00 00 40 20 10 08 04 00; -FEE8: 00 70 10 10 10 10 70 00 00 10 38 54 10 10 10 00 00 00 00 00 00 00 00 FF; -FF00: 00 1C 22 78 20 20 7E 00 00 00 38 04 3C 44 3C 00 00 20 20 3C 22 22 3C 00; -FF18: 00 00 1C 20 20 20 1C 00 00 04 04 3C 44 44 3C 00 00 00 38 44 78 40 3C 00; -FF30: 00 0C 10 18 10 10 10 00 00 00 3C 44 44 3C 04 38 00 40 40 78 44 44 44 00; -FF48: 00 10 00 30 10 10 38 00 00 04 00 04 04 04 24 18 00 20 28 30 30 28 24 00; -FF60: 00 10 10 10 10 10 0C 00 00 00 68 54 54 54 54 00 00 00 78 44 44 44 44 00; -FF78: 00 00 38 44 44 44 38 00 00 00 78 44 44 78 40 40 00 00 3C 44 44 3C 04 06; -FF90: 00 00 1C 20 20 20 20 00 00 00 38 40 38 04 78 00 00 10 38 10 10 10 0C 00; -FFA8: 00 00 44 44 44 44 38 00 00 00 44 44 28 28 10 00 00 00 44 54 54 54 28 00; -FFC0: 00 00 44 28 10 28 44 00 00 00 44 44 44 3C 04 38 00 00 7C 08 10 20 7C 00; -FFD8: 00 0E 08 30 08 08 0E 00 00 08 08 08 08 08 08 00 00 70 10 0C 10 10 70 00; -FFF0: 00 14 28 00 00 00 00 00 3C 42 99 A1 A1 99 42 3C; -END; diff --git a/rtl/tsconf.rom b/rtl/tsconf.rom new file mode 100644 index 0000000..410b1b7 Binary files /dev/null and b/rtl/tsconf.rom differ diff --git a/rtl/tsconf.v b/rtl/tsconf.v index ff931ce..996b99c 100644 --- a/rtl/tsconf.v +++ b/rtl/tsconf.v @@ -1,56 +1,56 @@ - -/* ----------------------------------------------------------------[02.11.2014] - u16-TSConf Version 0.2.9 - DEVBOARD ReVerSE-U16 By MVV - ---------------------------------------------------------------------------- - V0.1.0 27.07.2014 первая версия - V0.2.0 31.07.2014 добавлен транслятор PS/2, HDMI - V0.2.1 03.08.2014 добавлен Delta-Sigma DAC, I2C - V0.2.3 11.08.2014 добавлен enc424j600 - V0.2.4 24.08.2014 добавлена поддержка IDE Video DAC (zports.v, video_out.v) - V0.2.5 07.09.2014 добавлен порт #0001=key_scan, изменения в keyboard.vhd - V0.2.6 09.09.2014 исправлен вывод палитры в (lut.vhd) - V0.2.7 13.09.2014 дрожание мультиколора на tv80s, заменил на t80s - V0.2.8 19.10.2014 инвентирован CLK в модулях video_tmbuf, video_sfile и добавлены регистры на выходе - V0.2.9 02.11.2014 замена t80s, исправления в zint.v, zports.v, delta-sigma (приводит к намагничиванию динамиков) - WXEDA 10.03.2015 порт на девборду WXEDA - - http://tslabs.info/forum/viewtopic.php?f=31&t=401 - http://zx-pk.ru/showthread.php?t=23528 - - Copyright (c) 2014 MVV, TS-Labs, dsp, waybester, palsw - - All rights reserved - - Redistribution and use in source and synthezised forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - * Redistributions in synthesized form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - * Neither the name of the author nor the names of other contributors may - be used to endorse or promote products derived from this software without - specific prior written agreement from the author. - - * License is granted for non-commercial use only. A fee may not be charged - for redistributions as source code or in synthesized/hardware form without - specific prior written agreement from the author. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. + +/* ----------------------------------------------------------------[02.11.2014] + u16-TSConf Version 0.2.9 + DEVBOARD ReVerSE-U16 By MVV + ---------------------------------------------------------------------------- + V0.1.0 27.07.2014 первая версия + V0.2.0 31.07.2014 добавлен транслятор PS/2, HDMI + V0.2.1 03.08.2014 добавлен Delta-Sigma DAC, I2C + V0.2.3 11.08.2014 добавлен enc424j600 + V0.2.4 24.08.2014 добавлена поддержка IDE Video DAC (zports.v, video_out.v) + V0.2.5 07.09.2014 добавлен порт #0001=key_scan, изменения в keyboard.vhd + V0.2.6 09.09.2014 исправлен вывод палитры в (lut.vhd) + V0.2.7 13.09.2014 дрожание мультиколора на tv80s, заменил на t80s + V0.2.8 19.10.2014 инвентирован CLK в модулях video_tmbuf, video_sfile и добавлены регистры на выходе + V0.2.9 02.11.2014 замена t80s, исправления в zint.v, zports.v, delta-sigma (приводит к намагничиванию динамиков) + WXEDA 10.03.2015 порт на девборду WXEDA + + http://tslabs.info/forum/viewtopic.php?f=31&t=401 + http://zx-pk.ru/showthread.php?t=23528 + + Copyright (c) 2014 MVV, TS-Labs, dsp, waybester, palsw + + All rights reserved + + Redistribution and use in source and synthezised forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in synthesized form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of the author nor the names of other contributors may + be used to endorse or promote products derived from this software without + specific prior written agreement from the author. + + * License is granted for non-commercial use only. A fee may not be charged + for redistributions as source code or in synthesized/hardware form without + specific prior written agreement from the author. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ module tsconf @@ -113,11 +113,12 @@ module tsconf input [24:0] PS2_MOUSE, input [5:0] joystick, + input loader_act, input [15:0] loader_addr, input [7:0] loader_data, input loader_wr -); - +); + // CPU0 wire [15:0] cpu_a_bus; @@ -290,7 +291,7 @@ wire f0,f1; wire h0,h1; wire c0,c1,c2,c3; -clock TS01 +clock TS01 ( .clk(clk_28mhz), .f0(f0), @@ -305,7 +306,7 @@ clock TS01 wire zclk; wire zpos, zneg; -zclock TS02 +zclock TS02 ( .clk(clk_28mhz), .c0(c0), @@ -327,7 +328,7 @@ zclock TS02 reg zclk_r; always @(posedge clk) zclk_r <= zclk; -T80s CPU +T80s CPU ( .RESET_n(~reset), .CLK(clk), @@ -344,8 +345,8 @@ T80s CPU .DI(cpu_di_bus), .DO(cpu_do_bus) ); - -zsignals TS04 + +zsignals TS04 ( .clk(clk_28mhz), .iorq_n(cpu_iorq_n), @@ -373,8 +374,8 @@ zsignals TS04 .memwr_s(memwr_s), .opfetch_s(opfetch_s) ); - -zports TS05 + +zports TS05 ( .clk(clk_28mhz), .din(cpu_do_bus), @@ -447,8 +448,8 @@ zports TS05 .wait_start_gluclock(wait_start_gluclock), .wait_read(mc146818a_do_bus) ); - -zmem TS06 + +zmem TS06 ( .clk(clk_28mhz), .c0(c0), @@ -487,14 +488,15 @@ zmem TS06 .cpu_latch(cpu_latch), .cpu_stall(cpu_stall) // for Zclock if HI-> STALL (ZCLK) ); - -arbiter TS07 + +arbiter TS07 ( .clk(clk_28mhz), .c0(c0), .c1(c1), .c2(c2), .c3(c3), + .cyc(ce&c3), .dram_addr(dram_addr), .dram_req(dram_req), .dram_rnw(dram_rnw), @@ -511,6 +513,7 @@ arbiter TS07 .cpu_wrdata(cpu_do_bus), .cpu_req(cpu_req), .cpu_rnw(rd | csrom), + .cpu_csrom(csrom), .cpu_wrbsel(cpu_wrbsel), .cpu_next(cpu_next), // next cycle is allowed to be used by CPU .cpu_strobe(cpu_strobe), // c2 strobe @@ -527,10 +530,14 @@ arbiter TS07 .ts_next(ts_next), .tm_addr(tm_addr), .tm_req(tm_req), - .tm_next(tm_next) + .tm_next(tm_next), + .loader_clk(clk), + .loader_addr(loader_addr), + .loader_data(loader_data), + .loader_wr(loader_wr) ); - -video_top TS08 + +video_top TS08 ( .clk(clk_28mhz), .f0(f0), @@ -599,8 +606,8 @@ video_top TS08 .tm_req(tm_req), .tm_next(tm_next) ); - -dma TS09 + +dma TS09 ( .clk(clk_28mhz), .c2(c2), @@ -626,8 +633,8 @@ dma TS09 .cram_we(dma_cram_we), .sfile_we(dma_sfile_we) ); - -zmaps TS10 + +zmaps TS10 ( .clk(clk_28mhz), .memwr_s(memwr_s), @@ -645,7 +652,7 @@ zmaps TS10 .regs_we(regs_we) ); -spi TS11 +spi TS11 ( .clk(clk_28mhz), .sck(SD_CLK), @@ -658,8 +665,8 @@ spi TS11 .start(spi_start), .dout(spi_dout) ); - -zint TS13 + +zint TS13 ( .clk(clk_28mhz), .zpos(zpos), @@ -673,22 +680,9 @@ zint TS13 .im2vect(im2vect), //> CPU Din (2 downto 0); .int_n(cpu_int_n_TS) ); - -// BIOS -wire [7:0] bios_do_bus; -dpram #(.ADDRWIDTH(16), .MEM_INIT_FILE("rtl/tsbios.mif")) BIOS -( - .clock(clk), - .address_a({cpu_addr_20[14:0],cpu_wrbsel}), - .q_a(bios_do_bus), - - .address_b(loader_addr), - .data_b(loader_data), - .wren_b(loader_wr) -); // SDRAM Controller -sdram SE4 +sdram SE4 ( .clk(clk), .cyc(ce&c3), @@ -720,10 +714,10 @@ sdram SE4 wire [4:0] kb_do_bus; wire key_reset; wire [7:0] key_scancode; - -keyboard SE5 + +keyboard SE5 ( - .clk(clk_28mhz), + .clk(clk), .reset(COLD_RESET | WARM_RESET), .a(cpu_a_bus[15:8]), .keyb(kb_do_bus), @@ -731,10 +725,10 @@ keyboard SE5 .scancode(key_scancode), .ps2_key(PS2_KEY) ); - -kempston_mouse KM + +kempston_mouse KM ( - .clk_sys(clk_28mhz), + .clk_sys(clk), .reset(reset), .ps2_mouse(PS2_MOUSE), .addr(cpu_a_bus[10:8]), @@ -753,7 +747,7 @@ always @(posedge clk_28mhz) begin ena_0_4375mhz <= !div; //28MHz/64 end -mc146818a SE9 +mc146818a SE9 ( .RESET(reset), .CLK(clk_28mhz), @@ -775,7 +769,7 @@ wire [7:0] covox_b; wire [7:0] covox_c; wire [7:0] covox_d; -soundrive SE10 +soundrive SE10 ( .reset(reset), .clk(clk_28mhz), @@ -792,34 +786,34 @@ soundrive SE10 ); // Turbosound FM -reg ce_ym; -always @(posedge clk_28mhz) begin - reg [2:0] div; - - div <= div + 1'd1; - ce_ym <= !div; -end - -wire ts_enable = ~cpu_iorq_n & cpu_a_bus[0] & cpu_a_bus[15] & ~cpu_a_bus[1]; -wire ts_we = ts_enable & ~cpu_wr_n; - -wire [11:0] ts_l, ts_r; -wire [7:0] ts_do; +reg ce_ym; +always @(posedge clk_28mhz) begin + reg [2:0] div; + + div <= div + 1'd1; + ce_ym <= !div; +end + +wire ts_enable = ~cpu_iorq_n & cpu_a_bus[0] & cpu_a_bus[15] & ~cpu_a_bus[1]; +wire ts_we = ts_enable & ~cpu_wr_n; + +wire [11:0] ts_l, ts_r; +wire [7:0] ts_do; + +turbosound SE12 +( + .RESET(reset), + + .CLK(clk_28mhz), + .CE(ce_ym), + .BDIR(ts_we), + .BC(cpu_a_bus[14]), + .DI(cpu_do_bus), + .DO(ts_do), + .CHANNEL_L(ts_l), + .CHANNEL_R(ts_r) +); -turbosound SE12 -( - .RESET(reset), - - .CLK(clk_28mhz), - .CE(ce_ym), - .BDIR(ts_we), - .BC(cpu_a_bus[14]), - .DI(cpu_do_bus), - .DO(ts_do), - .CHANNEL_L(ts_l), - .CHANNEL_R(ts_r) -); - // General Sound wire [14:0] gs_l; @@ -827,7 +821,7 @@ wire [14:0] gs_r; wire [7:0] gs_do_bus; wire gs_sel = ~cpu_iorq_n & cpu_m1_n & (cpu_a_bus[7:4] == 'hB && cpu_a_bus[2:0] == 'h3); -gs #("rtl/sound/gs105b.mif") U15 +gs #("rtl/sound/gs105b.mif") U15 ( .RESET(reset), .CLK(clk), @@ -867,7 +861,7 @@ always @(posedge clk_28mhz) begin ce_saa <= (div == 0 || div == 3); end -saa1099 U16 +saa1099 U16 ( .clk_sys(clk_28mhz), .ce(ce_saa), @@ -899,7 +893,6 @@ assign RESET_OUT = reset; // CPU interface assign cpu_di_bus = - (csrom && ~cpu_mreq_n && ~cpu_rd_n) ? bios_do_bus : // BIOS (~cpu_mreq_n && ~cpu_rd_n) ? sdr_do_bus : // SDRAM (intack) ? im2vect : (gs_sel && ~cpu_rd_n) ? gs_do_bus : // General Sound diff --git a/sys/alsa.sv b/sys/alsa.sv deleted file mode 100644 index 9034389..0000000 --- a/sys/alsa.sv +++ /dev/null @@ -1,157 +0,0 @@ -//============================================================================ -// -// ALSA sound support for MiSTer -// (c)2019,2020 Alexey Melnikov -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -// -//============================================================================ - -module alsa -#( - parameter CLK_RATE = 24576000 -) -( - input reset, - input clk, - - output reg [31:3] ram_address, - input [63:0] ram_data, - output reg ram_req = 0, - input ram_ready, - - input spi_ss, - input spi_sck, - input spi_mosi, - output spi_miso, - - output reg [15:0] pcm_l, - output reg [15:0] pcm_r -); - -reg [60:0] buf_info; -reg [6:0] spicnt = 0; -always @(posedge spi_sck, posedge spi_ss) begin - reg [95:0] spi_data; - - if(spi_ss) spicnt <= 0; - else begin - spi_data[{spicnt[6:3],~spicnt[2:0]}] <= spi_mosi; - if(&spicnt) buf_info <= {spi_data[82:67],spi_data[50:35],spi_data[31:3]}; - spicnt <= spicnt + 1'd1; - end -end - -assign spi_miso = spi_out[{spicnt[4:3],~spicnt[2:0]}]; - -reg [31:0] spi_out = 0; -always @(posedge clk) if(spi_ss) spi_out <= {buf_rptr, hurryup, 8'h00}; - - -reg [31:3] buf_addr; -reg [18:3] buf_len; -reg [18:3] buf_wptr = 0; - -always @(posedge clk) begin - reg [60:0] data1,data2; - - data1 <= buf_info; - data2 <= data1; - if(data2 == data1) {buf_wptr,buf_len,buf_addr} <= data2; -end - -reg [2:0] hurryup = 0; -reg [18:3] buf_rptr = 0; - -always @(posedge clk) begin - reg [18:3] len = 0; - reg [1:0] ready = 0; - reg [63:0] readdata; - reg got_first = 0; - reg [7:0] ce_cnt = 0; - reg [1:0] state = 0; - - if(reset) begin - ready <= 0; - ce_cnt <= 0; - state <= 0; - got_first <= 0; - len <= 0; - end - else begin - - //ramp up - if(len[18:14] && (hurryup < 1)) hurryup <= 1; - if(len[18:16] && (hurryup < 2)) hurryup <= 2; - if(len[18:17] && (hurryup < 4)) hurryup <= 4; - - //ramp down - if(!len[18:15] && (hurryup > 2)) hurryup <= 2; - if(!len[18:13] && (hurryup > 1)) hurryup <= 1; - if(!len[18:10]) hurryup <= 0; - - if(ce_sample && ~&ce_cnt) ce_cnt <= ce_cnt + 1'd1; - - case(state) - 0: if(!ce_sample) begin - if(ready) begin - if(ce_cnt) begin - {readdata[31:0],pcm_r,pcm_l} <= readdata; - ready <= ready - 1'd1; - ce_cnt <= ce_cnt - 1'd1; - end - end - else if(buf_rptr != buf_wptr) begin - if(~got_first) begin - buf_rptr <= buf_wptr; - got_first <= 1; - end - else begin - ram_address <= buf_addr + buf_rptr; - ram_req <= ~ram_req; - buf_rptr <= buf_rptr + 1'd1; - len <= (buf_wptr < buf_rptr) ? (buf_len + buf_wptr - buf_rptr) : (buf_wptr - buf_rptr); - state <= 1; - end - end - else begin - len <= 0; - ce_cnt <= 0; - hurryup <= 0; - end - end - 1: if(ram_ready) begin - ready <= 2; - readdata <= ram_data; - if(buf_rptr >= buf_len) buf_rptr <= buf_rptr - buf_len; - state <= 0; - end - endcase - end -end - -reg ce_sample; -always @(posedge clk) begin - reg [31:0] acc = 0; - - ce_sample <= 0; - acc <= acc + 48000 + {hurryup,6'd0}; - if(acc >= CLK_RATE) begin - acc <= acc - CLK_RATE; - ce_sample <= 1; - end -end - -endmodule diff --git a/sys/arcade_video.v b/sys/arcade_video.v deleted file mode 100644 index f53b136..0000000 --- a/sys/arcade_video.v +++ /dev/null @@ -1,324 +0,0 @@ -//============================================================================ -// -// Copyright (C) 2017-2020 Sorgelig -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -// -//============================================================================ - -////////////////////////////////////////////////////////// -// DW: -// 6 : 2R 2G 2B -// 8 : 3R 3G 2B -// 9 : 3R 3G 3B -// 12 : 4R 4G 4B -// 24 : 8R 8G 8B - -module arcade_video #(parameter WIDTH=320, DW=8, GAMMA=1) -( - input clk_video, - input ce_pix, - - input[DW-1:0] RGB_in, - input HBlank, - input VBlank, - input HSync, - input VSync, - - output CLK_VIDEO, - output CE_PIXEL, - output [7:0] VGA_R, - output [7:0] VGA_G, - output [7:0] VGA_B, - output VGA_HS, - output VGA_VS, - output VGA_DE, - output [1:0] VGA_SL, - - input [2:0] fx, - input forced_scandoubler, - inout [21:0] gamma_bus -); - -assign CLK_VIDEO = clk_video; - -wire hs_fix,vs_fix; -sync_fix sync_v(CLK_VIDEO, HSync, hs_fix); -sync_fix sync_h(CLK_VIDEO, VSync, vs_fix); - -reg [DW-1:0] RGB_fix; - -reg CE,HS,VS,HBL,VBL; -always @(posedge CLK_VIDEO) begin - reg old_ce; - old_ce <= ce_pix; - CE <= 0; - if(~old_ce & ce_pix) begin - CE <= 1; - HS <= hs_fix; - if(~HS & hs_fix) VS <= vs_fix; - - RGB_fix <= RGB_in; - HBL <= HBlank; - if(HBL & ~HBlank) VBL <= VBlank; - end -end - -wire [7:0] R,G,B; - -generate - if(DW == 6) begin - assign R = {RGB_fix[5:4],RGB_fix[5:4],RGB_fix[5:4],RGB_fix[5:4]}; - assign G = {RGB_fix[3:2],RGB_fix[3:2],RGB_fix[3:2],RGB_fix[3:2]}; - assign B = {RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0]}; - end - else if(DW == 8) begin - assign R = {RGB_fix[7:5],RGB_fix[7:5],RGB_fix[7:6]}; - assign G = {RGB_fix[4:2],RGB_fix[4:2],RGB_fix[4:3]}; - assign B = {RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0]}; - end - else if(DW == 9) begin - assign R = {RGB_fix[8:6],RGB_fix[8:6],RGB_fix[8:7]}; - assign G = {RGB_fix[5:3],RGB_fix[5:3],RGB_fix[5:4]}; - assign B = {RGB_fix[2:0],RGB_fix[2:0],RGB_fix[2:1]}; - end - else if(DW == 12) begin - assign R = {RGB_fix[11:8],RGB_fix[11:8]}; - assign G = {RGB_fix[7:4],RGB_fix[7:4]}; - assign B = {RGB_fix[3:0],RGB_fix[3:0]}; - end - else begin // 24 - assign R = RGB_fix[23:16]; - assign G = RGB_fix[15:8]; - assign B = RGB_fix[7:0]; - end -endgenerate - -assign VGA_SL = sl[1:0]; -wire [2:0] sl = fx ? fx - 1'd1 : 3'd0; -wire scandoubler = fx || forced_scandoubler; - -video_mixer #(.LINE_LENGTH(WIDTH+4), .HALF_DEPTH(DW!=24), .GAMMA(GAMMA)) video_mixer -( - .CLK_VIDEO(CLK_VIDEO), - .ce_pix(CE), - .CE_PIXEL(CE_PIXEL), - - .scandoubler(scandoubler), - .hq2x(fx==1), - .gamma_bus(gamma_bus), - - .R((DW!=24) ? R[7:4] : R), - .G((DW!=24) ? G[7:4] : G), - .B((DW!=24) ? B[7:4] : B), - - .HSync (HS), - .VSync (VS), - .HBlank(HBL), - .VBlank(VBL), - - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .VGA_DE(VGA_DE) -); - -endmodule - -//============================================================================ -// -// Screen +90/-90 deg. rotation -// Copyright (C) 2020 Sorgelig -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -// -//============================================================================ - -module screen_rotate -( - input CLK_VIDEO, - input CE_PIXEL, - - input [7:0] VGA_R, - input [7:0] VGA_G, - input [7:0] VGA_B, - input VGA_HS, - input VGA_VS, - input VGA_DE, - - input rotate_ccw, - input no_rotate, - input flip, - output video_rotated, - - output FB_EN, - output [4:0] FB_FORMAT, - output reg [11:0] FB_WIDTH, - output reg [11:0] FB_HEIGHT, - output [31:0] FB_BASE, - output [13:0] FB_STRIDE, - input FB_VBL, - input FB_LL, - - output DDRAM_CLK, - input DDRAM_BUSY, - output [7:0] DDRAM_BURSTCNT, - output [28:0] DDRAM_ADDR, - output [63:0] DDRAM_DIN, - output [7:0] DDRAM_BE, - output DDRAM_WE, - output DDRAM_RD -); - -parameter MEM_BASE = 7'b0010010; // buffer at 0x24000000, 3x8MB - -reg do_flip; - -assign DDRAM_CLK = CLK_VIDEO; -assign DDRAM_BURSTCNT = 1; -assign DDRAM_ADDR = {MEM_BASE, i_fb, ram_addr[22:3]}; -assign DDRAM_BE = ram_addr[2] ? 8'hF0 : 8'h0F; -assign DDRAM_DIN = {ram_data,ram_data}; -assign DDRAM_WE = ram_wr; -assign DDRAM_RD = 0; - -assign FB_EN = fb_en[2]; -assign FB_FORMAT = 5'b00110; -assign FB_BASE = {MEM_BASE,o_fb,23'd0}; -assign FB_STRIDE = stride; - -function [1:0] buf_next; - input [1:0] a,b; - begin - buf_next = 1; - if ((a==0 && b==1) || (a==1 && b==0)) buf_next = 2; - if ((a==1 && b==2) || (a==2 && b==1)) buf_next = 0; - end -endfunction - -assign video_rotated = ~no_rotate; - -always @(posedge CLK_VIDEO) begin - do_flip <= no_rotate && flip; - if( do_flip ) begin - FB_WIDTH <= hsz; - FB_HEIGHT <= vsz; - end else begin - FB_WIDTH <= vsz; - FB_HEIGHT <= hsz; - end -end - -reg [1:0] i_fb,o_fb; -always @(posedge CLK_VIDEO) begin - reg old_vbl,old_vs; - old_vbl <= FB_VBL; - old_vs <= VGA_VS; - - if(FB_LL) begin - if(~old_vbl & FB_VBL) o_fb<={1'b0,~i_fb[0]}; - if(~old_vs & VGA_VS) i_fb<={1'b0,~i_fb[0]}; - end - else begin - if(~old_vbl & FB_VBL) o_fb<=buf_next(o_fb,i_fb); - if(~old_vs & VGA_VS) i_fb<=buf_next(i_fb,o_fb); - end -end - -initial begin - fb_en = 0; -end - -reg [2:0] fb_en = 0; -reg [11:0] hsz = 320, vsz = 240; -reg [11:0] bwidth; -reg [22:0] bufsize; -always @(posedge CLK_VIDEO) begin - reg [11:0] hcnt = 0, vcnt = 0; - reg old_vs, old_de; - - if(CE_PIXEL) begin - old_vs <= VGA_VS; - old_de <= VGA_DE; - - hcnt <= hcnt + 1'd1; - if(~old_de & VGA_DE) begin - hcnt <= 1; - vcnt <= vcnt + 1'd1; - end - if(old_de & ~VGA_DE) begin - hsz <= hcnt; - if( do_flip ) bwidth <= hcnt + 2'd3; - end - if(~old_vs & VGA_VS) begin - vsz <= vcnt; - if( !do_flip ) bwidth <= vcnt + 2'd3; - vcnt <= 0; - fb_en <= {fb_en[1:0], ~no_rotate | flip}; - end - if(old_vs & ~VGA_VS) bufsize <= (do_flip ? vsz : hsz ) * stride; - end -end - -wire [13:0] stride = {bwidth[11:2], 4'd0}; - -reg [22:0] ram_addr, next_addr; -reg [31:0] ram_data; -reg ram_wr; -always @(posedge CLK_VIDEO) begin - reg [13:0] hcnt = 0; - reg old_vs, old_de; - - ram_wr <= 0; - if(CE_PIXEL && FB_EN) begin - old_vs <= VGA_VS; - old_de <= VGA_DE; - - if(~old_vs & VGA_VS) begin - next_addr <= - do_flip ? bufsize-3'd4 : - rotate_ccw ? (bufsize - stride) : {vsz-1'd1, 2'b00}; - hcnt <= rotate_ccw ? 3'd4 : {vsz-2'd2, 2'b00}; - end - if(VGA_DE) begin - ram_wr <= 1; - ram_data <= {8'd0,VGA_B,VGA_G,VGA_R}; - ram_addr <= next_addr; - next_addr <= - do_flip ? next_addr-3'd4 : - rotate_ccw ? (next_addr - stride) : (next_addr + stride); - end - if(old_de & ~VGA_DE & ~do_flip) begin - next_addr <= rotate_ccw ? (bufsize - stride + hcnt) : hcnt; - hcnt <= rotate_ccw ? (hcnt + 3'd4) : (hcnt - 3'd4); - end - end -end - -endmodule diff --git a/sys/ascal.vhd b/sys/ascal.vhd deleted file mode 100644 index 6f085e0..0000000 --- a/sys/ascal.vhd +++ /dev/null @@ -1,2914 +0,0 @@ --------------------------------------------------------------------------------- --- AVALON SCALER --------------------------------------------------------------------------------- --- TEMLIB 2018 - 2020 --------------------------------------------------------------------------------- --- This code can be freely distributed and used for any purpose, but, if you --- find any bug, or want to suggest an enhancement, you ought to send a mail --- to info@temlib.org. --------------------------------------------------------------------------------- - --- Features --- - Arbitrary output video format --- - Autodetect input image size or fixed window --- - Progressive and interlaced input --- - Interpolation --- Upscaling : Nearest, Bilinear, Sharp Bilinear, Bicubic, Polyphase --- Downscaling : Nearest, Bilinear --- - Avalon bus interface with 128 or 64 bits DATA --- - Optional triple buffering --- - Support for external low lag syntonization - --------------------------------------------- --- Downscaling --- - Horizontal and vertical up-/down-scaling are independant. --- - Downscaling, H and/or V, supports only nearest-neighbour and bilinear --- filtering. --- - For interlaced video, when the vertical size is lower than a deinterlaced --- frame size (2x half-frame), the scaler processes only half-frames --- and upscales (when the output size is between 1x an 2x) or downscales (size --- below 1x) them. - --------------------------------------------- --- 5 clock domains --- i_xxx : Input video --- o_xxx : Output video --- avl_xxx : Avalon memory bus --- poly_xxx : Polyphase filters memory --- pal_xxx : Framebuffer mode 8bpp palette. - --------------------------------------------- --- O_FB_FORMAT : Framebuffer format --- [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp --- [3] : 0=16bits 565 1=16bits 1555 --- [4] : 0=RGB 1=BGR (for 16/24/32 modes) --- [5] : TBD - --------------------------------------------- --- Image header. When HEADER = TRUE --- Header Address = RAMBASE --- Image Address = RAMBASE + HEADER_SIZE - --- Header (Bytes. Big Endian.) --- 0 : Type = 1 --- 1 : Pixel format --- 0 : 16 bits/pixel, RGB : RRRRRGGGGGGBBBBB --- 1 : 24 bits/pixel, RGB --- 2 : 32 bits/pixel, RGB0 - --- 3:2 : Header size : Offset to start of picture (= N_BURST). 12 bits --- 5:4 : Attributes --- b0 ; Interlaced --- b1 : Field number --- b2 : Horizontal downscaled --- b3 : Vertical downscaled --- b4 : Triple buffered --- b7-5 : Frame counter --- 7:6 : Image width. Pixels. 12 bits --- 9:8 : Image height. Pixels. 12 bits --- 11:10 : Line length. Bytes. --- 13:12 : Output width. Pixels. 12 bits --- 15:14 : Output height. Pixels. 12 bits --------------------------------------------- - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - --- MODE[2:0] --- 000 : Nearest --- 001 : Bilinear --- 010 : Sharp Bilinear --- 011 : Bicubic --- 100 : Polyphase --- 101 : TBD --- 110 : TBD --- 111 : TBD - --- MODE[3] --- 0 : Direct. Single framebuffer. --- 1 : Triple buffering - --- MODE[4] : TBD - --- MASK : Enable / Disable selected interpoler --- 0:Nearest 1:Bilinear 2:SharpBilinear 3:Bicubic 4:Polyphase --- RAMBASE : RAM base address for framebuffer --- RAMSIZE : RAM allocated for one framebuffer (needs x3 if triple-buffering) --- Must be a power of two --- INTER : True=Autodetect interlaced video False=Force progressive scan --- HEADER : True=Add image properties header --- PALETTE : Enable palette for framebuffer 8bpp mode --- PALETTE2 : Enable palette for framebuffer 8bpp mode supplied by core --- DOWNSCALE : True=Support downscaling False=Downscaling disabled --- BYTESWAP : Little/Big endian byte swap --- FRAC : Fractional bits, subpixel resolution --- OHRES : Max. output horizontal resolution. Must be a power of two. --- (Used for sizing line buffers) --- IHRES : Max. input horizontal resolution. Must be a power of two. --- (Used for sizing line buffers) --- N_DW : Avalon data bus width. 64 or 128 bits --- N_AW : Avalon address bus width --- N_BURST : Burst size in bytes. Power of two. - -ENTITY ascal IS - GENERIC ( - MASK : unsigned(7 DOWNTO 0) :=x"FF"; - RAMBASE : unsigned(31 DOWNTO 0); - RAMSIZE : unsigned(31 DOWNTO 0) := x"0080_0000"; -- =8MB - INTER : boolean := true; - HEADER : boolean := true; - DOWNSCALE : boolean := true; - BYTESWAP : boolean := true; - PALETTE : boolean := true; - PALETTE2 : boolean := true; - ADAPTIVE : boolean := true; - DOWNSCALE_NN : boolean := false; - FRAC : natural RANGE 4 TO 8 :=4; - OHRES : natural RANGE 1 TO 4096 :=2048; - IHRES : natural RANGE 1 TO 2048 :=2048; - N_DW : natural RANGE 64 TO 128 := 128; - N_AW : natural RANGE 8 TO 32 := 32; - N_BURST : natural := 256 -- 256 bytes per burst - ); - PORT ( - ------------------------------------ - -- Input video - i_r : IN unsigned(7 DOWNTO 0); - i_g : IN unsigned(7 DOWNTO 0); - i_b : IN unsigned(7 DOWNTO 0); - i_hs : IN std_logic; -- H sync - i_vs : IN std_logic; -- V sync - i_fl : IN std_logic; -- Interlaced field - i_de : IN std_logic; -- Display Enable - i_ce : IN std_logic; -- Clock Enable - i_clk : IN std_logic; -- Input clock - - ------------------------------------ - -- Output video - o_r : OUT unsigned(7 DOWNTO 0); - o_g : OUT unsigned(7 DOWNTO 0); - o_b : OUT unsigned(7 DOWNTO 0); - o_hs : OUT std_logic; -- H sync - o_vs : OUT std_logic; -- V sync - o_de : OUT std_logic; -- Display Enable - o_vbl : OUT std_logic; -- V blank - o_brd : OUT std_logic; -- border enable - o_ce : IN std_logic; -- Clock Enable - o_clk : IN std_logic; -- Output clock - - -- Border colour R G B - o_border : IN unsigned(23 DOWNTO 0) := x"000000"; - - ------------------------------------ - -- Framebuffer mode - o_fb_ena : IN std_logic :='0'; -- Enable Framebuffer Mode - o_fb_hsize : IN natural RANGE 0 TO 4095 :=0; - o_fb_vsize : IN natural RANGE 0 TO 4095 :=0; - o_fb_format : IN unsigned(5 DOWNTO 0) :="000100"; - o_fb_base : IN unsigned(31 DOWNTO 0) :=x"0000_0000"; - o_fb_stride : IN unsigned(13 DOWNTO 0) :=(OTHERS =>'0'); - - -- Framebuffer palette in 8bpp mode - pal1_clk : IN std_logic :='0'; - pal1_dw : IN unsigned(47 DOWNTO 0) :=x"000000000000"; -- R1 G1 B1 R0 G0 B0 - pal1_dr : OUT unsigned(47 DOWNTO 0) :=x"000000000000"; - pal1_a : IN unsigned(6 DOWNTO 0) :="0000000"; -- Colour index/2 - pal1_wr : IN std_logic :='0'; - - pal_n : IN std_logic :='0'; - - pal2_clk : IN std_logic :='0'; - pal2_dw : IN unsigned(23 DOWNTO 0) :=x"000000"; -- R G B - pal2_dr : OUT unsigned(23 DOWNTO 0) :=x"000000"; - pal2_a : IN unsigned(7 DOWNTO 0) :="00000000"; -- Colour index - pal2_wr : IN std_logic :='0'; - - ------------------------------------ - -- Low lag PLL tuning - o_lltune : OUT unsigned(15 DOWNTO 0); - - ------------------------------------ - -- Input video parameters - iauto : IN std_logic :='1'; -- 1=Autodetect image size 0=Choose window - himin : IN natural RANGE 0 TO 4095 :=0; -- MIN < MAX, MIN >=0, MAX < DISP - himax : IN natural RANGE 0 TO 4095 :=0; - vimin : IN natural RANGE 0 TO 4095 :=0; - vimax : IN natural RANGE 0 TO 4095 :=0; - - -- Detected input image size - i_hdmax : OUT natural RANGE 0 TO 4095; - i_vdmax : OUT natural RANGE 0 TO 4095; - - -- Output video parameters - run : IN std_logic :='1'; -- 1=Enable output image. 0=No image - freeze : IN std_logic :='0'; -- 1=Disable framebuffer writes - mode : IN unsigned(4 DOWNTO 0); - -- SYNC |_________________________/"""""""""\_______| - -- DE |""""""""""""""""""\________________________| - -- RGB | <#IMAGE#> ^HDISP | - -- ^HMIN ^HMAX ^HSSTART ^HSEND ^HTOTAL - htotal : IN natural RANGE 0 TO 4095; - hsstart : IN natural RANGE 0 TO 4095; - hsend : IN natural RANGE 0 TO 4095; - hdisp : IN natural RANGE 0 TO 4095; - hmin : IN natural RANGE 0 TO 4095; - hmax : IN natural RANGE 0 TO 4095; -- 0 <= hmin < hmax < hdisp - vtotal : IN natural RANGE 0 TO 4095; - vsstart : IN natural RANGE 0 TO 4095; - vsend : IN natural RANGE 0 TO 4095; - vdisp : IN natural RANGE 0 TO 4095; - vmin : IN natural RANGE 0 TO 4095; - vmax : IN natural RANGE 0 TO 4095; -- 0 <= vmin < vmax < vdisp - vrr : IN std_logic := '0'; - vrrmax : IN natural RANGE 0 TO 4095 := 0; - - -- Scaler format. 00=16bpp 565, 01=24bpp 10=32bpp - format : IN unsigned(1 DOWNTO 0) :="01"; - - ------------------------------------ - -- Polyphase filter coefficients - -- Order : - -- [Horizontal] [Vertical] [Horizontal2] [Vertical2] - -- [0]...[2**FRAC-1] - -- [-1][0][1][2] - poly_clk : IN std_logic; - poly_dw : IN unsigned(9 DOWNTO 0); - poly_a : IN unsigned(FRAC+3 DOWNTO 0); - poly_wr : IN std_logic; - - ------------------------------------ - -- Avalon - avl_clk : IN std_logic; -- Avalon clock - avl_waitrequest : IN std_logic; - avl_readdata : IN std_logic_vector(N_DW-1 DOWNTO 0); - avl_readdatavalid : IN std_logic; - avl_burstcount : OUT std_logic_vector(7 DOWNTO 0); - avl_writedata : OUT std_logic_vector(N_DW-1 DOWNTO 0); - avl_address : OUT std_logic_vector(N_AW-1 DOWNTO 0); - avl_write : OUT std_logic; - avl_read : OUT std_logic; - avl_byteenable : OUT std_logic_vector(N_DW/8-1 DOWNTO 0); - - ------------------------------------ - reset_na : IN std_logic - ); - -BEGIN - ASSERT N_DW=64 OR N_DW=128 REPORT "DW" SEVERITY failure; - -END ENTITY ascal; - ---############################################################################## - -ARCHITECTURE rtl OF ascal IS - - CONSTANT MASK_NEAREST : natural :=0; - CONSTANT MASK_BILINEAR : natural :=1; - CONSTANT MASK_SHARP_BILINEAR : natural :=2; - CONSTANT MASK_BICUBIC : natural :=3; - CONSTANT MASK_POLY : natural :=4; - - ---------------------------------------------------------- - FUNCTION ilog2 (CONSTANT v : natural) RETURN natural IS - VARIABLE r : natural := 1; - VARIABLE n : natural := 0; - BEGIN - WHILE v>r LOOP - n:=n+1; - r:=r*2; - END LOOP; - RETURN n; - END FUNCTION ilog2; - FUNCTION to_std_logic (a : boolean) RETURN std_logic IS - BEGIN - IF a THEN RETURN '1'; - ELSE RETURN '0'; - END IF; - END FUNCTION to_std_logic; - - ---------------------------------------------------------- - CONSTANT NB_BURST : natural :=ilog2(N_BURST); - CONSTANT NB_LA : natural :=ilog2(N_DW/8); -- Low address bits - CONSTANT BLEN : natural :=N_BURST / N_DW * 8; -- Burst length - - ---------------------------------------------------------- - TYPE arr_dw IS ARRAY (natural RANGE <>) OF unsigned(N_DW-1 DOWNTO 0); - - TYPE type_pix IS RECORD - r,g,b : unsigned(7 DOWNTO 0); -- 0.8 - END RECORD; - TYPE arr_pix IS ARRAY (natural RANGE <>) OF type_pix; - TYPE arr_pixq IS ARRAY(natural RANGE <>) OF arr_pix(0 TO 3); - ATTRIBUTE ramstyle : string; - - SUBTYPE uint12 IS natural RANGE 0 TO 4095; - SUBTYPE uint13 IS natural RANGE 0 TO 8191; - - TYPE arr_uv48 IS ARRAY (natural RANGE <>) OF unsigned(47 DOWNTO 0); - TYPE arr_uv24 IS ARRAY (natural RANGE <>) OF unsigned(23 DOWNTO 0); - TYPE arr_uv40 IS ARRAY (natural RANGE <>) OF unsigned(39 DOWNTO 0); - TYPE arr_int9 IS ARRAY (natural RANGE <>) OF integer RANGE -256 TO 255; - TYPE arr_uint12 IS ARRAY (natural RANGE <>) OF uint12; - TYPE arr_frac IS ARRAY (natural RANGE <>) OF unsigned(11 DOWNTO 0); - TYPE arr_div IS ARRAY (natural RANGE <>) OF unsigned(20 DOWNTO 0); - - ---------------------------------------------------------- - -- Input image - SIGNAL i_pvs,i_pfl,i_pde,i_pce : std_logic; - SIGNAL i_ppix : type_pix; - SIGNAL i_freeze : std_logic; - SIGNAL i_count : unsigned(2 DOWNTO 0); - SIGNAL i_hsize,i_hmin,i_hmax,i_hcpt : uint12; - SIGNAL i_hrsize,i_vrsize : uint12; - SIGNAL i_himax,i_vimax : uint12; - SIGNAL i_vsize,i_vmaxmin,i_vmin,i_vmax,i_vcpt : uint12; - SIGNAL i_iauto : std_logic; - SIGNAL i_mode : unsigned(4 DOWNTO 0); - SIGNAL i_format : unsigned(1 DOWNTO 0); - SIGNAL i_ven,i_sof : std_logic; - SIGNAL i_wr : std_logic; - SIGNAL i_divstart,i_divrun : std_logic; - SIGNAL i_de_pre,i_vs_pre,i_fl_pre : std_logic; - SIGNAL i_de_delay : natural RANGE 0 TO 31; - SIGNAL i_intercnt : natural RANGE 0 TO 3; - SIGNAL i_inter,i_half,i_flm : std_logic; - SIGNAL i_write,i_wreq,i_alt,i_line,i_wline,i_wline_mem : std_logic; - SIGNAL i_walt,i_walt_mem,i_wreq_mem : std_logic; - SIGNAL i_wdelay : natural RANGE 0 TO 7; - SIGNAL i_push,i_pushend,i_pushend2 : std_logic; - SIGNAL i_eol : std_logic; - SIGNAL i_pushhead,i_pushhead2,i_pushhead3 : std_logic; - SIGNAL i_hburst,i_hbcpt : natural RANGE 0 TO 31; - SIGNAL i_shift : unsigned(0 TO 119) := (OTHERS =>'0'); - SIGNAL i_head : unsigned(127 DOWNTO 0); - SIGNAL i_acpt : natural RANGE 0 TO 15; - SIGNAL i_dpram : arr_dw(0 TO BLEN*2-1); - ATTRIBUTE ramstyle OF i_dpram : SIGNAL IS "no_rw_check"; - SIGNAL i_endframe0,i_endframe1,i_vss : std_logic; - SIGNAL i_wad : natural RANGE 0 TO BLEN*2-1; - SIGNAL i_dw : unsigned(N_DW-1 DOWNTO 0); - SIGNAL i_adrs,i_adrsi,i_wadrs,i_wadrs_mem : unsigned(31 DOWNTO 0); - SIGNAL i_reset_na : std_logic; - SIGNAL i_hnp,i_vnp : std_logic; - SIGNAL i_mem : arr_pix(0 TO IHRES-1); -- Downscale line buffer - ATTRIBUTE ramstyle OF i_mem : SIGNAL IS "no_rw_check"; - SIGNAL i_ohsize,i_ovsize : uint12; - SIGNAL i_vdivi : unsigned(12 DOWNTO 0); - SIGNAL i_vdivr : unsigned(24 DOWNTO 0); - SIGNAL i_div : unsigned(16 DOWNTO 0); - SIGNAL i_dir : unsigned(11 DOWNTO 0); - SIGNAL i_h_frac,i_v_frac : unsigned(11 DOWNTO 0); - SIGNAL i_hacc,i_vacc : uint13; - SIGNAL i_hdown,i_vdown : std_logic; - SIGNAL i_divcpt : natural RANGE 0 TO 36; - SIGNAL i_lwad,i_lrad : natural RANGE 0 TO OHRES-1; - SIGNAL i_lwr,i_bil : std_logic; - SIGNAL i_ldw,i_ldrm : type_pix; - SIGNAL i_hpixp,i_hpix0,i_hpix1,i_hpix2,i_hpix3,i_hpix4 : type_pix; - SIGNAL i_hpix,i_pix : type_pix; - SIGNAL i_hnp1,i_hnp2,i_hnp3,i_hnp4 : std_logic; - SIGNAL i_ven1,i_ven2,i_ven3,i_ven4,i_ven5,i_ven6 : std_logic; - - ---------------------------------------------------------- - -- Avalon - TYPE type_avl_state IS (sIDLE,sWRITE,sREAD); - SIGNAL avl_state : type_avl_state; - SIGNAL avl_write_i,avl_write_sync,avl_write_sync2 : std_logic; - SIGNAL avl_read_i,avl_read_sync,avl_read_sync2 : std_logic; - SIGNAL avl_read_pulse,avl_write_pulse : std_logic; - SIGNAL avl_read_sr,avl_write_sr,avl_read_clr,avl_write_clr : std_logic; - SIGNAL avl_rad,avl_rad_c,avl_wad : natural RANGE 0 TO 2*BLEN-1; - SIGNAL avl_walt,avl_wline,avl_rline : std_logic; - SIGNAL avl_dw,avl_dr : unsigned(N_DW-1 DOWNTO 0); - SIGNAL avl_wr : std_logic; - SIGNAL avl_readdataack,avl_readack : std_logic; - SIGNAL avl_radrs,avl_wadrs : unsigned(31 DOWNTO 0); - SIGNAL avl_i_offset0,avl_o_offset0 : unsigned(31 DOWNTO 0); - SIGNAL avl_i_offset1,avl_o_offset1 : unsigned(31 DOWNTO 0); - SIGNAL avl_reset_na : std_logic; - SIGNAL avl_o_vs_sync,avl_o_vs : std_logic; - SIGNAL avl_fb_ena : std_logic; - - FUNCTION buf_next(a,b : natural RANGE 0 TO 2; freeze : std_logic := '0') RETURN natural IS - BEGIN - IF (freeze='1') THEN RETURN a; END IF; - IF (a=0 AND b=1) OR (a=1 AND b=0) THEN RETURN 2; END IF; - IF (a=1 AND b=2) OR (a=2 AND b=1) THEN RETURN 0; END IF; - RETURN 1; - END FUNCTION; - FUNCTION buf_offset(b : natural RANGE 0 TO 2; - base : unsigned(31 DOWNTO 0); - size : unsigned(31 DOWNTO 0)) RETURN unsigned IS - BEGIN - IF b=1 THEN RETURN base+size; END IF; - IF b=2 THEN RETURN base+(size(30 DOWNTO 0) & '0'); END IF; - RETURN base; - END FUNCTION; - - ---------------------------------------------------------- - -- Output - SIGNAL o_run : std_logic; - SIGNAL o_freeze : std_logic; - SIGNAL o_mode,o_hmode,o_vmode : unsigned(4 DOWNTO 0); - SIGNAL o_format : unsigned(5 DOWNTO 0); - SIGNAL o_fb_pal_dr : unsigned(23 DOWNTO 0); - SIGNAL o_fb_pal_dr2 : unsigned(23 DOWNTO 0); - SIGNAL o_fb_pal_dr_x2 : unsigned(47 DOWNTO 0); - SIGNAL pal_idx: unsigned(7 DOWNTO 0); - SIGNAL pal_idx_lsb: std_logic; - SIGNAL pal1_mem : arr_uv48(0 TO 127); - SIGNAL pal2_mem : arr_uv24(0 TO 255); - ATTRIBUTE ramstyle of pal1_mem : signal is "no_rw_check"; - ATTRIBUTE ramstyle of pal2_mem : signal is "no_rw_check"; - SIGNAL o_htotal,o_hsstart,o_hsend : uint12; - SIGNAL o_hmin,o_hmax,o_hdisp,o_v_hmin_adj : uint12; - SIGNAL o_hsize,o_vsize : uint12; - SIGNAL o_vtotal,o_vsstart,o_vsend : uint12; - SIGNAL o_vrr,o_isync,o_isync2 : std_logic; - SIGNAL o_vrr_sync,o_vrr_sync2 : boolean; - SIGNAL o_vrr_min,o_vrr_min2 : boolean; - SIGNAL o_vrr_max,o_vrr_max2 : boolean; - SIGNAL o_vcpt_sync,o_vcpt_sync2, o_vrrmax : uint12; - SIGNAL o_sync, o_sync_max : boolean; - SIGNAL o_vmin,o_vmax,o_vdisp : uint12; - SIGNAL o_divcpt : natural RANGE 0 TO 36; - SIGNAL o_iendframe0,o_iendframe02,o_iendframe1,o_iendframe12 : std_logic; - SIGNAL o_bufup0,o_bufup1,o_inter : std_logic; - SIGNAL o_ibuf0,o_ibuf1,o_obuf0,o_obuf1 : natural RANGE 0 TO 2; - TYPE enum_o_state IS (sDISP,sHSYNC,sREAD,sWAITREAD); - SIGNAL o_state : enum_o_state; - TYPE enum_o_copy IS (sWAIT,sSHIFT,sCOPY); - SIGNAL o_copy : enum_o_copy; - SIGNAL o_pshift : natural RANGE 0 TO 15; - SIGNAL o_readack,o_readack_sync,o_readack_sync2 : std_logic; - SIGNAL o_readdataack,o_readdataack_sync,o_readdataack_sync2 : std_logic; - SIGNAL o_copyv : unsigned(0 TO 14); - SIGNAL o_adrs : unsigned(31 DOWNTO 0); -- Avalon address - SIGNAL o_adrs_pre : natural RANGE 0 TO 2**24-1; - SIGNAL o_stride : unsigned(13 DOWNTO 0); - SIGNAL o_adrsa,o_adrsb,o_rline : std_logic; - SIGNAL o_ad,o_ad1,o_ad2,o_ad3 : natural RANGE 0 TO 2*BLEN-1; - SIGNAL o_adturn : std_logic; - SIGNAL o_dr : unsigned(N_DW-1 DOWNTO 0); - SIGNAL o_shift : unsigned(0 TO N_DW+15); - SIGNAL o_sh,o_sh1,o_sh2,o_sh3,o_sh4 : std_logic; - SIGNAL o_reset_na : std_logic; - SIGNAL o_dpram : arr_dw(0 TO BLEN*2-1); - ATTRIBUTE ramstyle OF o_dpram : SIGNAL IS "no_rw_check"; - SIGNAL o_line0,o_line1,o_line2,o_line3 : arr_pix(0 TO OHRES-1); - ATTRIBUTE ramstyle OF o_line0 : SIGNAL IS "no_rw_check"; - ATTRIBUTE ramstyle OF o_line1 : SIGNAL IS "no_rw_check"; - ATTRIBUTE ramstyle OF o_line2 : SIGNAL IS "no_rw_check"; - ATTRIBUTE ramstyle OF o_line3 : SIGNAL IS "no_rw_check"; - SIGNAL o_wadl,o_radl0,o_radl1,o_radl2,o_radl3 : natural RANGE 0 TO OHRES-1; - SIGNAL o_ldw,o_ldr0,o_ldr1,o_ldr2,o_ldr3 : type_pix; - SIGNAL o_wr : unsigned(3 DOWNTO 0); - SIGNAL o_hcpt,o_vcpt,o_vcpt_pre,o_vcpt_pre2,o_vcpt_pre3,o_vcpt2 : uint12; - SIGNAL o_ihsize,o_ihsizem,o_ivsize : uint12; - SIGNAL o_ihsize_temp, o_ihsize_temp2 : natural RANGE 0 TO 32767; - - SIGNAL o_vfrac : unsigned(11 DOWNTO 0); - SIGNAL o_hfrac : arr_frac(0 TO 9); - ATTRIBUTE ramstyle OF o_hfrac : SIGNAL IS "logic"; -- avoid blockram shift register - - SIGNAL o_hacc,o_hacc_ini,o_hacc_next,o_vacc,o_vacc_next,o_vacc_ini : natural RANGE 0 TO 4*OHRES-1; - SIGNAL o_hsv,o_vsv,o_dev,o_pev,o_end : unsigned(0 TO 11); - SIGNAL o_hsp,o_vss : std_logic; - SIGNAL o_vcarrym,o_prim : boolean; - SIGNAL o_read,o_read_pre : std_logic; - SIGNAL o_readlev,o_copylev : natural RANGE 0 TO 2; - SIGNAL o_hburst,o_hbcpt : natural RANGE 0 TO 31; - SIGNAL o_fload : natural RANGE 0 TO 3; - SIGNAL o_acpt,o_acpt1,o_acpt2,o_acpt3,o_acpt4 : natural RANGE 0 TO 15; -- Alternance pixels FIFO - SIGNAL o_dshi : natural RANGE 0 TO 3; - SIGNAL o_first,o_last,o_last1,o_last2 : std_logic; - SIGNAL o_lastt1,o_lastt2,o_lastt3,o_lastt4 : std_logic; - SIGNAL o_alt,o_altx : unsigned(3 DOWNTO 0); - SIGNAL o_hdown,o_vdown : std_logic; - SIGNAL o_primv,o_lastv,o_bibv : unsigned(0 TO 2); - TYPE arr_uint4 IS ARRAY (natural RANGE <>) OF natural RANGE 0 TO 15; - SIGNAL o_off : arr_uint4(0 TO 2); - SIGNAL o_bibu : std_logic :='0'; - SIGNAL o_dcptv : arr_uint12(1 TO 14); - SIGNAL o_dcpt : uint12; - SIGNAL o_hpixs,o_hpix0,o_hpix1,o_hpix2,o_hpix3 : type_pix; - SIGNAL o_hpixq : arr_pixq(2 TO 8); - ATTRIBUTE ramstyle OF o_hpixq : SIGNAL IS "logic"; -- avoid blockram shift register - SIGNAL o_vpixq, o_vpixq_pre : arr_pix(0 TO 3); - SIGNAL o_vpix_outer : arr_pix(0 TO 2); - SIGNAL o_vpix_inner : arr_pix(0 TO 6); - - - SIGNAL o_vpe : std_logic; - SIGNAL o_div : arr_div(0 TO 2); --uint12; - SIGNAL o_dir : arr_frac(0 TO 2); - ATTRIBUTE ramstyle OF o_div, o_dir : SIGNAL IS "logic"; -- avoid blockram shift register - SIGNAL o_vdivi : unsigned(12 DOWNTO 0); - SIGNAL o_vdivr : unsigned(24 DOWNTO 0); - SIGNAL o_divstart : std_logic; - SIGNAL o_divrun : std_logic; - SIGNAL o_hacpt,o_vacpt : unsigned(11 DOWNTO 0); - SIGNAL o_vacptl : unsigned(1 DOWNTO 0); - - ----------------------------------------------------------------------------- - FUNCTION shift_ishift(shift : unsigned(0 TO 119); - pix : type_pix; - format : unsigned(1 DOWNTO 0)) RETURN unsigned IS - BEGIN - CASE format IS - WHEN "01" => -- 24bpp - RETURN shift(24 TO 119) & pix.r & pix.g & pix.b; - WHEN "10" => -- 32bpp - RETURN shift(32 TO 119) & pix.r & pix.g & pix.b & x"00"; - WHEN OTHERS => -- 16bpp 565 - RETURN shift(16 TO 119) & - pix.g(4 DOWNTO 2) & pix.r(7 DOWNTO 3) & - pix.b(7 DOWNTO 3) & pix.g(7 DOWNTO 5); - END CASE; - END FUNCTION; - - FUNCTION shift_ipack( i_dw : unsigned(N_DW-1 DOWNTO 0); - acpt : natural RANGE 0 TO 15; - shift : unsigned(0 TO 119); - pix : type_pix; - format : unsigned(1 DOWNTO 0)) RETURN unsigned IS - VARIABLE dw : unsigned(N_DW-1 DOWNTO 0); - BEGIN - dw:=i_dw; - CASE format IS - WHEN "01" => -- 24bpp - IF N_DW=128 THEN - IF acpt=5 THEN dw:=shift(0 TO 119) & pix.r; - ELSIF acpt=10 THEN dw:=shift(8 TO 119) & pix.r & pix.g; - ELSIF acpt=15 THEN dw:=shift(16 TO 119) & pix.r & pix.g & pix.b; - END IF; - ELSE -- N_DW=64 - IF (acpt MOD 8)=2 THEN dw:=shift(72 TO 119) & pix.r & pix.g; - ELSIF (acpt MOD 8)=5 THEN dw:=shift(64 TO 119) & pix.r; - ELSIF (acpt MOD 8)=7 THEN dw:=shift(80 TO 119) & pix.r & pix.g & pix.b; - END IF; - END IF; - WHEN "10" => -- 32bpp - IF (N_DW=128 AND (acpt MOD 4)=3) OR (N_DW=64 AND (acpt MOD 8)=7) THEN - dw:=shift(128-N_DW+24 TO 119) & pix.r & pix.g & pix.b & x"00"; - END IF; - WHEN OTHERS => -- 16bpp 565 - IF (N_DW=128 AND (acpt MOD 8)=7) OR (N_DW=64 AND (acpt MOD 4)=3) THEN - dw:=shift(128-N_DW+8 TO 119) & pix.g(4 DOWNTO 2) & pix.r(7 DOWNTO 3) & - pix.b(7 DOWNTO 3) & pix.g(7 DOWNTO 5); - END IF; - END CASE; - RETURN dw; - END FUNCTION; - - FUNCTION shift_inext (acpt : natural RANGE 0 TO 15; - format : unsigned(1 DOWNTO 0)) RETURN boolean IS - BEGIN - CASE format IS - WHEN "01" => -- 24bpp - RETURN (N_DW=128 AND (acpt=5 OR acpt=10 OR acpt=15)) OR - (N_DW=64 AND ((acpt MOD 8)=2 OR (acpt MOD 8)=5 OR (acpt MOD 8)=7)); - WHEN "10" => -- 32bpp - RETURN (N_DW=128 AND ((acpt MOD 4)=3)) OR - (N_DW=64 AND ((acpt MOD 2)=1)); - WHEN OTHERS => -- 16bpp - RETURN (N_DW=128 AND ((acpt MOD 8)=7)) OR - (N_DW=64 AND ((acpt MOD 4)=3)); - END CASE; - END FUNCTION; - - FUNCTION shift_opack(acpt : natural RANGE 0 TO 15; - shift : unsigned(0 TO N_DW+15); - dr : unsigned(N_DW-1 DOWNTO 0); - format : unsigned(5 DOWNTO 0)) RETURN unsigned IS - VARIABLE shift_v : unsigned(0 TO N_DW+15); - BEGIN - CASE format(2 DOWNTO 0) IS - WHEN "011" => -- 8bpp - IF (N_DW=128 AND acpt=0) OR (N_DW=64 AND (acpt MOD 8)=0) THEN - shift_v:=dr & dr(15 DOWNTO 0); - ELSE - shift_v:=shift(8 TO N_DW+15) & dr(7 DOWNTO 0); - END IF; - - WHEN "100" => -- 16bpp - IF (N_DW=128 AND (acpt MOD 8)=0) OR (N_DW=64 AND (acpt MOD 4)=0) THEN - shift_v:=dr & dr(15 DOWNTO 0); - ELSE - shift_v:=shift(16 TO N_DW+15) & dr(15 DOWNTO 0); - END IF; - - WHEN "101" => -- 24bpp - IF N_DW=128 THEN - IF acpt=0 THEN - shift_v:=dr & dr(15 DOWNTO 0); - ELSIF acpt=5 THEN - shift_v:=shift(24 TO 31) & dr & dr(7 DOWNTO 0); - ELSIF acpt=10 THEN - shift_v:=shift(24 TO 39) & dr; - ELSE - shift_v:=shift(24 TO N_DW+15) & dr(23 DOWNTO 0); - END IF; - ELSE -- N_DW=64 - IF (acpt MOD 8)=0 THEN - shift_v:=dr & dr(15 DOWNTO 0); - ELSIF (acpt MOD 8)=2 THEN - shift_v:=shift(24 TO 39) & dr; - ELSIF (acpt MOD 8)=5 THEN - shift_v:=shift(24 TO 31) & dr & dr(7 DOWNTO 0); - ELSE - shift_v:=shift(24 TO N_DW+15) & dr(23 DOWNTO 0); - END IF; - END IF; - WHEN OTHERS => -- 32bpp - IF (N_DW=128 AND (acpt MOD 4)=0) OR (N_DW=64 AND (acpt MOD 2)=0) THEN - shift_v:=dr & dr(15 DOWNTO 0); - ELSE - shift_v:=shift(32 TO N_DW+15) & dr(31 DOWNTO 0); - END IF; - END CASE; - RETURN shift_v; - END FUNCTION; - - FUNCTION shift_onext (acpt : natural RANGE 0 TO 15; - format : unsigned(5 DOWNTO 0)) RETURN boolean IS - BEGIN - CASE format(2 DOWNTO 0) IS - WHEN "011" => -- 8bpp - RETURN (N_DW=128 AND acpt=0) OR - (N_DW=64 AND ((acpt MOD 8)=0)); - WHEN "100" => -- 16bpp - RETURN (N_DW=128 AND ((acpt MOD 8)=0)) OR - (N_DW=64 AND ((acpt MOD 4)=0)); - WHEN "101" => -- 24bpp - RETURN (N_DW=128 AND (acpt=0 OR acpt=5 OR acpt=10)) OR - (N_DW=64 AND ((acpt MOD 8)=0 OR (acpt MOD 8)=2 OR (acpt MOD 8)=5)); - WHEN OTHERS => -- 32bpp - RETURN (N_DW=128 AND ((acpt MOD 4)=0)) OR - (N_DW=64 AND ((acpt MOD 2)=0)); - END CASE; - END FUNCTION; - - FUNCTION shift_opix (shift : unsigned(0 TO N_DW+15); - format : unsigned(5 DOWNTO 0)) RETURN type_pix IS - BEGIN - CASE format(3 DOWNTO 0) IS - WHEN "0100" => -- 16bpp 565 - RETURN (b=>shift(8 TO 12) & shift(8 TO 10), - g=>shift(13 TO 15) & shift(0 TO 2) & shift(13 TO 14), - r=>shift(3 TO 7) & shift(3 TO 5)); - WHEN "1100" => -- 16bpp 1555 - RETURN (b=>shift(9 TO 13) & shift(9 TO 11), - g=>shift(14 TO 15) & shift(0 TO 2) & shift(14 TO 15) & shift(0), - r=>shift(3 TO 7) & shift(3 TO 5)); - WHEN "0101" | "0110" => -- 24bpp / 32bpp - RETURN (r=>shift(0 TO 7),g=>shift(8 TO 15),b=>shift(16 TO 23)); - - WHEN OTHERS => - RETURN (r=>shift(0 TO 7),g=>shift(8 TO 15),b=>shift(16 TO 23)); - - END CASE; - END FUNCTION; - - FUNCTION pixoffset(adrs : unsigned(31 DOWNTO 0); - format : unsigned (5 DOWNTO 0)) RETURN natural IS - BEGIN - CASE format(2 DOWNTO 0) IS - WHEN "011" => -- 8bbp - RETURN to_integer(adrs(NB_LA-1 DOWNTO 0)); - WHEN "100" => -- 16bpp 565 - RETURN to_integer(adrs(NB_LA-1 DOWNTO 1)); - WHEN OTHERS => -- 32bpp - RETURN to_integer(adrs(NB_LA-1 DOWNTO 2)); - END CASE; - END FUNCTION; - - FUNCTION swap(d : unsigned(N_DW-1 DOWNTO 0)) RETURN unsigned IS - VARIABLE e : unsigned(N_DW-1 DOWNTO 0); - BEGIN - IF BYTESWAP THEN - FOR i IN 0 TO N_DW/8-1 LOOP - e(i*8+7 DOWNTO i*8):=d(N_DW-i*8-1 DOWNTO N_DW-i*8-8); - END LOOP; - RETURN e; - ELSE - RETURN d; - END IF; - END FUNCTION swap; - - ----------------------------------------------------------------------------- - FUNCTION altx (a : unsigned(1 DOWNTO 0)) RETURN unsigned IS - BEGIN - CASE a IS - WHEN "00" => RETURN "0001"; - WHEN "01" => RETURN "0010"; - WHEN "10" => RETURN "0100"; - WHEN OTHERS => RETURN "1000"; - END CASE; - END FUNCTION; - - ----------------------------------------------------------------------------- - FUNCTION bound(a : unsigned; - s : natural) RETURN unsigned IS - BEGIN - IF a(a'left)='1' THEN - RETURN x"00"; - ELSIF a(a'left DOWNTO s)/=0 THEN - RETURN x"FF"; - ELSE - RETURN a(s-1 DOWNTO s-8); - END IF; - END FUNCTION bound; - - ----------------------------------------------------------------------------- - -- Nearest - FUNCTION near_frac(f : unsigned) RETURN unsigned IS - VARIABLE x : unsigned(FRAC-1 DOWNTO 0); - BEGIN - x:=(OTHERS =>f(f'left)); - RETURN x; - END FUNCTION; - - SIGNAL o_h_near_frac,o_v_near_frac : unsigned(FRAC-1 DOWNTO 0); - SIGNAL o_h_bil_frac,o_v_bil_frac : unsigned(FRAC-1 DOWNTO 0); - SIGNAL o_h_bil_pix,o_v_bil_pix : type_pix; - - ----------------------------------------------------------------------------- - -- Nearest + Bilinear + Sharp Bilinear - FUNCTION bil_frac(f : unsigned) RETURN unsigned IS - BEGIN - RETURN f(f'left DOWNTO f'left+1-FRAC); - END FUNCTION; - - TYPE type_bil_t IS RECORD - r,g,b : unsigned(8+FRAC DOWNTO 0); - END RECORD; - - FUNCTION bil_calc(f : unsigned(FRAC-1 DOWNTO 0); - p : arr_pix(0 TO 3)) RETURN type_bil_t IS - VARIABLE fp,fn : unsigned(FRAC DOWNTO 0); - VARIABLE u : unsigned(8+FRAC DOWNTO 0); - VARIABLE x : type_bil_t; - CONSTANT Z : unsigned(FRAC-1 DOWNTO 0):=(OTHERS =>'0'); - BEGIN - fp:=('0' & f) + (Z & f(FRAC-1)); - fn:=('1' & Z) - fp; - u:=p(2).r * fp + p(1).r * fn; - x.r:=u; - u:=p(2).g * fp + p(1).g * fn; - x.g:=u; - u:=p(2).b * fp + p(1).b * fn; - x.b:=u; - RETURN x; - END FUNCTION; - - FUNCTION near_calc(f : unsigned(FRAC-1 DOWNTO 0); - p : arr_pix(0 TO 3)) RETURN type_bil_t IS - VARIABLE fp,fn : unsigned(FRAC DOWNTO 0); - VARIABLE u : unsigned(8+FRAC DOWNTO 0); - VARIABLE x : type_bil_t; - CONSTANT Z : unsigned(FRAC-1 DOWNTO 0):=(OTHERS =>'0'); - BEGIN - IF f(FRAC-1)='0' THEN - x.r := '0' & p(1).r & Z; - x.g := '0' & p(1).g & Z; - x.b := '0' & p(1).b & Z; - ELSE - x.r := '0' & p(2).r & Z; - x.g := '0' & p(2).g & Z; - x.b := '0' & p(2).b & Z; - END IF; - RETURN x; - END FUNCTION; - - SIGNAL o_h_bil_t,o_v_bil_t : type_bil_t; - SIGNAL o_h_near_t,o_v_near_t : type_bil_t; - SIGNAL i_h_bil_t : type_bil_t; - - ----------------------------------------------------------------------------- - -- Sharp Bilinear - -- <0.5 : x*x*x*4 - -- >0.5 : 1 - (1-x)*(1-x)*(1-x)*4 - - TYPE type_sbil_tt IS RECORD - f : unsigned(FRAC-1 DOWNTO 0); - s : unsigned(FRAC-1 DOWNTO 0); - END RECORD; - - SIGNAL o_h_sbil_t,o_v_sbil_t : type_sbil_tt; - - FUNCTION sbil_frac1(f : unsigned(11 DOWNTO 0)) RETURN type_sbil_tt IS - VARIABLE u : unsigned(FRAC-1 DOWNTO 0); - VARIABLE v : unsigned(2*FRAC-1 DOWNTO 0); - VARIABLE x : type_sbil_tt; - BEGIN - IF f(11)='0' THEN - u:=f(11 DOWNTO 12-FRAC); - ELSE - u:=NOT f(11 DOWNTO 12-FRAC); - END IF; - v:=u*u; - x.f:=u; - x.s:=v(2*FRAC-2 DOWNTO FRAC-1); - RETURN x; - END FUNCTION; - - FUNCTION sbil_frac2(f : unsigned(11 DOWNTO 0); - t : type_sbil_tt) RETURN unsigned IS - VARIABLE v : unsigned(2*FRAC-1 DOWNTO 0); - BEGIN - v:=t.f*t.s; - IF f(11)='0' THEN - RETURN v(2*FRAC-2 DOWNTO FRAC-1); - ELSE - RETURN NOT v(2*FRAC-2 DOWNTO FRAC-1); - END IF; - END FUNCTION; - - ----------------------------------------------------------------------------- - -- Bicubic - TYPE type_bic_abcd IS RECORD - a : unsigned(7 DOWNTO 0); -- 0.8 - b : signed(8 DOWNTO 0); -- 0.9 - c : signed(11 DOWNTO 0); -- 3.9 - d : signed(10 DOWNTO 0); -- 2.9 - xx : signed(8 DOWNTO 0); -- X.X 1.8 - END RECORD; - TYPE type_bic_pix_abcd IS RECORD - r,g,b : type_bic_abcd; - END RECORD; - TYPE type_bic_tt1 IS RECORD -- Intermediate result - r_bx,g_bx,b_bx : signed(8 DOWNTO 0); -- B.X 1.8 - r_cxx,g_cxx,b_cxx : signed(11 DOWNTO 0); -- C.XX 3.9 - r_dxx,g_dxx,b_dxx : signed(10 DOWNTO 0); -- D.XX 2.9 - END RECORD; - TYPE type_bic_tt2 IS RECORD -- Intermediate result - r_abxcxx,g_abxcxx,b_abxcxx : signed(9 DOWNTO 0); -- A + B.X + C.XX 2.8 - r_dxxx,g_dxxx,b_dxxx : signed(9 DOWNTO 0); -- D.X.X.X 2.8 - END RECORD; - - ---------------------------------------------------------- - -- Y = A + B.X + C.X.X + D.X.X.X = A + X.(B + X.(C + X.D)) - -- A = Y(0) 0 .. 1 unsigned - -- B = Y(1)/2 - Y(-1)/2 -1/2 .. +1/2 signed - -- C = Y(-1) - 5*Y(0)/2 + 2*Y(1) - Y(2)/2 -3 .. +3 signed - -- D = -Y(-1)/2 + 3*Y(0)/2 - 3*Y(1)/2 + Y(2)/2 -2 .. +2 signed - - FUNCTION bic_calc0(f : unsigned(11 DOWNTO 0); - pm,p0,p1,p2 : unsigned(7 DOWNTO 0)) RETURN type_bic_abcd IS - VARIABLE xx : signed(2*FRAC+1 DOWNTO 0); -- 2.(2*FRAC) - BEGIN - xx := signed('0' & f(11 DOWNTO 12-FRAC)) * - signed('0' & f(11 DOWNTO 12-FRAC)); -- 2.(2*FRAC) - RETURN type_bic_abcd'( - a=>p0,-- 0.8 - b=>signed(('0' & p1) - ('0' & pm)), -- 0.9 - c=>signed(("000" & pm & '0') - ("00" & p0 & "00") - ("0000" & p0) + - ("00" & p1 & "00") - ("0000" & p2)), -- 3.9 - d=>signed(("00" & p0 & '0') - ("00" & p1 & '0') - ("000" & p1) + - ("000" & p0) + ("000" & p2) - ("000" & pm)), -- 2.9 - xx=>xx(2*FRAC DOWNTO 2*FRAC-8)); -- 1.8 - END FUNCTION; - FUNCTION bic_calc0(f : unsigned(11 DOWNTO 0); - p : arr_pix(0 TO 3)) RETURN type_bic_pix_abcd IS - BEGIN - RETURN type_bic_pix_abcd'( r=>bic_calc0(f,p(0).r,p(1).r,p(2).r,p(3).r), - g=>bic_calc0(f,p(0).g,p(1).g,p(2).g,p(3).g), - b=>bic_calc0(f,p(0).b,p(1).b,p(2).b,p(3).b)); - END FUNCTION; - - ---------------------------------------------------------- - -- Calc : B.X, C.XX, D.XX - FUNCTION bic_calc1(f : unsigned(11 DOWNTO 0); - abcd : type_bic_pix_abcd) RETURN type_bic_tt1 IS - VARIABLE t : type_bic_tt1; - VARIABLE bx : signed(9+FRAC DOWNTO 0); -- 1.(FRAC+9) - VARIABLE cxx : signed(20 DOWNTO 0); -- 4.17 - VARIABLE dxx : signed(19 DOWNTO 0); -- 3.17 - BEGIN - bx := abcd.r.b * signed('0' & f(11 DOWNTO 12-FRAC)); -- 1.(FRAC+9) - t.r_bx:=bx(9+FRAC DOWNTO 9+FRAC-8); -- 1.8 - cxx:= abcd.r.c * abcd.r.xx; -- 3.9 * 1.8 = 4.17 - t.r_cxx:=cxx(19 DOWNTO 8); -- 3.9 - dxx:= abcd.r.d * abcd.r.xx; -- 2.9 * 1.8 = 3.17 - t.r_dxx:=dxx(18 DOWNTO 8); -- 2.9 - bx := abcd.g.b * signed('0' & f(11 DOWNTO 12-FRAC)); -- 1.(FRAC+9) - t.g_bx:=bx(9+FRAC DOWNTO 9+FRAC-8); -- 1.8 - cxx:= abcd.g.c * abcd.g.xx; -- 3.9 * 1.8 = 4.17 - t.g_cxx:=cxx(19 DOWNTO 8); -- 3.9 - dxx:= abcd.g.d * abcd.g.xx; -- 2.9 * 1.8 = 3.17 - t.g_dxx:=dxx(18 DOWNTO 8); -- 2.9 - bx := abcd.b.b * signed('0' & f(11 DOWNTO 12-FRAC)); -- 1.(FRAC+9) - t.b_bx:=bx(9+FRAC DOWNTO 9+FRAC-8); -- 1.8 - cxx:= abcd.b.c * abcd.b.xx; -- 3.9 * 1.8 = 4.17 - t.b_cxx:=cxx(19 DOWNTO 8); -- 3.9 - dxx:= abcd.b.d * abcd.b.xx; -- 2.9 * 1.8 = 3.17 - t.b_dxx:=dxx(18 DOWNTO 8); -- 2.9 - RETURN t; - END FUNCTION; - - ---------------------------------------------------------- - -- Calc A + BX + CXX , X.DXX - FUNCTION bic_calc2(f : unsigned(11 DOWNTO 0); - t : type_bic_tt1; - abcd : type_bic_pix_abcd) RETURN type_bic_tt2 IS - VARIABLE u : type_bic_tt2; - VARIABLE x : signed(11+FRAC DOWNTO 0); -- 3.(9+FRAC) - BEGIN - u.r_abxcxx:=(t.r_bx(8) & t.r_bx) + ("00" & signed(abcd.r.a)) + t.r_cxx(10 DOWNTO 1); -- 2.8 - u.g_abxcxx:=(t.g_bx(8) & t.g_bx) + ("00" & signed(abcd.g.a)) + t.g_cxx(10 DOWNTO 1); -- 2.8 - u.b_abxcxx:=(t.b_bx(8) & t.b_bx) + ("00" & signed(abcd.b.a)) + t.b_cxx(10 DOWNTO 1); -- 2.8 - - x:=t.r_dxx * signed('0' & f(11 DOWNTO 12-FRAC)); --2.9 * 1.FRAC =3.(9+FRAC) - u.r_dxxx:=x(10+FRAC DOWNTO 9+FRAC-8); -- 2.8 - x:=t.g_dxx * signed('0' & f(11 DOWNTO 12-FRAC)); --2.9 * 1.FRAC =3.(9+FRAC) - u.g_dxxx:=x(10+FRAC DOWNTO 9+FRAC-8); -- 2.8 - x:=t.b_dxx * signed('0' & f(11 DOWNTO 12-FRAC)); --2.9 * 1.FRAC =3.(9+FRAC) - u.b_dxxx:=x(10+FRAC DOWNTO 9+FRAC-8); -- 2.8 - RETURN u; - END FUNCTION; - - ---------------------------------------------------------- - -- Calc (A + BX + CXX) + (DXXX) - FUNCTION bic_calc3(f : unsigned(11 DOWNTO 0); - t : type_bic_tt2; - abcd : type_bic_pix_abcd) RETURN type_pix IS - VARIABLE x : type_pix; - VARIABLE v : signed(9 DOWNTO 0); -- 2.8 - BEGIN - v:=t.r_abxcxx + t.r_dxxx; - x.r:=bound(unsigned(v),8); - v:=t.g_abxcxx + t.g_dxxx; - x.g:=bound(unsigned(v),8); - v:=t.b_abxcxx + t.b_dxxx; - x.b:=bound(unsigned(v),8); - RETURN x; - END FUNCTION; - - ----------------------------------------------------------------------------- - SIGNAL o_h_bic_pix,o_v_bic_pix : type_pix; - SIGNAL o_h_bic_abcd1,o_h_bic_abcd2 : type_bic_pix_abcd; - SIGNAL o_v_bic_abcd1,o_v_bic_abcd2 : type_bic_pix_abcd; - SIGNAL o_h_bic_tt1,o_v_bic_tt1 : type_bic_tt1; - SIGNAL o_h_bic_tt2,o_v_bic_tt2 : type_bic_tt2; - - ----------------------------------------------------------------------------- - -- Polyphase - -- 2.7 - TYPE poly_phase_t IS RECORD - t0, t1, t2, t3 : signed(9 DOWNTO 0); - END RECORD; - - -- 4.14 - TYPE poly_phase_interp_t IS RECORD - t0, t1, t2, t3 : signed(17 DOWNTO 0); - END RECORD; - - -- 5.22 - TYPE type_poly_t IS RECORD - r0,r1,b0,b1,g0,g1 : signed(26 DOWNTO 0); - END RECORD; - - SIGNAL o_h_poly_mem : arr_uv40(0 TO 2**FRAC-1); - SIGNAL o_v_poly_mem : arr_uv40(0 TO 2**FRAC-1); - SIGNAL o_a_poly_mem : arr_uv40(0 TO 2**FRAC-1); - ATTRIBUTE ramstyle OF o_h_poly_mem : SIGNAL IS "no_rw_check"; - ATTRIBUTE ramstyle OF o_v_poly_mem : SIGNAL IS "no_rw_check"; - ATTRIBUTE ramstyle OF o_a_poly_mem : SIGNAL IS "no_rw_check"; - SIGNAL o_a_poly_addr, o_v_poly_addr : integer RANGE 0 TO 2**FRAC-1; - SIGNAL o_h_poly_phase_a,o_h_poly_phase_a2,o_h_poly_phase_a3, o_h_poly_phase_a4, o_h_poly_phase_a5 : poly_phase_t; - SIGNAL o_v_poly_phase_a,o_v_poly_phase_a2,o_v_poly_phase_a3, o_v_poly_phase_a4, o_v_poly_phase_a5 : poly_phase_t; - SIGNAL o_poly_phase_a, o_poly_phase_a2, o_poly_phase_a3 : poly_phase_t; - SIGNAL o_poly_phase_b,o_poly_phase_b2,o_poly_phase_b3 : poly_phase_t; - SIGNAL o_v_poly_phase, o_v_poly_phase2, o_h_poly_phase, o_poly_phase, o_poly_phase1 : poly_phase_interp_t; - SIGNAL o_v_poly_pix, o_h_poly_pix, o_h_lum_pix, o_v_lum_pix : type_pix; - SIGNAL o_poly_lum, o_poly_lum1 : unsigned(7 DOWNTO 0); - SIGNAL o_poly_lerp_ta, o_poly_lerp_tb : signed(9 DOWNTO 0); - SIGNAL o_h_poly_t,o_h_poly_t2,o_v_poly_t : type_poly_t; - - SIGNAL o_v_poly_adaptive, o_h_poly_adaptive, o_v_poly_use_adaptive, o_h_poly_use_adaptive : std_logic; - SIGNAL poly_wr_mode : std_logic_vector(2 DOWNTO 0); - SIGNAL poly_tdw : unsigned(39 DOWNTO 0); - SIGNAL poly_a2 : unsigned(FRAC-1 DOWNTO 0); - - FUNCTION poly_unpack(a : unsigned(39 DOWNTO 0)) RETURN poly_phase_t IS - VARIABLE v : poly_phase_t; - BEGIN - v.t0 := signed(a(39 DOWNTO 30)); - v.t1 := signed(a(29 DOWNTO 20)); - v.t2 := signed(a(19 DOWNTO 10)); - v.t3 := signed(a( 9 DOWNTO 0)); - RETURN v; - END FUNCTION; - - -- 6 DSP 18*18 + 18*18 - FUNCTION poly_calc(fi : poly_phase_interp_t; - p : arr_pix(0 TO 3)) RETURN type_poly_t IS - VARIABLE t : type_poly_t; - BEGIN - -- 3.15 * 1.8 = 4.23 - t.r0:=(fi.t0 * signed('0' & p(0).r) + - fi.t1 * signed('0' & p(1).r)); - t.r1:=(fi.t2 * signed('0' & p(2).r) + - fi.t3 * signed('0' & p(3).r)); - t.g0:=(fi.t0 * signed('0' & p(0).g) + - fi.t1 * signed('0' & p(1).g)); - t.g1:=(fi.t2 * signed('0' & p(2).g) + - fi.t3 * signed('0' & p(3).g)); - t.b0:=(fi.t0 * signed('0' & p(0).b) + - fi.t1 * signed('0' & p(1).b)); - t.b1:=(fi.t2 * signed('0' & p(2).b) + - fi.t3 * signed('0' & p(3).b)); - RETURN t; - END FUNCTION; - - FUNCTION poly_final(t : type_poly_t) RETURN type_pix IS - VARIABLE p : type_pix; - BEGIN - p.r:=bound(unsigned(t.r0(26 DOWNTO 8)+t.r1(26 DOWNTO 8)),15); - p.g:=bound(unsigned(t.g0(26 DOWNTO 8)+t.g1(26 DOWNTO 8)),15); - p.b:=bound(unsigned(t.b0(26 DOWNTO 8)+t.b1(26 DOWNTO 8)),15); - RETURN p; - END FUNCTION; - - -- 4 DSP 18*18 + 18*18 - FUNCTION poly_lerp(a : poly_phase_t; - b : poly_phase_t; - ta : SIGNED(9 DOWNTO 0); - tb : SIGNED(9 DOWNTO 0)) RETURN poly_phase_interp_t IS - VARIABLE v : poly_phase_interp_t; - VARIABLE t0,t1,t2,t3 : signed(19 DOWNTO 0); - BEGIN - -- 2.8 * 2.8 = 4.16 - t0 := (a.t0 * ta) + (b.t0 * tb); - t1 := (a.t1 * ta) + (b.t1 * tb); - t2 := (a.t2 * ta) + (b.t2 * tb); - t3 := (a.t3 * ta) + (b.t3 * tb); - - -- 4.16 -> 3.15 - v.t0 := t0(18 DOWNTO 1); - v.t1 := t1(18 DOWNTO 1); - v.t2 := t2(18 DOWNTO 1); - v.t3 := t3(18 DOWNTO 1); - - RETURN v; - END FUNCTION; - - FUNCTION poly_cvt(a : poly_phase_t) RETURN poly_phase_interp_t IS - VARIABLE v : poly_phase_interp_t; - BEGIN - v.t0 := resize(signed( a.t0 & "0000000" ), v.t0'length); - v.t1 := resize(signed( a.t1 & "0000000" ), v.t1'length); - v.t2 := resize(signed( a.t2 & "0000000" ), v.t2'length); - v.t3 := resize(signed( a.t3 & "0000000" ), v.t3'length); - RETURN v; - END FUNCTION; - - -- Nearest neighbor polyphase ceoffs - FUNCTION poly_nn(frac : unsigned(FRAC-1 DOWNTO 0)) RETURN poly_phase_t IS - VARIABLE v : poly_phase_t; - BEGIN - IF frac(frac'left)='0' THEN - v := (t1=>to_signed(256, 10), OTHERS=>to_signed(0, 10)); - ELSE - v := (t2=>to_signed(256, 10), OTHERS=>to_signed(0, 10)); - END IF; - RETURN v; - END FUNCTION; - - - FUNCTION poly_lum(p : type_pix) RETURN unsigned IS - VARIABLE v : UNSIGNED(7 DOWNTO 0); - BEGIN - -- 0.375 R + 0.5 G + 0.125 B - --v := ("00" & p.r(7 DOWNTO 2)) + ("000" & p.r(7 DOWNTO 3)) + ("0" & p.g(7 DOWNTO 1)) + ("000" & p.b(7 DOWNTO 3)); - - -- 0.25 R + 0.5 G + 0.25 B - -- v := ( ("00" & p.r(7 DOWNTO 2)) + ("0" & p.g(7 DOWNTO 1)) + ("00" & p.b(7 DOWNTO 2)) ); - - -- Just OR them all together - --v := (p.r OR p.g OR p.b); - - -- Maximum - IF p.r > p.g THEN - v := p.r; - ELSE - v := p.g; - END IF; - - IF p.b > v THEN - v := p.b; - END IF; - - -- 100% - -- v := "1111111"; - - RETURN v; - END FUNCTION; -BEGIN - - ----------------------------------------------------------------------------- - i_reset_na<='0' WHEN reset_na='0' ELSE '1' WHEN rising_edge(i_clk); - o_reset_na<='0' WHEN reset_na='0' ELSE '1' WHEN rising_edge(o_clk); - avl_reset_na<='0' WHEN reset_na='0' ELSE '1' WHEN rising_edge(avl_clk); - - ----------------------------------------------------------------------------- - -- Input pixels FIFO and shreg - InAT:PROCESS(i_clk,i_reset_na) IS - CONSTANT Z : unsigned(FRAC-1 DOWNTO 0):=(OTHERS =>'0'); - VARIABLE frac_v : unsigned(FRAC-1 DOWNTO 0); - VARIABLE div_v : unsigned(16 DOWNTO 0); - VARIABLE dir_v : unsigned(11 DOWNTO 0); - VARIABLE bil_t_v : type_bil_t; - BEGIN - IF i_reset_na='0' THEN - i_write<='0'; - - ELSIF rising_edge(i_clk) THEN - i_push<='0'; - i_pushhead<='0'; - i_eol<='0'; -- End Of Line - i_freeze <=freeze; -- - i_iauto<=iauto; -- - i_wreq<='0'; - i_wr<='0'; - - ------------------------------------------------------ - i_head(127 DOWNTO 120)<=x"01"; -- Header type - i_head(119 DOWNTO 112)<="000000" & i_format; -- Header format - i_head(111 DOWNTO 96)<="0000" & to_unsigned(N_BURST,12); -- Header size - i_head(95 DOWNTO 80)<=x"0000"; -- Attributes. TBD - i_head(80)<=i_inter; - i_head(81)<=i_flm; - i_head(82)<=i_hdown; - i_head(83)<=i_vdown; - i_head(84)<=i_mode(3); - i_head(87 DOWNTO 85)<=i_count; - i_head(79 DOWNTO 64)<="0000" & to_unsigned(i_hrsize,12); -- Image width - i_head(63 DOWNTO 48)<="0000" & to_unsigned(i_vrsize,12); -- Image height - i_head(47 DOWNTO 32)<= to_unsigned(N_BURST * i_hburst,16); -- Line Length. Bytes - i_head(31 DOWNTO 16)<="0000" & to_unsigned(i_ohsize,12); - i_head(15 DOWNTO 0) <="0000" & to_unsigned(i_ovsize,12); - - ------------------------------------------------------ - i_ppix<=(i_r,i_g,i_b); - i_pvs<=i_vs; - i_pfl<=i_fl; - i_pde<=i_de; - i_pce<=i_ce; - - ------------------------------------------------------ - IF i_pce='1' THEN - ---------------------------------------------------- - i_vs_pre<=i_pvs; - i_de_pre<=i_pde; - i_fl_pre<=i_pfl; - - ---------------------------------------------------- - -- Detect interlaced video - IF NOT INTER THEN - i_intercnt<=0; - ELSIF i_pfl/=i_fl_pre THEN - i_intercnt<=3; - ELSIF i_pvs='1' AND i_vs_pre='0' AND i_intercnt>0 THEN - i_intercnt<=i_intercnt-1; - END IF; - i_inter<=to_std_logic(i_intercnt>0); - - ---------------------------------------------------- - IF i_pvs='1' AND i_vs_pre='0' THEN - i_sof<='1'; - END IF; - - IF i_pde='1' AND i_de_pre='0' THEN - i_flm<=i_pfl; - END IF; - - IF i_pde='1' AND i_sof='1' THEN - i_sof<='0'; - i_vcpt<=0; - IF i_inter='1' AND i_flm='0' AND i_half='0' AND INTER THEN - i_line<='1'; - i_adrsi<=to_unsigned(N_BURST * i_hburst,32) + - to_unsigned(N_BURST * to_integer( - unsigned'("00") & to_std_logic(HEADER)),32); - ELSE - i_line<='0'; - i_adrsi<=to_unsigned(N_BURST * to_integer( - unsigned'("00") & to_std_logic(HEADER)),32); - END IF; - END IF; - - i_ven<=to_std_logic(i_hcpt>=i_hmin AND i_hcpt<=i_hmax AND - i_vcpt>=i_vmin AND i_vcpt<=i_vmax); - - -- Detects end of frame for triple buffering. - i_endframe0<=i_vs AND (NOT i_inter OR i_flm); - i_endframe1<=i_vs AND (NOT i_inter OR NOT i_flm); - - i_vss<=to_std_logic(i_vcpt>=i_vmin AND i_vcpt<=i_vmax); - - ---------------------------------------------------- - IF i_pde='1' AND i_de_pre='0' THEN - i_vimax<=i_vcpt; - i_hcpt<=0; - ELSE - i_hcpt<=(i_hcpt+1) MOD 4096; - END IF; - - IF i_pde='0' AND i_de_pre='1' THEN - i_himax<=i_hcpt; - END IF; - - IF i_iauto='1' THEN - -- Auto-size - i_hmin<=0; - i_hmax<=i_himax; - i_vmin<=0; - IF i_pvs='1' AND i_vs_pre='0' AND (i_inter='0' OR i_pfl='0') THEN - i_vmax<=i_vimax; - END IF; - ELSE - -- Forced image - i_hmin<=himin; -- - i_hmax<=himax; -- - i_vmin<=vimin; -- - IF i_pvs='1' AND i_vs_pre='0' AND (i_inter='0' OR i_pfl='0') THEN - i_vmax<=vimax; -- - END IF; - END IF; - - IF i_pvs='1' AND i_vs_pre='0' AND (i_inter='0' OR i_pfl='0') THEN - i_vdmax<=i_vimax; - END IF; - i_hdmax<=i_himax; - - IF i_format="00" OR i_format="11" THEN -- 16bpp - i_hburst<=(i_hrsize*2 + N_BURST - 1) / N_BURST; - ELSIF i_format="01" THEN -- 24bpp - i_hburst<=(i_hrsize*3 + N_BURST - 1) / N_BURST; - ELSE -- 32bpp - i_hburst<=(i_hrsize*4 + N_BURST - 1) / N_BURST; - END IF; - ---------------------------------------------------- - i_mode<=mode; -- - i_format<=format; -- - - -- Downscaling : Nearest or bilinear - i_bil<=to_std_logic(i_mode(2 DOWNTO 0)/="000" AND NOT DOWNSCALE_NN); - - i_hdown<=to_std_logic(i_hsize>i_ohsize AND DOWNSCALE); --H downscale - i_vdown<=to_std_logic(i_vsize>i_ovsize AND DOWNSCALE); --V downscale - - ---------------------------------------------------- - i_hsize <=(4096+i_hmax-i_hmin+1) MOD 4096; - i_vmaxmin<=(4096+i_vmax-i_vmin+1) MOD 4096; - - IF i_inter='0' THEN - -- Non interlaced - i_vsize<=i_vmaxmin; - i_half <='0'; - ELSIF i_ovsize<2*i_vmaxmin THEN - -- Interlaced, but downscaling, use only half frames - i_vsize<=i_vmaxmin; - i_half <='1'; - ELSE - -- Interlaced : Double image height - i_vsize<=2*i_vmaxmin; - i_half <='0'; - END IF; - - i_ohsize<=o_hsize; -- - i_ovsize<=o_vsize; -- - - ---------------------------------------------------- - -- Downscaling vertical - i_divstart<='0'; - IF i_de_delay=16 THEN - IF (i_vacc + 2*i_ovsize) < 2*i_vsize THEN - i_vacc<=(i_vacc + 2*i_ovsize) MOD 8192; - i_vnp<='0'; - ELSE - i_vacc<=(i_vacc + 2*i_ovsize - 2*i_vsize + 8192) MOD 8192; - i_vnp<='1'; - END IF; - i_divstart<='1'; - - IF i_vcpt=i_vmin THEN - i_vacc<=(i_vsize - i_ovsize + 8192) MOD 8192; - i_vnp<='1'; -- - END IF; - END IF; - - IF i_vdown='0' THEN - i_vnp<='1'; - END IF; - - -- Downscaling horizontal - IF i_ven='1' THEN - IF i_hacc + 2*i_ohsize < 2*i_hsize THEN - i_hacc<=(i_hacc + 2*i_ohsize) MOD 8192; - i_hnp<='0'; -- Skip. pix. - ELSE - i_hacc<=(i_hacc + 2*i_ohsize - 2*i_hsize + 8192) MOD 8192; - i_hnp<='1'; - END IF; - END IF; - IF i_hdown='0' THEN - i_hnp<='1'; - END IF; - - ---------------------------------------------------- - -- Downscaling interpolation - i_hpixp<=i_ppix; - i_hpix0<=i_hpixp; - i_hpix1<=i_hpix0; - i_hpix2<=i_hpix1; - i_hpix3<=i_hpix2; - i_hpix4<=i_hpix3; - - i_hnp1<=i_hnp; i_hnp2<=i_hnp1; i_hnp3<=i_hnp2; i_hnp4<=i_hnp3; - i_ven1<=i_ven; i_ven2<=i_ven1; i_ven3<=i_ven2; i_ven4<=i_ven3; - i_ven5<=i_ven4; i_ven6<=i_ven5; - - -- C1 : DIV 1. Pipelined 4 bits non-restoring divider - dir_v:=x"000"; - div_v:=to_unsigned(i_hacc * 16,17); - - div_v:=div_v-to_unsigned(i_hsize*16,17); - dir_v(11):=NOT div_v(16); - IF div_v(16)='0' THEN - div_v:=div_v-to_unsigned(i_hsize*8,17); - ELSE - div_v:=div_v+to_unsigned(i_hsize*8,17); - END IF; - dir_v(10):=NOT div_v(16); - i_div<=div_v; - i_dir<=dir_v; - - -- C2 : DIV 2. - div_v:=i_div; - dir_v:=i_dir; - IF div_v(16)='0' THEN - div_v:=div_v-to_unsigned(i_hsize*4,17); - ELSE - div_v:=div_v+to_unsigned(i_hsize*4,17); - END IF; - dir_v(9):=NOT div_v(16); - - IF div_v(16)='0' THEN - div_v:=div_v-to_unsigned(i_hsize*2,17); - ELSE - div_v:=div_v+to_unsigned(i_hsize*2,17); - END IF; - dir_v(8):=NOT div_v(16); - i_h_frac<=dir_v; - - -- C4 : Horizontal Bilinear - IF i_bil='0' THEN - frac_v:=near_frac(i_h_frac); - i_h_bil_t<=near_calc(frac_v,(i_hpix2,i_hpix2,i_hpix3,i_hpix3)); - ELSE - frac_v:=bil_frac(i_h_frac); - i_h_bil_t<=bil_calc(frac_v,(i_hpix2,i_hpix2,i_hpix3,i_hpix3)); - END IF; - - i_hpix.r<=bound(i_h_bil_t.r,8+FRAC); - i_hpix.g<=bound(i_h_bil_t.g,8+FRAC); - i_hpix.b<=bound(i_h_bil_t.b,8+FRAC); - - IF i_hdown='0' THEN - i_hpix<=i_hpix4; - END IF; - - -- C5 : Vertical Bilinear - IF i_bil='0' THEN - frac_v:=near_frac(i_v_frac(11 DOWNTO 0)); - bil_t_v:=near_calc(frac_v,(i_hpix,i_hpix,i_ldrm,i_ldrm)); - ELSE - frac_v:=bil_frac(i_v_frac(11 DOWNTO 0)); - bil_t_v:=bil_calc(frac_v,(i_hpix,i_hpix,i_ldrm,i_ldrm)); - END IF; - - i_pix.r<=bound(bil_t_v.r,8+FRAC); - i_pix.g<=bound(bil_t_v.g,8+FRAC); - i_pix.b<=bound(bil_t_v.b,8+FRAC); - - IF i_vdown='0' THEN - i_pix<=i_hpix; - END IF; - - ---------------------------------------------------- - -- VNP : Vert. downscaling line enable - -- HNP : Horiz. downscaling pix. enable - -- VEN : Enable pixel within displayed window - - IF (i_hnp4='1' AND i_ven6='1') OR i_pushend='1' THEN - i_shift<=shift_ishift(i_shift,i_pix,i_format); - i_dw<=shift_ipack(i_dw,i_acpt,i_shift,i_pix,i_format); - - IF shift_inext(i_acpt,i_format) AND i_vnp='1' THEN - i_push<='1'; - i_pushend<='0'; - END IF; - i_acpt<=(i_acpt+1) MOD 16; - END IF; - - IF i_ven6='1' AND i_ven5='0' AND i_vnp='1' THEN - i_pushend<='1'; - END IF; - i_pushend2<=i_pushend; - - IF i_pushend2='1' AND i_pushend='0' THEN - i_eol<='1'; - END IF; - - IF i_pde='0' AND i_de_pre='1' THEN - i_de_delay<=0; - ELSIF i_de_delay<18 THEN - i_de_delay<=i_de_delay+1; - END IF; - - IF i_de_delay=16 THEN - i_lwad<=0; - i_lrad<=0; - i_vcpt<=i_vcpt+1; - i_hacc<=(i_hsize - i_ohsize + 8192) MOD 8192; - i_hbcpt<=0; - END IF; - IF i_de_delay=17 THEN - i_acpt<=0; - i_wad<=2*BLEN-1; - END IF; - - IF i_pvs='0' AND i_vs_pre='1' THEN - -- Push header - i_pushhead<=to_std_logic(HEADER); - END IF; - - END IF; -- IF i_pce='1' - - ------------------------------------------------------ - -- Push pixels to downscaling line buffer - i_lwr<=i_hnp4 AND i_ven5 AND i_pce; - IF i_lwr='1' THEN - i_lwad<=(i_lwad+1) MOD OHRES; - END IF; - i_ldw<=i_hpix; - - IF i_hnp3='1' AND i_ven4='1' AND i_pce='1' THEN - i_lrad<=(i_lrad+1) MOD OHRES; - END IF; - - ------------------------------------------------------ - -- Write image properties header - i_pushhead2<=i_pushhead; i_pushhead3<=i_pushhead2; - - IF i_pushhead='1' AND i_freeze='0' THEN - i_dw<=i_head(127 DOWNTO 128-N_DW); - i_count<=i_count+1; - i_wr<='1'; - i_wad<=0; - IF N_DW=128 THEN - i_alt<='0'; - i_wreq<=NOT i_freeze; - i_adrs<=(OTHERS =>'0'); - END IF; - END IF; - - IF i_pushhead2='1' AND i_freeze='0' AND N_DW=64 THEN - i_dw<=i_head(N_DW-1 DOWNTO 0); - i_wr<='1'; - i_wad<=1; - i_wreq<=NOT i_freeze; - i_alt<='0'; - i_adrs<=(OTHERS =>'0'); - END IF; - IF i_pushhead3='1' THEN - i_wad<=BLEN-1; - END IF; - - ------------------------------------------------------ - -- Push pixels to DPRAM - IF i_push='1' AND i_freeze='0' THEN - i_wr<='1'; - i_wad<=(i_wad+1) MOD (BLEN*2); - IF (i_wad+1) MOD BLEN=BLEN-1 AND i_hbcpt 12 - IDividers:PROCESS (i_clk,i_reset_na) IS - BEGIN - IF i_reset_na='0' THEN ---pragma synthesis_off - i_v_frac<=x"000"; ---pragma synthesis_on - NULL; - ELSIF rising_edge(i_clk) THEN - i_vdivi<=to_unsigned(2*i_vsize,13); - i_vdivr<=to_unsigned(i_vacc*4096,25); - - ------------------------------------------------------ - IF i_divstart='1' THEN - i_divcpt<=0; - i_divrun<='1'; - - ELSIF i_divrun='1' THEN - ---------------------------------------------------- - IF i_divcpt=6 THEN - i_divrun<='0'; - i_v_frac<=i_vdivr(4 DOWNTO 0) & NOT i_vdivr(24) & "000000"; - ELSE - i_divcpt<=i_divcpt+1; - END IF; - - IF i_vdivr(24)='0' THEN - i_vdivr(24 DOWNTO 12)<=i_vdivr(23 DOWNTO 11) - i_vdivi; - ELSE - i_vdivr(24 DOWNTO 12)<=i_vdivr(23 DOWNTO 11) + i_vdivi; - END IF; - i_vdivr(11 DOWNTO 0)<=i_vdivr(10 DOWNTO 0) & NOT i_vdivr(24); - - ---------------------------------------------------- - END IF; - END IF; - END PROCESS IDividers; - - ----------------------------------------------------------------------------- - -- DPRAM Input. Double buffer for RAM bursts. - PROCESS (i_clk) IS - BEGIN - IF rising_edge(i_clk) THEN - IF i_wr='1' THEN - i_dpram(i_wad)<=i_dw; - END IF; - END IF; - END PROCESS; - - avl_dr<=i_dpram(avl_rad_c) WHEN rising_edge(avl_clk); - - -- Line buffer for downscaling with interpolation - DownLine:IF DOWNSCALE GENERATE - ILBUF:PROCESS(i_clk) IS - BEGIN - IF rising_edge(i_clk) THEN - IF i_lwr='1' THEN - i_mem(i_lwad MOD IHRES)<=i_ldw; - END IF; - IF i_pce='1' THEN - i_ldrm<=i_mem(i_lrad MOD IHRES); - END IF; - END IF; - END PROCESS ILBUF; - END GENERATE DownLine; - - ----------------------------------------------------------------------------- - -- AVALON interface - Avaloir:PROCESS(avl_clk,avl_reset_na) IS - VARIABLE adr_v : unsigned(31 DOWNTO 0); - BEGIN - IF avl_reset_na='0' THEN - avl_state<=sIDLE; - avl_write_sr<='0'; - avl_read_sr<='0'; - avl_readdataack<='0'; - avl_readack<='0'; - - ELSIF rising_edge(avl_clk) THEN - ---------------------------------- - avl_write_sync<=i_write; -- - avl_write_sync2<=avl_write_sync; - avl_write_pulse<=avl_write_sync XOR avl_write_sync2; - IF avl_write_pulse='1' THEN - avl_wadrs <=i_wadrs AND (RAMSIZE - 1); -- - avl_wline <=i_wline; -- - avl_walt <=i_walt; -- - END IF; - - ---------------------------------- - avl_read_sync<=o_read; -- - avl_read_sync2<=avl_read_sync; - avl_read_pulse<=avl_read_sync XOR avl_read_sync2; - avl_radrs <=o_adrs; -- - avl_rline <=o_rline; -- - - -------------------------------------------- - avl_o_vs_sync<=o_vsv(0); -- - avl_o_vs<=avl_o_vs_sync; - - avl_fb_ena<=o_fb_ena; -- - IF avl_fb_ena='0' THEN - IF HEADER THEN - avl_o_offset0<=buf_offset(o_obuf0,RAMBASE,RAMSIZE) + N_BURST; -- - avl_o_offset1<=buf_offset(o_obuf1,RAMBASE,RAMSIZE) + N_BURST; -- - ELSE - avl_o_offset0<=buf_offset(o_obuf0,RAMBASE,RAMSIZE); -- - avl_o_offset1<=buf_offset(o_obuf1,RAMBASE,RAMSIZE); -- - END IF; - ELSIF avl_o_vs_sync='0' AND avl_o_vs='1' THEN - -- Copy framebuffer base address at VS falling edge - avl_o_offset0<=o_fb_base; -- - avl_o_offset1<=o_fb_base; -- - END IF; - - avl_i_offset0<=buf_offset(o_ibuf0,RAMBASE,RAMSIZE); -- - avl_i_offset1<=buf_offset(o_ibuf1,RAMBASE,RAMSIZE); -- - - -------------------------------------------- - avl_dw<=swap(unsigned(avl_readdata)); - avl_read_i<='0'; - avl_write_i<='0'; - - avl_write_sr<=(avl_write_sr OR avl_write_pulse) AND NOT avl_write_clr; - avl_read_sr <=(avl_read_sr OR avl_read_pulse) AND NOT avl_read_clr; - avl_write_clr<='0'; - avl_read_clr <='0'; - - avl_rad<=avl_rad_c; - - -------------------------------------------- - CASE avl_state IS - WHEN sIDLE => - IF avl_write_sr='1' THEN - avl_state<=sWRITE; - avl_write_clr<='1'; - IF avl_walt='0' THEN - avl_rad<=0; - ELSE - avl_rad<=BLEN; - END IF; - IF avl_wline='0' THEN - avl_address<=std_logic_vector( - avl_wadrs(N_AW+NB_LA-1 DOWNTO NB_LA) + - avl_i_offset0(N_AW+NB_LA-1 DOWNTO NB_LA)); - ELSE - avl_address<=std_logic_vector( - avl_wadrs(N_AW+NB_LA-1 DOWNTO NB_LA) + - avl_i_offset1(N_AW+NB_LA-1 DOWNTO NB_LA)); - END IF; - ELSIF avl_read_sr='1' THEN - avl_state<=sREAD; - avl_read_clr<='1'; - END IF; - - WHEN sWRITE => - avl_write_i<='1'; - IF avl_write_i='1' AND avl_waitrequest='0' THEN - IF (avl_rad MOD BLEN)=BLEN-1 THEN - avl_write_i<='0'; - avl_state<=sIDLE; - END IF; - END IF; - - WHEN sREAD => - IF avl_rline='0' THEN - adr_v:=avl_radrs + avl_o_offset0; - ELSE - adr_v:=avl_radrs + avl_o_offset1; - END IF; - avl_address<=std_logic_vector(adr_v(N_AW+NB_LA-1 DOWNTO NB_LA)); - - avl_read_i<='1'; - IF avl_read_i='1' AND avl_waitrequest='0' THEN - avl_state<=sIDLE; - avl_read_i<='0'; - avl_readack<=NOT avl_readack; - END IF; - END CASE; - - -------------------------------------------- - -- Pipelined data read - avl_wr<='0'; - IF avl_readdatavalid='1' THEN - avl_wr<='1'; - avl_wad<=(avl_wad+1) MOD (2*BLEN); - IF (avl_wad MOD BLEN)=BLEN-2 THEN - avl_readdataack<=NOT avl_readdataack; - END IF; - END IF; - - IF avl_o_vs_sync='0' AND avl_o_vs='1' THEN - avl_wad<=2*BLEN-1; - END IF; - - -------------------------------------------- - END IF; - END PROCESS Avaloir; - - avl_read<=avl_read_i; - avl_write<=avl_write_i; - avl_writedata<=std_logic_vector(swap(avl_dr)); - avl_burstcount<=std_logic_vector(to_unsigned(BLEN,8)); - avl_byteenable<=(OTHERS =>'1'); - - avl_rad_c<=(avl_rad+1) MOD (2*BLEN) - WHEN avl_write_i='1' AND avl_waitrequest='0' ELSE avl_rad; - - ----------------------------------------------------------------------------- - -- DPRAM Output. Double buffer for RAM bursts. - PROCESS (avl_clk) IS - BEGIN - IF rising_edge(avl_clk) THEN - IF avl_wr='1' THEN - o_dpram(avl_wad)<=avl_dw; - END IF; - END IF; - END PROCESS; - - o_dr<=o_dpram(o_ad3) WHEN rising_edge(o_clk); - - ----------------------------------------------------------------------------- - -- Output Vertical Divider - -- Vfrac = Vacc / Vsize - ODivider:PROCESS (o_clk,o_reset_na) IS - BEGIN - IF o_reset_na='0' THEN ---pragma synthesis_off - o_vfrac<=x"000"; ---pragma synthesis_on - ELSIF rising_edge(o_clk) THEN - o_vdivi<=to_unsigned(2*o_vsize,13); - o_vdivr<=to_unsigned(o_vacc*4096,25); - ------------------------------------------------------ - IF o_divstart='1' THEN - o_divcpt<=0; - o_divrun<='1'; - - ELSIF o_divrun='1' THEN - ---------------------------------------------------- - IF o_divcpt=12 THEN - o_divrun<='0'; - o_vfrac<=o_vdivr(10 DOWNTO 0) & NOT o_vdivr(24); - ELSE - o_divcpt<=o_divcpt+1; - END IF; - - IF o_vdivr(24)='0' THEN - o_vdivr(24 DOWNTO 12)<=o_vdivr(23 DOWNTO 11) - o_vdivi; - ELSE - o_vdivr(24 DOWNTO 12)<=o_vdivr(23 DOWNTO 11) + o_vdivi; - END IF; - o_vdivr(11 DOWNTO 0)<=o_vdivr(10 DOWNTO 0) & NOT o_vdivr(24); - ---------------------------------------------------- - END IF; - END IF; - END PROCESS ODivider; - - ----------------------------------------------------------------------------- - Scalaire:PROCESS (o_clk,o_reset_na) IS - VARIABLE lev_inc_v,lev_dec_v : std_logic; - VARIABLE prim_v,last_v,bib_v : std_logic; - VARIABLE shift_v : unsigned(0 TO N_DW+15); - VARIABLE hpix_v : type_pix; - VARIABLE hcarry_v,vcarry_v : boolean; - VARIABLE dif_v : natural RANGE 0 TO 8*OHRES-1; - VARIABLE off_v : natural RANGE 0 TO 15; - BEGIN - IF o_reset_na='0' THEN - o_copy<=sWAIT; - o_state<=sDISP; - o_read_pre<='0'; - o_readlev<=0; - o_copylev<=0; - o_hsp<='0'; - - ELSIF rising_edge(o_clk) THEN - ------------------------------------------------------ - o_mode <=mode; -- ? - o_format <="0001" & format; -- ? - - o_run <=run; -- ? - - o_htotal <=htotal; -- ? - o_hsstart<=hsstart; -- ? - o_hsend <=hsend; -- ? - o_hdisp <=hdisp; -- ? - o_hmin <=hmin; -- ? - o_hmax <=hmax; -- ? - - o_vtotal <=vtotal; -- ? - o_vsstart<=vsstart; -- ? - o_vsend <=vsend; -- ? - o_vdisp <=vdisp; -- ? - o_vmin <=vmin; -- ? - o_vmax <=vmax; -- ? - - o_hsize <=o_hmax - o_hmin + 1; - o_vsize <=o_vmax - o_vmin + 1; - - o_vrr <=vrr; - o_vrrmax <= vrrmax; - - -------------------------------------------- - -- Triple buffering. - -- For intelaced video, half frames are updated independently - -- Input : Toggle buffer at end of input frame - o_isync <= '0'; - o_isync2 <= o_isync; - o_freeze <= freeze; - o_inter <=i_inter; -- - o_iendframe0<=i_endframe0; -- - o_iendframe02<=o_iendframe0; - IF o_iendframe0='1' AND o_iendframe02='0' THEN - o_ibuf0<=buf_next(o_ibuf0,o_obuf0,o_freeze); - o_bufup0<='1'; - o_isync <= '1'; - END IF; - o_iendframe1<=i_endframe1; -- - o_iendframe12<=o_iendframe1; - IF o_iendframe1='1' AND o_iendframe12='0' THEN - o_ibuf1<=buf_next(o_ibuf1,o_obuf1,o_freeze); - o_bufup1<='1'; - o_isync <= '1'; - END IF; - - -- Output : Change framebuffer, and image properties, at VS falling edge - IF o_vsv(1)='1' AND o_vsv(0)='0' AND o_bufup0='1' THEN - o_obuf0<=buf_next(o_obuf0,o_ibuf0,o_freeze); - o_bufup0<='0'; - END IF; - IF o_vsv(1)='1' AND o_vsv(0)='0' AND o_bufup1='1' THEN - o_obuf1<=buf_next(o_obuf1,o_ibuf1,o_freeze); - o_bufup1<='0'; - o_ihsize<=i_hrsize; -- - o_ivsize<=i_vrsize; -- - o_hdown<=i_hdown; -- - o_vdown<=i_vdown; -- - END IF; - - -- Simultaneous change of input and output framebuffers - IF o_vsv(1)='1' AND o_vsv(0)='0' AND - o_iendframe0='1' AND o_iendframe02='0' THEN - o_bufup0<='0'; - o_obuf0<=o_ibuf0; - END IF; - IF o_vsv(1)='1' AND o_vsv(0)='0' AND - o_iendframe1='1' AND o_iendframe12='0' THEN - o_bufup1<='0'; - o_obuf1<=o_ibuf1; - END IF; - - -- Non-interlaced, use same buffer for even and odd lines - IF o_inter='0' THEN - o_ibuf1<=o_ibuf0; - o_obuf1<=o_obuf0; - END IF; - - -- Triple buffer disabled - IF o_mode(3)='0' THEN - o_obuf0<=0; - o_obuf1<=0; - o_ibuf0<=0; - o_ibuf1<=0; - END IF; - - -- Framebuffer mode. - IF o_fb_ena='1' THEN - o_ihsize<=o_fb_hsize; - o_ivsize<=o_fb_vsize; - o_format<=o_fb_format; - o_hdown<='0'; - o_vdown<='0'; - END IF; - - -- 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp - CASE o_format(2 DOWNTO 0) IS - WHEN "011" => o_ihsize_temp <= o_ihsize; - WHEN "100" => o_ihsize_temp <= o_ihsize * 2; - WHEN "110" => o_ihsize_temp <= o_ihsize * 4; - WHEN OTHERS => o_ihsize_temp <= o_ihsize * 3; - END CASE; - - o_ihsize_temp2 <= (o_ihsize_temp + N_BURST - 1); - o_hburst <= o_ihsize_temp2 / N_BURST; - - IF o_fb_ena='1' AND o_fb_stride /= 0 THEN - o_stride<=o_fb_stride; - ELSE - o_stride<=to_unsigned(o_ihsize_temp2,14); - o_stride(NB_BURST-1 DOWNTO 0)<=(OTHERS =>'0'); - END IF; - ------------------------------------------------------ - o_hmode<=o_mode; - IF o_hdown='1' AND DOWNSCALE THEN - -- Force nearest if downscaling : Downscaled framebuffer - o_hmode(2 DOWNTO 0)<="000"; - END IF; - - o_vmode<=o_mode; - IF o_vdown='1' AND DOWNSCALE THEN - -- Force nearest if downscaling : Downscaled framebuffer - o_vmode(2 DOWNTO 0)<="000"; - END IF; - - ------------------------------------------------------ - -- End DRAM READ - o_readack_sync<=avl_readack; -- - o_readack_sync2<=o_readack_sync; - o_readack<=o_readack_sync XOR o_readack_sync2; - - o_readdataack_sync<=avl_readdataack; -- - o_readdataack_sync2<=o_readdataack_sync; - o_readdataack<=o_readdataack_sync XOR o_readdataack_sync2; - - ------------------------------------------------------ - lev_inc_v:='0'; - lev_dec_v:='0'; - - -- acpt : Pixel position within current data word - -- dcpt : Destination image position - - -- Force preload 2 lines at top of screen - IF o_hsv(0)='1' AND o_hsv(1)='0' THEN - IF o_vcpt_pre3=o_vmin THEN - o_fload<=2; - o_bibu<='0'; - END IF; - o_hsp<='1'; - END IF; - - o_vpe<=to_std_logic(o_vcpt_pre=o_vmin); - o_divstart<='0'; - o_adrsa<='0'; - o_adrsb<=o_adrsa; - - o_vacc_ini<=(o_vsize - o_ivsize + 8192) MOD 8192; - o_hacc_ini<=(o_hsize + o_ihsize + 8192) MOD 8192; - - --Alternate phase - --o_vacc_ini<=o_ivsize; - --o_hacc_ini<=(2*o_hsize - o_ihsize + 8192) MOD 8192; - - CASE o_state IS - -------------------------------------------------- - WHEN sDISP => - IF o_hsp='1' THEN - o_state<=sHSYNC; - o_hsp<='0'; - END IF; - o_prim<=true; - o_vcarrym<=false; - - -------------------------------------------------- - WHEN sHSYNC => - dif_v :=(o_vacc_next - 2*o_vsize + 16384) MOD 16384; - IF o_prim THEN - IF dif_v>=8192 THEN - o_vacc <=o_vacc_next; - ELSE - o_vacc <=dif_v; - END IF; - END IF; - IF dif_v>=8192 THEN - o_vacc_next<=(o_vacc_next + 2*o_ivsize) MOD 8192; - vcarry_v:=false; - ELSE - o_vacc_next<=dif_v; - vcarry_v:=true; - END IF; - - IF o_vcpt_pre2=o_vmin THEN - o_vacc <=o_vacc_ini; - o_vacc_next<=o_vacc_ini + 2*o_ivsize; - o_vacpt <=x"001"; - o_vacptl<="01"; - vcarry_v:=false; - END IF; - - IF vcarry_v THEN - o_vacpt<=o_vacpt+1; - END IF; - IF vcarry_v AND o_prim THEN - o_vacptl<=o_vacptl+1; - END IF; - o_vcarrym <= o_vcarrym OR vcarry_v; - o_prim <= false; - o_hbcpt<=0; -- Clear burst counter on line - o_divstart<=to_std_logic(NOT vcarry_v); - IF NOT vcarry_v OR o_fload>0 THEN - IF (o_vpe='1' AND o_vcarrym) OR o_fload>0 THEN - o_state<=sREAD; - ELSE - o_state<=sDISP; - END IF; - END IF; - - WHEN sREAD => - -- Read a block - IF o_readlev<2 AND o_adrsb='1' THEN - lev_inc_v:='1'; - o_read_pre<=NOT o_read_pre; - o_state <=sWAITREAD; - o_bibu<=NOT o_bibu; - END IF; - prim_v:=to_std_logic(o_hbcpt=0); - last_v:=to_std_logic(o_hbcpt=o_hburst-1); - bib_v :=o_bibu; - off_v :=pixoffset(o_adrs + o_fb_base(NB_LA-1 DOWNTO 0),o_fb_format); - IF o_fb_ena='0' THEN - off_v:=0; - END IF; - o_adrsa<='1'; - - WHEN sWAITREAD => - IF o_readack='1' THEN - o_hbcpt<=o_hbcpt+1; - IF o_hbcpt=1 THEN - o_fload<=o_fload-1; - END IF; - END IF; - END IF; - - -------------------------------------------------- - END CASE; - - o_read<=o_read_pre AND o_run; - o_rline<=o_vacpt(0); -- Even/Odd line for interlaced video - - o_adrs_pre<=to_integer(o_vacpt) * to_integer(o_stride); - IF o_adrsa='1' THEN - IF o_fload=2 THEN - o_adrs<=to_unsigned(o_hbcpt * N_BURST,32); - o_alt<="1111"; - ELSIF o_fload=1 THEN - o_adrs<=to_unsigned(o_hbcpt * N_BURST,32) + o_stride; - o_alt<="0100"; - ELSE - o_adrs<=to_unsigned(o_adrs_pre + (o_hbcpt * N_BURST),32); - o_alt<=altx(o_vacptl + 1); - END IF; - END IF; - - ------------------------------------------------------ - -- Copy from buffered memory to pixel lines - o_sh<='0'; - CASE o_copy IS - WHEN sWAIT => - o_copyv(0)<='0'; - IF o_copylev>0 AND o_copyv(0)='0' THEN - o_copy<=sCOPY; - IF o_off(0)>0 AND o_primv(0)='1' THEN - o_copy<=sSHIFT; - END IF; - o_altx<=o_alt; - END IF; - o_adturn<='0'; - o_pshift<=o_off(0) -1; - IF o_primv(0)='1' THEN - -- First memcopy of a horizontal line, carriage return ! - o_ihsizem<=o_ihsize + o_off(0) - 2; - o_hacc <=o_hacc_ini; - o_hacc_next<=o_hacc_ini + 2*o_ihsize; - o_hacpt <=x"000"; - o_dcpt<=0; - o_dshi<=2; - o_acpt<=0; - o_first<='1'; - o_last<='0'; - END IF; - - IF o_bibv(0)='0' THEN - o_ad<=0; - ELSE - o_ad<=BLEN; - END IF; - - WHEN sSHIFT => - o_hacpt<=o_hacpt+1; - o_sh<='1'; - o_acpt<=(o_acpt+1) MOD 16; - IF shift_onext(o_acpt,o_format) THEN - o_ad<=(o_ad+1) MOD (2*BLEN); - END IF; - o_pshift<=o_pshift-1; - IF o_pshift=0 THEN - o_copy<=sCOPY; - END IF; - - WHEN sCOPY => - -- dshi : Force shift first two or three pixels of each line - IF o_dshi=0 THEN - dif_v:=(o_hacc_next - 2*o_hsize + (8*OHRES)) MOD (8*OHRES); - IF dif_v>=4*OHRES THEN - o_hacc<=o_hacc_next; - o_hacc_next<=o_hacc_next + 2*o_ihsize; - hcarry_v:=false; - ELSE - o_hacc<=dif_v; - o_hacc_next<=(dif_v + 2*o_ihsize + (4*OHRES)) MOD (4*OHRES); - hcarry_v:=true; - END IF; - o_dcpt<=(o_dcpt+1) MOD 4096; - ELSE - o_dshi<=o_dshi-1; - hcarry_v:=false; - END IF; - IF o_dshi<=1 THEN - o_copyv(0)<='1'; - END IF; - IF hcarry_v THEN - o_hacpt<=o_hacpt+1; - o_last <=to_std_logic(o_hacpt>=o_ihsizem); - END IF; - - IF hcarry_v OR o_dshi>0 THEN - o_sh<='1'; - o_acpt<=(o_acpt+1) MOD 16; - - -- Shift two more pixels to the right before ending line. - o_last1<=o_last; - o_last2<=o_last1; - - IF shift_onext(o_acpt,o_format) THEN - o_ad<=(o_ad+1) MOD (2*BLEN); - END IF; - - IF o_adturn='1' AND (shift_onext((o_acpt+1) MOD 16,o_format)) AND - (((o_ad MOD BLEN=0) AND o_lastv(0)='0') OR o_last2='1') THEN - o_copy<=sWAIT; - lev_dec_v:='1'; - END IF; - - IF o_ad MOD BLEN=4 THEN - o_adturn<='1'; - END IF; - END IF; - END CASE; - - o_acpt1<=o_acpt; o_acpt2<=o_acpt1; o_acpt3<=o_acpt2; o_acpt4<=o_acpt3; - o_ad1<=o_ad; o_ad2<=o_ad1; o_ad3<=o_ad2; - o_sh1<=o_sh; o_sh2<=o_sh1; o_sh3<=o_sh2; o_sh4<=o_sh3; - o_lastt1<=o_last; o_lastt2<=o_lastt1; - o_lastt3<=o_lastt2; o_lastt4<=o_lastt3; - - ------------------------------------------------------ - IF o_sh3='1' THEN - shift_v:=shift_opack(o_acpt4,o_shift,o_dr,o_format); - o_shift<=shift_v; - o_hpixs<=shift_opix(shift_v,o_format); - END IF; - - IF o_sh4='1' THEN - hpix_v:=o_hpixs; - IF o_format(4)='1' THEN -- Swap B <-> R - hpix_v:=(r=>o_hpixs.b,g=>o_hpixs.g,b=>o_hpixs.r); - END IF; - IF o_format(2 DOWNTO 0)="011" THEN - -- 8bpp indexed colour mode - hpix_v:=(r=>o_fb_pal_dr(23 DOWNTO 16),g=>o_fb_pal_dr(15 DOWNTO 8), - b=>o_fb_pal_dr(7 DOWNTO 0)); - END IF; - o_hpix0<=hpix_v; - o_hpix1<=o_hpix0; - o_hpix2<=o_hpix1; - o_hpix3<=o_hpix2; - - IF o_first='1' THEN - -- Left edge. Duplicate first pixel - o_hpix1<=hpix_v; - o_hpix2<=hpix_v; - o_first<='0'; - END IF; - IF o_lastt4='1' THEN - -- Right edge. Keep last pixel. - o_hpix0<=o_hpix0; - END IF; - END IF; - - ------------------------------------------------------ - -- lev_inc : read start - -- lev_dec : end of copy - -- READLEV : Number of ongoing Avalon Reads - IF lev_dec_v='0' AND lev_inc_v='1' THEN - o_readlev<=o_readlev+1; - ELSIF lev_dec_v='1' AND lev_inc_v='0' THEN - o_readlev<=o_readlev-1; - END IF; - - -- COPYLEV : Number of ongoing copies to line buffers - IF lev_dec_v='1' AND o_readdataack='0' THEN - o_copylev<=o_copylev-1; - ELSIF lev_dec_v='0' AND o_readdataack='1' THEN - o_copylev<=o_copylev+1; - END IF; - - -- FIFOs - IF lev_dec_v='1' THEN - o_primv(0 TO 1)<=o_primv(1 TO 2); -- First buffer of line - o_lastv(0 TO 1)<=o_lastv(1 TO 2); -- Last buffer of line - o_bibv (0 TO 1)<=o_bibv (1 TO 2); -- Double buffer select - o_off (0 TO 1)<=o_off (1 TO 2); -- Start offset - END IF; - - IF lev_inc_v='1' THEN - IF o_readlev=0 OR (o_readlev=1 AND lev_dec_v='1') THEN - o_primv(0)<=prim_v; - o_lastv(0)<=last_v; - o_bibv (0)<=bib_v; - o_off (0)<=off_v; - ELSIF (o_readlev=1 AND lev_dec_v='0') OR - (o_readlev=2 AND lev_dec_v='1') THEN - o_primv(1)<=prim_v; - o_lastv(1)<=last_v; - o_bibv (1)<=bib_v; - o_off (1)<=off_v; - END IF; - o_primv(2)<=prim_v; - o_lastv(2)<=last_v; - o_bibv (2)<=bib_v; - o_off (2)<=off_v; - END IF; - - ------------------------------------------------------ - END IF; - END PROCESS Scalaire; - - -- Fetch polyphase coefficients - PolyFetch:PROCESS (o_clk) IS - VARIABLE hfrac3_v, vfrac_v : unsigned(FRAC-1 DOWNTO 0); - BEGIN - IF rising_edge(o_clk) THEN - hfrac3_v:=o_hfrac(3)(11 DOWNTO 12-FRAC); - vfrac_v:=o_vfrac(11 DOWNTO 12-FRAC); - - o_v_poly_use_adaptive <= to_std_logic((o_vmode(2 DOWNTO 0)/="000") AND (o_v_poly_adaptive = '1')); - o_h_poly_use_adaptive <= to_std_logic((o_hmode(2 DOWNTO 0)/="000") AND (o_h_poly_adaptive = '1')); - o_v_poly_addr<=to_integer(o_vfrac(11 DOWNTO 12-FRAC)); - - -- C3 / HC3 / VC4 - IF o_vmode(2 DOWNTO 0)/="000" THEN - o_v_poly_phase_a<=poly_unpack(o_v_poly_mem(o_v_poly_addr)); - ELSE - o_v_poly_phase_a<=poly_nn(vfrac_v); - END IF; - - IF o_hmode(2 DOWNTO 0)/="000" THEN - o_h_poly_phase_a<=poly_unpack(o_h_poly_mem(to_integer(hfrac3_v))); - ELSE - o_h_poly_phase_a<=poly_nn(hfrac3_v); - END IF; - - IF o_v_poly_use_adaptive='1' THEN - o_poly_lum<=poly_lum(o_v_lum_pix); - o_a_poly_addr<=o_v_poly_addr; - ELSIF o_h_poly_use_adaptive='1' THEN - o_poly_lum<=poly_lum(o_h_lum_pix); - o_a_poly_addr<=to_integer(hfrac3_v); - END IF; - - -- C4 / HC4 / VC5 - o_poly_phase_b<=poly_unpack(o_a_poly_mem(o_a_poly_addr)); - - IF o_v_poly_use_adaptive='1' THEN - o_poly_phase_a<=o_v_poly_phase_a; - ELSIF o_h_poly_use_adaptive = '1' THEN - o_poly_phase_a<=o_h_poly_phase_a; - END IF; - - o_h_poly_phase_a2<=o_h_poly_phase_a; - o_v_poly_phase_a2<=o_v_poly_phase_a; - o_poly_lum1<=o_poly_lum; - - -- C5 / HC5 / VC6 - o_poly_lerp_ta<=signed(to_unsigned(256,10) - resize(o_poly_lum1,10)); - o_poly_lerp_tb<=signed(resize(o_poly_lum1,10)); - - o_poly_phase_b2<=o_poly_phase_b; - o_poly_phase_a2<=o_poly_phase_a; - - o_h_poly_phase_a3<=o_h_poly_phase_a2; - o_v_poly_phase_a3<=o_v_poly_phase_a2; - - -- C6 / HC6 / VC7 - o_poly_phase<=poly_lerp(o_poly_phase_a2, o_poly_phase_b2, o_poly_lerp_ta, o_poly_lerp_tb); - o_h_poly_phase_a4<=o_h_poly_phase_a3; - o_v_poly_phase_a4<=o_v_poly_phase_a3; - - -- C7 / HC7 / VC8 - o_h_poly_phase_a5<=o_h_poly_phase_a4; - o_v_poly_phase_a5<=o_v_poly_phase_a4; - o_poly_phase1<=o_poly_phase; - - -- C8 / HC8 / VC9 - o_v_poly_phase<=poly_cvt(o_v_poly_phase_a5); - o_h_poly_phase<=poly_cvt(o_h_poly_phase_a5); - - IF o_v_poly_use_adaptive = '1' THEN - o_v_poly_phase<=o_poly_phase1; - ELSIF o_h_poly_use_adaptive = '1' THEN - o_h_poly_phase<=o_poly_phase1; - END IF; - - END IF; - END PROCESS PolyFetch; - - - -- Framebuffer palette - GenPal1:IF PALETTE GENERATE - Tempera1:PROCESS(pal1_clk) IS - BEGIN - IF rising_edge(pal1_clk) THEN - IF pal1_wr='1' THEN - pal1_mem(to_integer(pal1_a))<=pal1_dw; - END IF; - pal1_dr<=pal1_mem(to_integer(pal1_a)); - END IF; - END PROCESS; - - pal_idx <= shift_opack(o_acpt4,o_shift,o_dr,o_format)(0 TO 7); - pal_idx_lsb <= pal_idx(0) WHEN rising_edge(o_clk); - o_fb_pal_dr_x2 <= pal1_mem(to_integer(pal_idx(7 DOWNTO 1))) WHEN rising_edge(o_clk); - END GENERATE GenPal1; - - GenPal2:IF PALETTE and PALETTE2 GENERATE - Tempera2:PROCESS(pal2_clk) IS - BEGIN - IF rising_edge(pal2_clk) THEN - IF pal2_wr='1' THEN - pal2_mem(to_integer(pal2_a))<=pal2_dw; - END IF; - pal2_dr<=pal2_mem(to_integer(pal2_a)); - END IF; - END PROCESS; - - o_fb_pal_dr2 <= pal2_mem(to_integer(pal_idx(7 DOWNTO 0))) WHEN rising_edge(o_clk); - o_fb_pal_dr <= o_fb_pal_dr2 when pal_n = '1' else o_fb_pal_dr_x2(47 DOWNTO 24) WHEN pal_idx_lsb = '1' ELSE o_fb_pal_dr_x2(23 DOWNTO 0); - END GENERATE GenPal2; - - GenPal1not2:IF PALETTE and not PALETTE2 GENERATE - o_fb_pal_dr <= o_fb_pal_dr_x2(47 DOWNTO 24) WHEN pal_idx_lsb = '1' ELSE o_fb_pal_dr_x2(23 DOWNTO 0); - END GENERATE GenPal1not2; - - GenNoPal:IF NOT PALETTE GENERATE - o_fb_pal_dr<=x"000000"; - END GENERATE GenNoPal; - - ----------------------------------------------------------------------------- - -- Polyphase ROMs - Polikarpov:PROCESS(poly_clk) IS - BEGIN - IF rising_edge(poly_clk) THEN - IF poly_wr='1' THEN - poly_tdw(9+10*(3-to_integer(poly_a(1 DOWNTO 0))) DOWNTO - 10*(3-to_integer(poly_a(1 DOWNTO 0))))<=poly_dw; - END IF; - - poly_wr_mode(0)<=poly_wr AND NOT poly_a(FRAC+2); - poly_wr_mode(1)<=poly_wr AND poly_a(FRAC+2); - poly_wr_mode(2)<=poly_wr AND poly_a(FRAC+3) AND to_std_logic(ADAPTIVE); - poly_a2<=poly_a(FRAC+1 DOWNTO 2); - - CASE poly_wr_mode IS - WHEN "001" => -- horiz - o_h_poly_mem(to_integer(poly_a2))<=poly_tdw; - o_h_poly_adaptive<='0'; - WHEN "010" => -- vert - o_v_poly_mem(to_integer(poly_a2))<=poly_tdw; - o_v_poly_adaptive<='0'; - WHEN "101" => -- horiz adaptive - o_a_poly_mem(to_integer(poly_a2))<=poly_tdw; - o_h_poly_adaptive<='1'; - WHEN "110" => -- vert adaptive - o_a_poly_mem(to_integer(poly_a2))<=poly_tdw; - o_v_poly_adaptive<='1'; - WHEN OTHERS => NULL; - END CASE; - END IF; - END PROCESS Polikarpov; - - ----------------------------------------------------------------------------- - -- Horizontal Scaler - HSCAL:PROCESS(o_clk) IS - VARIABLE div_v : unsigned(20 DOWNTO 0); - VARIABLE dir_v : unsigned(11 DOWNTO 0); - BEGIN - IF rising_edge(o_clk) THEN - -- Pipeline signals - ----------------------------------- - -- Pipelined 8 bits non-restoring divider. Cycle 1 - dir_v:=x"000"; - div_v:=to_unsigned(o_hacc * 256,21); - - div_v:=div_v-to_unsigned(o_hsize*256,21); - dir_v(11):=NOT div_v(20); - IF div_v(20)='0' THEN - div_v:=div_v-to_unsigned(o_hsize*128,21); - ELSE - div_v:=div_v+to_unsigned(o_hsize*128,21); - END IF; - dir_v(10):=NOT div_v(20); - - o_div(0)<=div_v; - o_dir(0)<=dir_v; - - -- Cycle 2 - div_v:=o_div(0); - dir_v:=o_dir(0); - IF div_v(20)='0' THEN - div_v:=div_v-to_unsigned(o_hsize*64,21); - ELSE - div_v:=div_v+to_unsigned(o_hsize*64,21); - END IF; - dir_v( 9):=NOT div_v(20); - - IF div_v(20)='0' THEN - div_v:=div_v-to_unsigned(o_hsize*32,21); - ELSE - div_v:=div_v+to_unsigned(o_hsize*32,21); - END IF; - dir_v( 8):=NOT div_v(20); - - o_div(1)<=div_v; - o_dir(1)<=dir_v; - - -- Cycle 3 - div_v:=o_div(1); - dir_v:=o_dir(1); - IF FRAC>4 THEN - IF div_v(20)='0' THEN - div_v:=div_v-to_unsigned(o_hsize*16,21); - ELSE - div_v:=div_v+to_unsigned(o_hsize*16,21); - END IF; - dir_v(7):=NOT div_v(20); - - IF div_v(20)='0' THEN - div_v:=div_v-to_unsigned(o_hsize*8,21); - ELSE - div_v:=div_v+to_unsigned(o_hsize*8,21); - END IF; - dir_v(6):=NOT div_v(20); - END IF; - o_div(2)<=div_v; - o_dir(2)<=dir_v; - - div_v:=o_div(2); - dir_v:=o_dir(2); - IF FRAC>6 THEN - IF div_v(20)='0' THEN - div_v:=div_v-to_unsigned(o_hsize*4,21); - ELSE - div_v:=div_v+to_unsigned(o_hsize*4,21); - END IF; - dir_v(5):=NOT div_v(20); - - IF div_v(20)='0' THEN - div_v:=div_v-to_unsigned(o_hsize*2,21); - ELSE - div_v:=div_v+to_unsigned(o_hsize*2,21); - END IF; - dir_v(4):=NOT div_v(20); - END IF; - - ----------------------------------- - o_hfrac(1)<=dir_v; - o_hfrac(2 TO 9) <= o_hfrac(1 TO 8); - - o_copyv(1 TO 14)<=o_copyv(0 TO 13); - - o_dcptv(1)<=o_dcpt; - IF o_dcptv(1)>=o_hsize THEN - o_copyv(2)<='0'; - END IF; - o_dcptv(2)<=o_dcptv(1) MOD OHRES; - o_dcptv(3 TO 14)<=o_dcptv(2 TO 13); - - -- C2 - o_hpixq(2)<=(o_hpix3,o_hpix2,o_hpix1,o_hpix0); - o_hpixq(3 TO 8)<=o_hpixq(2 TO 7); - - -- BILINEAR / SHARP BILINEAR --------------- - -- C7 : Pre-calc Sharp Bilinear - o_h_sbil_t<=sbil_frac1(o_hfrac(6)); - - -- C8 : Select - o_h_bil_frac<=(OTHERS =>'0'); - IF o_hmode(0)='1' THEN -- Bilinear - IF MASK(MASK_BILINEAR)='1' THEN - o_h_bil_frac<=bil_frac(o_hfrac(7)); - END IF; - ELSE -- Sharp Bilinear - IF MASK(MASK_SHARP_BILINEAR)='1' THEN - o_h_bil_frac<=sbil_frac2(o_hfrac(7),o_h_sbil_t); - END IF; - END IF; - - -- C9 : Opposite frac - o_h_bil_t<=bil_calc(o_h_bil_frac,o_hpixq(8)); - - -- C10 : Bilinear / Sharp Bilinear - o_h_bil_pix.r<=bound(o_h_bil_t.r,8+FRAC); - o_h_bil_pix.g<=bound(o_h_bil_t.g,8+FRAC); - o_h_bil_pix.b<=bound(o_h_bil_t.b,8+FRAC); - - -- BICUBIC ------------------------------------------- - -- C8 : Bicubic coefficients A,B,C,D - -- C8 : Bicubic calc T1 = X.D + C - o_h_bic_abcd1<=bic_calc0(o_hfrac(7),o_hpixq(6)); - o_h_bic_tt1<=bic_calc1(o_hfrac(7), - bic_calc0(o_hfrac(7),o_hpixq(6))); - - -- C9 : Bicubic calc T2 = X.T1 + B - o_h_bic_abcd2<=o_h_bic_abcd1; - o_h_bic_tt2<=bic_calc2(o_hfrac(8),o_h_bic_tt1,o_h_bic_abcd1); - - -- C10 : Bicubic final Y = X.T2 + A - o_h_bic_pix<=bic_calc3(o_hfrac(9),o_h_bic_tt2,o_h_bic_abcd2); - - -- POLYPHASE ----------------------------------------- - -- C2 - IF o_hfrac(2)(o_hfrac(2)'left)='0' THEN - o_h_lum_pix<=o_hpix2; - ELSE - o_h_lum_pix<=o_hpix1; - END IF; - - -- C3-C8 in PolyFetch - - -- C9 : Apply Polyphase - o_h_poly_t<=poly_calc(o_h_poly_phase,o_hpixq(8)); - - -- C10 : Sum and bound - o_h_poly_pix<=poly_final(o_h_poly_t); - - -- C11 : Select interpoler ---------------------------- - o_wadl<=o_dcptv(14); - o_wr<=o_altx AND (o_copyv(14) & o_copyv(14) & o_copyv(14) & o_copyv(14)); - o_ldw<=(x"00",x"00",x"00"); - - CASE o_hmode(2 DOWNTO 0) IS - WHEN "000" => -- Nearest - IF MASK(MASK_NEAREST)='1' THEN - o_ldw<=o_h_poly_pix; - END IF; - WHEN "001" | "010" => -- Bilinear | Sharp Bilinear - IF MASK(MASK_BILINEAR)='1' OR - MASK(MASK_SHARP_BILINEAR)='1' THEN - o_ldw<=o_h_bil_pix; - END IF; - WHEN "011" => -- BiCubic - IF MASK(MASK_BICUBIC)='1' THEN - o_ldw<=o_h_bic_pix; - END IF; - WHEN OTHERS => -- PolyPhase - IF MASK(MASK_POLY)='1' THEN - o_ldw<=o_h_poly_pix; - END IF; - END CASE; - ------------------------------------------------------ - END IF; - END PROCESS HSCAL; - - ----------------------------------------------------------------------------- - -- Line buffers 4 x OHRES x (R+G+B) - OLBUF:PROCESS(o_clk) IS - BEGIN - IF rising_edge(o_clk) THEN - -- WRITES - IF o_wr(0)='1' THEN o_line0(o_wadl)<=o_ldw; END IF; - IF o_wr(1)='1' THEN o_line1(o_wadl)<=o_ldw; END IF; - IF o_wr(2)='1' THEN o_line2(o_wadl)<=o_ldw; END IF; - IF o_wr(3)='1' THEN o_line3(o_wadl)<=o_ldw; END IF; - - -- READS - o_ldr0<=o_line0(o_radl0); - o_ldr1<=o_line1(o_radl1); - o_ldr2<=o_line2(o_radl2); - o_ldr3<=o_line3(o_radl3); - END IF; - END PROCESS OLBUF; - - ----------------------------------------------------------------------------- - -- Output video sweep - OSWEEP:PROCESS(o_clk) IS - BEGIN - IF rising_edge(o_clk) THEN - - IF o_ce='1' THEN - -- Output pixels count - IF o_hcpt+1=o_vtotal THEN - o_vcpt_pre3<=0; - ELSIF o_vrr_sync2 THEN - o_vcpt_pre3<=o_vsstart; - o_sync<=false; - ELSE - o_vcpt_pre3<=(o_vcpt_pre3+1) MOD 4096; - END IF; - - o_vcpt_pre2<=o_vcpt_pre3; - o_vcpt_pre<=o_vcpt_pre2; - o_vcpt<=o_vcpt_pre; - END IF; - - o_end(0)<=to_std_logic(o_vcpt>=o_vdisp); - o_dev(0)<=to_std_logic(o_hcpt=o_hmin AND o_hcpt<=o_hmax AND - o_vcpt>=o_vmin AND o_vcpt<=o_vmax); - o_hsv(0)<=to_std_logic(o_hcpt>=o_hsstart AND o_hcpt=o_hsstart) OR - (o_vcpt>o_vsstart AND o_vcpt=o_vmin AND o_vcpt_pre2<=o_vmax); - o_hsv(1 TO 11)<=o_hsv(0 TO 10); - o_vsv(1 TO 11)<=o_vsv(0 TO 10); - o_dev(1 TO 11)<=o_dev(0 TO 10); - o_pev(1 TO 11)<=o_pev(0 TO 10); - o_end(1 TO 11)<=o_end(0 TO 10); - - IF o_run='0' THEN - o_hsv(2)<='0'; - o_vsv(2)<='0'; - o_dev(2)<='0'; - o_pev(2)<='0'; - o_end(2)<='0'; - END IF; - END IF; - - o_vcpt_sync2<=o_vcpt_sync; - o_vrr_min<=(o_vcpt_sync2=o_vdisp AND o_vcpt2 o_radl1<=r2_v; - WHEN "11" => o_radl2<=r2_v; - WHEN "00" => o_radl3<=r2_v; - WHEN OTHERS => o_radl0<=r2_v; - END CASE; - ELSE - CASE o_vacptl IS - WHEN "10" => o_radl2<=r2_v; - WHEN "11" => o_radl3<=r2_v; - WHEN "00" => o_radl0<=r2_v; - WHEN OTHERS => o_radl1<=r2_v; - END CASE; - END IF; - - -- CYCLE 2 ----------------------------------------- - -- Lines reordering - CASE o_vacptl IS - WHEN "10" => pixq_v:=(o_ldr0,o_ldr1,o_ldr2,o_ldr3); - WHEN "11" => pixq_v:=(o_ldr1,o_ldr2,o_ldr3,o_ldr0); - WHEN "00" => pixq_v:=(o_ldr2,o_ldr3,o_ldr0,o_ldr1); - WHEN OTHERS => pixq_v:=(o_ldr3,o_ldr0,o_ldr1,o_ldr2); - END CASE; - - IF fracnn_v = '0' THEN - o_vpix_outer<=(pixq_v(0), pixq_v(2), pixq_v(3)); - o_vpix_inner(0)<=pixq_v(1); - ELSE - o_vpix_outer<=(pixq_v(0), pixq_v(1), pixq_v(3)); - o_vpix_inner(0)<=pixq_v(2); - END IF; - - -- CYCLE 3-7 - o_vpix_inner(1 TO 5)<=o_vpix_inner(0 TO 4); - - -- CYCLE 8 - IF to_integer(o_vacpt)>o_ivsize THEN - IF fracnn_v = '0' THEN - o_vpixq_pre<=(o_vpix_outer(0), o_vpix_inner(5), o_vpix_inner(5), o_vpix_inner(5)); - ELSE - o_vpixq_pre<=(o_vpix_outer(0), o_vpix_outer(1), o_vpix_outer(1), o_vpix_outer(1)); - END IF; - ELSIF to_integer(o_vacpt)=o_ivsize THEN - IF fracnn_v = '0' THEN - o_vpixq_pre<=(o_vpix_outer(0), o_vpix_inner(5), o_vpix_outer(1), o_vpix_outer(1)); - ELSE - o_vpixq_pre<=(o_vpix_outer(0), o_vpix_outer(1), o_vpix_inner(5), o_vpix_inner(5)); - END IF; - ELSE - IF fracnn_v = '0' THEN - o_vpixq_pre<=(o_vpix_outer(0), o_vpix_inner(5), o_vpix_outer(1), o_vpix_outer(2)); - ELSE - o_vpixq_pre<=(o_vpix_outer(0), o_vpix_outer(1), o_vpix_inner(5), o_vpix_outer(2)); - END IF; - END IF; - - -- CYCLE 9 - o_vpixq<=o_vpixq_pre; - - -- BILINEAR / SHARP BILINEAR ----------------------- - -- C8 : Pre-calc Sharp Bilinear - o_v_sbil_t<=sbil_frac1(o_vfrac); - - -- C9 : Select - o_v_bil_frac<=(OTHERS =>'0'); - IF o_vmode(0)='1' THEN -- Bilinear - IF MASK(MASK_BILINEAR)='1' THEN - o_v_bil_frac<=bil_frac(o_vfrac); - END IF; - ELSE -- Sharp Bilinear - IF MASK(MASK_SHARP_BILINEAR)='1' THEN - o_v_bil_frac<=sbil_frac2(o_vfrac,o_v_sbil_t); - END IF; - END IF; - - -- C10 : - o_v_bil_t<=bil_calc(o_v_bil_frac,o_vpixq); - - -- C11 : Nearest / Bilinear / Sharp Bilinear - o_v_bil_pix.r<=bound(o_v_bil_t.r,8+FRAC); - o_v_bil_pix.g<=bound(o_v_bil_t.g,8+FRAC); - o_v_bil_pix.b<=bound(o_v_bil_t.b,8+FRAC); - - -- BICUBIC ----------------------------------------- - -- C9 : Bicubic coefficients A,B,C,D - -- C9 : Bicubic calc T1 = X.D + C - o_v_bic_abcd1<=bic_calc0(o_vfrac,o_vpixq); - o_v_bic_tt1<=bic_calc1(o_vfrac,bic_calc0(o_vfrac,o_vpixq)); - - -- C10 : Bicubic calc T2 = X.T1 + B - o_v_bic_abcd2<=o_v_bic_abcd1; - o_v_bic_tt2<=bic_calc2(o_vfrac,o_v_bic_tt1,o_v_bic_abcd1); - - -- C11 : Bicubic final Y = X.T2 + A - o_v_bic_pix<=bic_calc3(o_vfrac,o_v_bic_tt2,o_v_bic_abcd2); - - -- POLYPHASE --------------------------------------- - -- C3 : Setup luminance - o_v_lum_pix<=o_vpix_inner(0); - - -- C4-C9 in PolyFetch - - -- C10 : Apply polyphase - o_v_poly_t<=poly_calc(o_v_poly_phase,o_vpixq); - - -- C11 : Bound - o_v_poly_pix<=poly_final(o_v_poly_t); - - -- CYCLE 12 ----------------------------------------- - o_hs<=o_hsv(11); - o_vs<=o_vsv(11); - o_de<=o_dev(11); - o_vbl<=o_end(11); - o_r<=x"00"; - o_g<=x"00"; - o_b<=x"00"; - o_brd<= not o_pev(11); - - CASE o_vmode(2 DOWNTO 0) IS - WHEN "000" => -- Nearest - IF MASK(MASK_NEAREST)='1' THEN - o_r<=o_v_poly_pix.r; - o_g<=o_v_poly_pix.g; - o_b<=o_v_poly_pix.b; - END IF; - WHEN "001" | "010" => -- Bilinear | Sharp Bilinear - IF MASK(MASK_BILINEAR)='1' OR - MASK(MASK_SHARP_BILINEAR)='1' THEN - o_r<=o_v_bil_pix.r; - o_g<=o_v_bil_pix.g; - o_b<=o_v_bil_pix.b; - END IF; - WHEN "011" => -- BiCubic - IF MASK(MASK_BICUBIC)='1' THEN - o_r<=o_v_bic_pix.r; - o_g<=o_v_bic_pix.g; - o_b<=o_v_bic_pix.b; - END IF; - - WHEN OTHERS => -- Polyphase - IF MASK(MASK_POLY)='1' THEN - o_r<=o_v_poly_pix.r; - o_g<=o_v_poly_pix.g; - o_b<=o_v_poly_pix.b; - END IF; - END CASE; - - IF o_pev(11)='0' THEN - o_r<=o_border(23 DOWNTO 16); -- Copy border colour - o_g<=o_border(15 DOWNTO 8); - o_b<=o_border(7 DOWNTO 0); - END IF; - - ---------------------------------------------------- - END IF; - END IF; - END PROCESS VSCAL; - - ----------------------------------------------------------------------------- - -- Low Lag syntoniser interface - o_lltune<=(0 => i_vss, - 1 => i_pde, - 2 => i_inter, - 3 => i_flm, - 4 => o_vss, - 5 => i_pce, - 6 => i_clk, - 7 => o_clk, - OTHERS =>'0'); - - ---------------------------------------------------------------------------- -END ARCHITECTURE rtl; diff --git a/sys/audio_out.v b/sys/audio_out.v deleted file mode 100644 index 0f748e0..0000000 --- a/sys/audio_out.v +++ /dev/null @@ -1,296 +0,0 @@ - -module audio_out -#( - parameter CLK_RATE = 24576000 -) -( - input reset, - input clk, - - //0 - 48KHz, 1 - 96KHz - input sample_rate, - - input [31:0] flt_rate, - input [39:0] cx, - input [7:0] cx0, - input [7:0] cx1, - input [7:0] cx2, - input [23:0] cy0, - input [23:0] cy1, - input [23:0] cy2, - - input [4:0] att, - input [1:0] mix, - - input is_signed, - input [15:0] core_l, - input [15:0] core_r, - - input [15:0] alsa_l, - input [15:0] alsa_r, - - // I2S - output i2s_bclk, - output i2s_lrclk, - output i2s_data, - - // SPDIF - output spdif, - - // Sigma-Delta DAC - output dac_l, - output dac_r -); - -localparam AUDIO_RATE = 48000; -localparam AUDIO_DW = 16; - -localparam CE_RATE = AUDIO_RATE*AUDIO_DW*8; -localparam FILTER_DIV = (CE_RATE/(AUDIO_RATE*32))-1; - -wire [31:0] real_ce = sample_rate ? {CE_RATE[30:0],1'b0} : CE_RATE[31:0]; - -reg mclk_ce; -always @(posedge clk) begin - reg [31:0] cnt; - - mclk_ce = 0; - cnt = cnt + real_ce; - if(cnt >= CLK_RATE) begin - cnt = cnt - CLK_RATE; - mclk_ce = 1; - end -end - -reg i2s_ce; -always @(posedge clk) begin - reg div; - i2s_ce <= 0; - if(mclk_ce) begin - div <= ~div; - i2s_ce <= div; - end -end - -i2s i2s -( - .reset(reset), - - .clk(clk), - .ce(i2s_ce), - - .sclk(i2s_bclk), - .lrclk(i2s_lrclk), - .sdata(i2s_data), - - .left_chan(al), - .right_chan(ar) -); - -spdif toslink -( - .rst_i(reset), - - .clk_i(clk), - .bit_out_en_i(mclk_ce), - - .sample_i({ar,al}), - .spdif_o(spdif) -); - -sigma_delta_dac #(15) sd_l -( - .CLK(clk), - .RESET(reset), - .DACin({~al[15], al[14:0]}), - .DACout(dac_l) -); - -sigma_delta_dac #(15) sd_r -( - .CLK(clk), - .RESET(reset), - .DACin({~ar[15], ar[14:0]}), - .DACout(dac_r) -); - -reg sample_ce; -always @(posedge clk) begin - reg [8:0] div = 0; - reg [1:0] add = 0; - - div <= div + add; - if(!div) begin - div <= 2'd1 << sample_rate; - add <= 2'd1 << sample_rate; - end - - sample_ce <= !div; -end - -reg flt_ce; -always @(posedge clk) begin - reg [31:0] cnt = 0; - - flt_ce = 0; - cnt = cnt + {flt_rate[30:0],1'b0}; - if(cnt >= CLK_RATE) begin - cnt = cnt - CLK_RATE; - flt_ce = 1; - end -end - -reg [15:0] cl,cr; -always @(posedge clk) begin - reg [15:0] cl1,cl2; - reg [15:0] cr1,cr2; - - cl1 <= core_l; cl2 <= cl1; - if(cl2 == cl1) cl <= cl2; - - cr1 <= core_r; cr2 <= cr1; - if(cr2 == cr1) cr <= cr2; -end - -reg a_en1 = 0, a_en2 = 0; -always @(posedge clk, posedge reset) begin - reg [1:0] dly1 = 0; - reg [14:0] dly2 = 0; - - if(reset) begin - dly1 <= 0; - dly2 <= 0; - a_en1 <= 0; - a_en2 <= 0; - end - else begin - if(flt_ce) begin - if(~&dly1) dly1 <= dly1 + 1'd1; - else a_en1 <= 1; - end - - if(sample_ce) begin - if(!dly2[13+sample_rate]) dly2 <= dly2 + 1'd1; - else a_en2 <= 1; - end - end -end - -wire [15:0] acl, acr; -IIR_filter #(.use_params(0)) IIR_filter -( - .clk(clk), - .reset(reset), - - .ce(flt_ce & a_en1), - .sample_ce(sample_ce), - - .cx(cx), - .cx0(cx0), - .cx1(cx1), - .cx2(cx2), - .cy0(cy0), - .cy1(cy1), - .cy2(cy2), - - .input_l({~is_signed ^ cl[15], cl[14:0]}), - .input_r({~is_signed ^ cr[15], cr[14:0]}), - .output_l(acl), - .output_r(acr) -); - -wire [15:0] adl; -DC_blocker dcb_l -( - .clk(clk), - .ce(sample_ce), - .sample_rate(sample_rate), - .mute(~a_en2), - .din(acl), - .dout(adl) -); - -wire [15:0] adr; -DC_blocker dcb_r -( - .clk(clk), - .ce(sample_ce), - .sample_rate(sample_rate), - .mute(~a_en2), - .din(acr), - .dout(adr) -); - -wire [15:0] al, audio_l_pre; -aud_mix_top audmix_l -( - .clk(clk), - .ce(sample_ce), - .att(att), - .mix(mix), - - .core_audio(adl), - .pre_in(audio_r_pre), - .linux_audio(alsa_l), - - .pre_out(audio_l_pre), - .out(al) -); - -wire [15:0] ar, audio_r_pre; -aud_mix_top audmix_r -( - .clk(clk), - .ce(sample_ce), - .att(att), - .mix(mix), - - .core_audio(adr), - .pre_in(audio_l_pre), - .linux_audio(alsa_r), - - .pre_out(audio_r_pre), - .out(ar) -); - -endmodule - -module aud_mix_top -( - input clk, - input ce, - - input [4:0] att, - input [1:0] mix, - - input [15:0] core_audio, - input [15:0] linux_audio, - input [15:0] pre_in, - - output reg [15:0] pre_out = 0, - output reg [15:0] out = 0 -); - -reg signed [16:0] a1, a2, a3, a4; -always @(posedge clk) if (ce) begin - - a1 <= {core_audio[15],core_audio}; - a2 <= a1 + {linux_audio[15],linux_audio}; - - pre_out <= a2[16:1]; - - case(mix) - 0: a3 <= a2; - 1: a3 <= $signed(a2) - $signed(a2[16:3]) + $signed(pre_in[15:2]); - 2: a3 <= $signed(a2) - $signed(a2[16:2]) + $signed(pre_in[15:1]); - 3: a3 <= {a2[16],a2[16:1]} + {pre_in[15],pre_in}; - endcase - - if(att[4]) a4 <= 0; - else a4 <= a3 >>> att[3:0]; - - //clamping - out <= ^a4[16:15] ? {a4[16],{15{a4[15]}}} : a4[15:0]; -end - -endmodule diff --git a/sys/build_id.tcl b/sys/build_id.tcl deleted file mode 100644 index b43b9d9..0000000 --- a/sys/build_id.tcl +++ /dev/null @@ -1,73 +0,0 @@ - -# Build TimeStamp Verilog Module -# Jeff Wiencrot - 8/1/2011 -# Sorgelig - 02/11/2019 -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate "`define BUILD_DATE \"[clock format [ clock seconds ] -format %y%m%d]\"" - - # Create a Verilog file for output - set outputFileName "build_id.v" - - set fileData "" - if { [file exists $outputFileName]} { - set outputFile [open $outputFileName "r"] - set fileData [read $outputFile] - close $outputFile - } - - if {$buildDate ne $fileData} { - set outputFile [open $outputFileName "w"] - puts -nonewline $outputFile $buildDate - close $outputFile - # Send confirmation message to the Messages window - post_message "Generated: [pwd]/$outputFileName: $buildDate" - } -} - -# Build CDF file -# Sorgelig - 17/2/2018 -proc generateCDF {revision device outpath} { - - set outputFileName "jtag.cdf" - set outputFile [open $outputFileName "w"] - - puts $outputFile "JedecChain;" - puts $outputFile " FileRevision(JESD32A);" - puts $outputFile " DefaultMfr(6E);" - puts $outputFile "" - puts $outputFile " P ActionCode(Ign)" - puts $outputFile " Device PartName(SOCVHPS) MfrSpec(OpMask(0));" - puts $outputFile " P ActionCode(Cfg)" - puts $outputFile " Device PartName($device) Path(\"$outpath/\") File(\"$revision.sof\") MfrSpec(OpMask(1));" - puts $outputFile "ChainEnd;" - puts $outputFile "" - puts $outputFile "AlteraBegin;" - puts $outputFile " ChainType(JTAG);" - puts $outputFile "AlteraEnd;" -} - -set project_name [lindex $quartus(args) 1] -set revision [lindex $quartus(args) 2] - -if {[project_exists $project_name]} { - if {[string equal "" $revision]} { - project_open $project_name -revision [get_current_revision $project_name] - } else { - project_open $project_name -revision $revision - } -} else { - post_message -type error "Project $project_name does not exist" - exit -} - -set device [get_global_assignment -name DEVICE] -set outpath [get_global_assignment -name PROJECT_OUTPUT_DIRECTORY] - -if [is_project_open] { - project_close -} - -generateBuildID_Verilog -generateCDF $revision $device $outpath diff --git a/sys/ddr_svc.sv b/sys/ddr_svc.sv deleted file mode 100644 index ed24d4e..0000000 --- a/sys/ddr_svc.sv +++ /dev/null @@ -1,108 +0,0 @@ -// -// Copyright (c) 2020 Alexey Melnikov -// -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// ------------------------------------------ -// - -// 16-bit version - -module ddr_svc -( - input clk, - - input ram_waitrequest, - output [7:0] ram_burstcnt, - output [28:0] ram_addr, - input [63:0] ram_readdata, - input ram_read_ready, - output reg ram_read, - output [63:0] ram_writedata, - output [7:0] ram_byteenable, - output reg ram_write, - - output [7:0] ram_bcnt, - - input [31:3] ch0_addr, - input [7:0] ch0_burst, - output [63:0] ch0_data, - input ch0_req, - output ch0_ready, - - input [31:3] ch1_addr, - input [7:0] ch1_burst, - output [63:0] ch1_data, - input ch1_req, - output ch1_ready -); - -assign ram_burstcnt = ram_burst; -assign ram_byteenable = 8'hFF; -assign ram_addr = ram_address; -assign ram_writedata = 0; - -assign ch0_data = ram_q[0]; -assign ch1_data = ram_q[1]; -assign ch0_ready = ready[0]; -assign ch1_ready = ready[1]; - -reg [7:0] ram_burst; -reg [63:0] ram_q[2]; -reg [31:3] ram_address; -reg [1:0] ack = 0; -reg [1:0] ready; -reg state = 0; -reg ch = 0; - -always @(posedge clk) begin - ready <= 0; - - if(!ram_waitrequest) begin - ram_read <= 0; - ram_write <= 0; - - case(state) - 0: if(ch0_req != ack[0]) begin - ack[0] <= ch0_req; - ram_address <= ch0_addr; - ram_burst <= ch0_burst; - ram_read <= 1; - ch <= 0; - ram_bcnt <= 8'hFF; - state <= 1; - end - else if(ch1_req != ack[1]) begin - ack[1] <= ch1_req; - ram_address <= ch1_addr; - ram_burst <= ch1_burst; - ram_read <= 1; - ch <= 1; - ram_bcnt <= 8'hFF; - state <= 1; - end - 1: begin - if(ram_read_ready) begin - ram_bcnt <= ram_bcnt + 1'd1; - ram_q[ch] <= ram_readdata; - ready[ch] <= 1; - if ((ram_bcnt+2'd2) == ram_burst) state <= 0; - end - end - endcase - end -end - -endmodule diff --git a/sys/f2sdram_safe_terminator.sv b/sys/f2sdram_safe_terminator.sv deleted file mode 100644 index 3586365..0000000 --- a/sys/f2sdram_safe_terminator.sv +++ /dev/null @@ -1,250 +0,0 @@ -// ============================================================================ -// -// f2sdram_safe_terminator for MiSTer platform -// -// ============================================================================ -// Copyright (c) 2021 bellwood420 -// -// Background: -// -// Terminating a transaction of burst writing(/reading) in its midstream -// seems to cause an illegal state to f2sdram interface. -// -// Forced reset request that occurs when loading other core is inevitable. -// -// So if it happens exactly within the transaction period, -// unexpected issues with accessing to f2sdram interface will be caused -// in next loaded core. -// -// It seems that only way to reset broken f2sdram interface is to reset -// whole SDRAM Controller Subsystem from HPS via permodrst register -// in Reset Manager. -// But it cannot be done safely while Linux is running. -// It is usually done when cold or warm reset is issued in HPS. -// -// Main_MiSTer is issuing reset for FPGA <> HPS bridges -// via brgmodrst register in Reset Manager when loading rbf. -// But it has no effect on f2sdram interface. -// f2sdram interface seems to belong to SDRAM Controller Subsystem -// rather than FPGA-to-HPS bridge. -// -// Main_MiSTer is also trying to issuing reset for f2sdram ports -// via fpgaportrst register in SDRAM Controller Subsystem when loading rbf. -// But according to the Intel's document, fpgaportrst register can be -// used to stretch the port reset. -// It seems that it cannot be used to assert the port reset. -// -// According to the Intel's document, there seems to be a reset port on -// Avalon-MM slave interface, but it cannot be found in Qsys generated HDL. -// -// To conclude, the only thing FPGA can do is not to break the transaction. -// ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -// -// Purpose: -// To prevent the issue, this module completes ongoing transaction -// on behalf of user logic, when reset is asserted. -// -// Usage: -// Insert this module into the bus line between -// f2sdram (Avalon-MM slave) and user logic (Avalon-MM master). -// -// Notice: -// Asynchronous reset request is not supported. -// Please feed reset request synchronized to clock. -// -module f2sdram_safe_terminator #( - parameter DATA_WIDTH = 64, - parameter BURSTCOUNT_WIDTH = 8 -) ( - // clk should be the same as one provided to f2sdram port - // clk should not be stop when reset is asserted - input clk, - // rst_req_sync should be synchronized to clk - // Asynchronous reset request is not supported - input rst_req_sync, - - // Master port: connecting to Alavon-MM slave(f2sdram) - input waitrequest_master, - output [BURSTCOUNT_WIDTH-1:0] burstcount_master, - output [ADDRESS_WITDH-1:0] address_master, - input [DATA_WIDTH-1:0] readdata_master, - input readdatavalid_master, - output read_master, - output [DATA_WIDTH-1:0] writedata_master, - output [BYTEENABLE_WIDTH-1:0] byteenable_master, - output write_master, - - // Slave port: connecting to Alavon-MM master(user logic) - output waitrequest_slave, - input [BURSTCOUNT_WIDTH-1:0] burstcount_slave, - input [ADDRESS_WITDH-1:0] address_slave, - output [DATA_WIDTH-1:0] readdata_slave, - output readdatavalid_slave, - input read_slave, - input [DATA_WIDTH-1:0] writedata_slave, - input [BYTEENABLE_WIDTH-1:0] byteenable_slave, - input write_slave -); - -localparam BYTEENABLE_WIDTH = DATA_WIDTH/8; -localparam ADDRESS_WITDH = 32-$clog2(BYTEENABLE_WIDTH); - -/* -* Capture init reset deaseert -*/ -reg init_reset_deasserted = 1'b0; - -always_ff @(posedge clk) begin - if (!rst_req_sync) begin - init_reset_deasserted <= 1'b1; - end -end - -/* -* Lock stage -*/ -reg lock_stage = 1'b0; - -always_ff @(posedge clk) begin - if (rst_req_sync) begin - // Reset assert - if (init_reset_deasserted) begin - lock_stage <= 1'b1; - end - end - else begin - // Reset deassert - lock_stage <= 1'b0; - end -end - -/* -* Write burst transaction observer -*/ -reg state_write = 1'b0; -wire next_state_write; - -wire burst_write_start = !state_write && next_state_write; -wire valid_write_data = state_write && !waitrequest_master; -wire burst_write_end = state_write && (write_burstcounter == write_burstcount_latch - 1'd1); -wire valid_non_burst_write = !state_write && write_slave && (burstcount_slave == 1) && !waitrequest_master; - -reg [BURSTCOUNT_WIDTH-1:0] write_burstcounter = 0; -reg [BURSTCOUNT_WIDTH-1:0] write_burstcount_latch = 0; -reg [ADDRESS_WITDH-1:0] write_address_latch = 0; - -always_ff @(posedge clk) begin - state_write <= next_state_write; - - if (burst_write_start) begin - write_burstcounter <= waitrequest_master ? 1'd0 : 1'd1; - write_burstcount_latch <= burstcount_slave; - write_address_latch <= address_slave; - end - else if (valid_write_data) begin - write_burstcounter <= write_burstcounter + 1'd1; - end -end - -always_comb begin - if (!state_write) begin - if (valid_non_burst_write) - next_state_write = 1'b0; - else if (write_slave) - next_state_write = 1'b1; - else - next_state_write = 1'b0; - end - else begin - if (burst_write_end) - next_state_write = 1'b0; - else - next_state_write = 1'b1; - end -end - -reg [BURSTCOUNT_WIDTH-1:0] write_terminate_counter = 0; -reg [BURSTCOUNT_WIDTH-1:0] burstcount_latch = 0; -reg [ADDRESS_WITDH-1:0] address_latch = 0; - -reg terminating = 0; -reg read_terminating = 0; -reg write_terminating = 0; - -wire on_write_transaction = state_write && next_state_write; -wire on_start_write_transaction = !state_write && next_state_write; - -always_ff @(posedge clk) begin - if (rst_req_sync) begin - // Reset assert - if (init_reset_deasserted) begin - if (!lock_stage) begin - // Even not knowing reading is in progress or not, - // if it is in progress, it will finish at some point, and no need to do anything. - // Assume that reading is in progress when we are not on write transaction. - burstcount_latch <= burstcount_slave; - address_latch <= address_slave; - terminating <= 1; - - if (on_write_transaction) begin - write_terminating <= 1; - burstcount_latch <= write_burstcount_latch; - address_latch <= write_address_latch; - write_terminate_counter <= waitrequest_master ? write_burstcounter : write_burstcounter + 1'd1; - end - else if (on_start_write_transaction) begin - if (!valid_non_burst_write) begin - write_terminating <= 1; - write_terminate_counter <= waitrequest_master ? 1'd0 : 1'd1; - end - end - else if (read_slave && waitrequest_master) begin - // Need to keep read signal, burstcount and address until waitrequest_master deasserted - read_terminating <= 1; - end - end - else if (!waitrequest_master) begin - read_terminating <= 0; - end - end - end - else begin - // Reset deassert - if (!write_terminating) terminating <= 0; - read_terminating <= 0; - end - - if (write_terminating) begin - // Continue write transaction until the end - if (!waitrequest_master) write_terminate_counter <= write_terminate_counter + 1'd1; - if (write_terminate_counter == burstcount_latch - 1'd1) write_terminating <= 0; - end -end - -/* -* Bus mux depending on the stage. -*/ -always_comb begin - if (terminating) begin - burstcount_master = burstcount_latch; - address_master = address_latch; - read_master = read_terminating; - write_master = write_terminating; - byteenable_master = 0; - end - else begin - burstcount_master = burstcount_slave; - address_master = address_slave; - read_master = read_slave; - byteenable_master = byteenable_slave; - write_master = write_slave; - end -end - -// Just passing master <-> slave -assign writedata_master = writedata_slave; -assign readdata_slave = readdata_master; -assign readdatavalid_slave = readdatavalid_master; -assign waitrequest_slave = waitrequest_master; - -endmodule diff --git a/sys/gamma_corr.sv b/sys/gamma_corr.sv deleted file mode 100644 index 321b83f..0000000 --- a/sys/gamma_corr.sv +++ /dev/null @@ -1,124 +0,0 @@ -module gamma_corr -( - input clk_sys, - input clk_vid, - input ce_pix, - input gamma_en, - input gamma_wr, - input [9:0] gamma_wr_addr, - input [7:0] gamma_value, - input HSync, - input VSync, - input HBlank, - input VBlank, - input [23:0] RGB_in, - output reg HSync_out, - output reg VSync_out, - output reg HBlank_out, - output reg VBlank_out, - output reg [23:0] RGB_out -); - -(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve[768]; - -always @(posedge clk_sys) if (gamma_wr) gamma_curve[gamma_wr_addr] <= gamma_value; -always @(posedge clk_vid) gamma <= gamma_curve[gamma_index]; - -reg [9:0] gamma_index; -reg [7:0] gamma; - -always @(posedge clk_vid) begin - reg [7:0] R_in, G_in, B_in; - reg [7:0] R_gamma, G_gamma; - reg hs,vs,hb,vb; - reg [1:0] ctr = 0; - reg old_ce; - - old_ce <= ce_pix; - if(~old_ce & ce_pix) begin - {R_in,G_in,B_in} <= RGB_in; - hs <= HSync; vs <= VSync; - hb <= HBlank; vb <= VBlank; - - RGB_out <= gamma_en ? {R_gamma,G_gamma,gamma} : {R_in,G_in,B_in}; - HSync_out <= hs; VSync_out <= vs; - HBlank_out <= hb; VBlank_out <= vb; - - ctr <= 1; - gamma_index <= {2'b00,RGB_in[23:16]}; - end - - if (|ctr) ctr <= ctr + 1'd1; - - case(ctr) - 1: begin gamma_index <= {2'b01,G_in}; end - 2: begin R_gamma <= gamma; gamma_index <= {2'b10,B_in}; end - 3: begin G_gamma <= gamma; end - endcase -end - -endmodule - -module gamma_fast -( - input clk_vid, - input ce_pix, - - inout [21:0] gamma_bus, - - input HSync, - input VSync, - input HBlank, - input VBlank, - input DE, - input [23:0] RGB_in, - - output reg HSync_out, - output reg VSync_out, - output reg HBlank_out, - output reg VBlank_out, - output reg DE_out, - output reg [23:0] RGB_out -); - -(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve_r[256]; -(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve_g[256]; -(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve_b[256]; - -assign gamma_bus[21] = 1; -wire clk_sys = gamma_bus[20]; -wire gamma_en = gamma_bus[19]; -wire gamma_wr = gamma_bus[18]; -wire [9:0] gamma_wr_addr = gamma_bus[17:8]; -wire [7:0] gamma_value = gamma_bus[7:0]; - -always @(posedge clk_sys) if (gamma_wr) begin - case(gamma_wr_addr[9:8]) - 0: gamma_curve_r[gamma_wr_addr[7:0]] <= gamma_value; - 1: gamma_curve_g[gamma_wr_addr[7:0]] <= gamma_value; - 2: gamma_curve_b[gamma_wr_addr[7:0]] <= gamma_value; - endcase -end - -reg [7:0] gamma_index_r,gamma_index_g,gamma_index_b; - -always @(posedge clk_vid) begin - reg [7:0] R_in, G_in, B_in; - reg [7:0] R_gamma, G_gamma; - reg hs,vs,hb,vb,de; - - if(ce_pix) begin - {gamma_index_r,gamma_index_g,gamma_index_b} <= RGB_in; - hs <= HSync; vs <= VSync; - hb <= HBlank; vb <= VBlank; - de <= DE; - - RGB_out <= gamma_en ? {gamma_curve_r[gamma_index_r],gamma_curve_g[gamma_index_g],gamma_curve_b[gamma_index_b]} - : {gamma_index_r,gamma_index_g,gamma_index_b}; - HSync_out <= hs; VSync_out <= vs; - HBlank_out <= hb; VBlank_out <= vb; - DE_out <= de; - end -end - -endmodule diff --git a/sys/hps_io.sv b/sys/hps_io.sv deleted file mode 100644 index 45510a9..0000000 --- a/sys/hps_io.sv +++ /dev/null @@ -1,1039 +0,0 @@ -// -// hps_io.v -// -// Copyright (c) 2014 Till Harbaum -// Copyright (c) 2017-2020 Alexey Melnikov -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -/////////////////////////////////////////////////////////////////////// -// altera message_off 10665 - -// -// Use buffer to access SD card. It's time-critical part. -// -// WIDE=1 for 16 bit file I/O -// VDNUM 1..10 -// BLKSZ 0..7: 0 = 128, 1 = 256, 2 = 512(default), .. 7 = 16384 -// -module hps_io #(parameter CONF_STR, CONF_STR_BRAM=1, PS2DIV=0, WIDE=0, VDNUM=1, BLKSZ=2, PS2WE=0) -( - input clk_sys, - inout [48:0] HPS_BUS, - - // buttons up to 32 - output reg [31:0] joystick_0, - output reg [31:0] joystick_1, - output reg [31:0] joystick_2, - output reg [31:0] joystick_3, - output reg [31:0] joystick_4, - output reg [31:0] joystick_5, - - // analog -127..+127, Y: [15:8], X: [7:0] - output reg [15:0] joystick_l_analog_0, - output reg [15:0] joystick_l_analog_1, - output reg [15:0] joystick_l_analog_2, - output reg [15:0] joystick_l_analog_3, - output reg [15:0] joystick_l_analog_4, - output reg [15:0] joystick_l_analog_5, - - output reg [15:0] joystick_r_analog_0, - output reg [15:0] joystick_r_analog_1, - output reg [15:0] joystick_r_analog_2, - output reg [15:0] joystick_r_analog_3, - output reg [15:0] joystick_r_analog_4, - output reg [15:0] joystick_r_analog_5, - - input [15:0] joystick_0_rumble, // 15:8 - 'large' rumble motor magnitude, 7:0 'small' rumble motor magnitude - input [15:0] joystick_1_rumble, - input [15:0] joystick_2_rumble, - input [15:0] joystick_3_rumble, - input [15:0] joystick_4_rumble, - input [15:0] joystick_5_rumble, - - // paddle 0..255 - output reg [7:0] paddle_0, - output reg [7:0] paddle_1, - output reg [7:0] paddle_2, - output reg [7:0] paddle_3, - output reg [7:0] paddle_4, - output reg [7:0] paddle_5, - - // spinner [7:0] -128..+127, [8] - toggle with every update - output reg [8:0] spinner_0, - output reg [8:0] spinner_1, - output reg [8:0] spinner_2, - output reg [8:0] spinner_3, - output reg [8:0] spinner_4, - output reg [8:0] spinner_5, - - // ps2 keyboard emulation - output ps2_kbd_clk_out, - output ps2_kbd_data_out, - input ps2_kbd_clk_in, - input ps2_kbd_data_in, - - input [2:0] ps2_kbd_led_status, - input [2:0] ps2_kbd_led_use, - - output ps2_mouse_clk_out, - output ps2_mouse_data_out, - input ps2_mouse_clk_in, - input ps2_mouse_data_in, - - // ps2 alternative interface. - - // [8] - extended, [9] - pressed, [10] - toggles with every press/release - output reg [10:0] ps2_key = 0, - - // [24] - toggles with every event - output reg [24:0] ps2_mouse = 0, - output reg [15:0] ps2_mouse_ext = 0, // 15:8 - reserved(additional buttons), 7:0 - wheel movements - - output [1:0] buttons, - output forced_scandoubler, - output direct_video, - input video_rotated, - - //toggle to force notify of video mode change - input new_vmode, - - inout [21:0] gamma_bus, - - output reg [127:0] status, - input [127:0] status_in, - input status_set, - input [15:0] status_menumask, - - input info_req, - input [7:0] info, - - // SD config - output reg [VD:0] img_mounted, // signaling that new image has been mounted - output reg img_readonly, // mounted as read only. valid only for active bit in img_mounted - output reg [63:0] img_size, // size of image in bytes. valid only for active bit in img_mounted - - // SD block level access - input [31:0] sd_lba[VDNUM], - input [5:0] sd_blk_cnt[VDNUM], // number of blocks-1, total size ((sd_blk_cnt+1)*(1<<(BLKSZ+7))) must be <= 16384! - input [VD:0] sd_rd, - input [VD:0] sd_wr, - output reg [VD:0] sd_ack, - - // SD byte level access. Signals for 2-PORT altsyncram. - output reg [AW:0] sd_buff_addr, - output reg [DW:0] sd_buff_dout, - input [DW:0] sd_buff_din[VDNUM], - output reg sd_buff_wr, - - // ARM -> FPGA download - output reg ioctl_download = 0, // signal indicating an active download - output reg [15:0] ioctl_index, // menu index used to upload the file - output reg ioctl_wr, - output reg [26:0] ioctl_addr, // in WIDE mode address will be incremented by 2 - output reg [DW:0] ioctl_dout, - output reg ioctl_upload = 0, // signal indicating an active upload - input ioctl_upload_req, // request to save (must be supported on HPS side for specific core) - input [7:0] ioctl_upload_index, - input [DW:0] ioctl_din, - output reg ioctl_rd, - output reg [31:0] ioctl_file_ext, - input ioctl_wait, - - // [15]: 0 - unset, 1 - set. [1:0]: 0 - none, 1 - 32MB, 2 - 64MB, 3 - 128MB - // [14]: debug mode: [8]: 1 - phase up, 0 - phase down. [7:0]: amount of shift. - output reg [15:0] sdram_sz, - - // RTC MSM6242B layout - output reg [64:0] RTC, - - // Seconds since 1970-01-01 00:00:00 - output reg [32:0] TIMESTAMP, - - // UART flags - output reg [7:0] uart_mode, - output reg [31:0] uart_speed, - - // for core-specific extensions - inout [35:0] EXT_BUS -); - -assign EXT_BUS[31:16] = HPS_BUS[31:16]; -assign EXT_BUS[35:33] = HPS_BUS[35:33]; - -localparam DW = (WIDE) ? 15 : 7; -localparam AW = (WIDE) ? 12 : 13; -localparam VD = VDNUM-1; - -wire io_strobe= HPS_BUS[33]; -wire io_enable= HPS_BUS[34]; -wire fp_enable= HPS_BUS[35]; -wire io_wide = (WIDE) ? 1'b1 : 1'b0; -wire [15:0] io_din = HPS_BUS[31:16]; -reg [15:0] io_dout; - -assign HPS_BUS[37] = ioctl_wait; -assign HPS_BUS[36] = clk_sys; -assign HPS_BUS[32] = io_wide; -assign HPS_BUS[15:0] = EXT_BUS[32] ? EXT_BUS[15:0] : fp_enable ? fp_dout : io_dout; - -reg [15:0] cfg; -assign buttons = cfg[1:0]; -//cfg[2] - vga_scaler handled in sys_top -//cfg[3] - csync handled in sys_top -assign forced_scandoubler = cfg[4]; -//cfg[5] - ypbpr handled in sys_top -assign direct_video = cfg[10]; - -reg [3:0] sdn; -reg [3:0] sd_rrb = 0; -always_comb begin - int n, i; - - sdn = 0; - for(i = VDNUM - 1; i >= 0; i = i - 1) begin - n = i + sd_rrb; - if(n >= VDNUM) n = n - VDNUM; - if(sd_wr[n] | sd_rd[n]) sdn = n[3:0]; - end -end - -///////////////////////////////////////////////////////// - -wire [15:0] vc_dout; -video_calc video_calc -( - .clk_100(HPS_BUS[43]), - .clk_vid(HPS_BUS[42]), - .clk_sys(clk_sys), - .ce_pix(HPS_BUS[41]), - .de(HPS_BUS[40]), - .hs(HPS_BUS[39]), - .vs(HPS_BUS[38]), - .vs_hdmi(HPS_BUS[44]), - .f1(HPS_BUS[45]), - .new_vmode(new_vmode), - .video_rotated(video_rotated), - - .par_num(byte_cnt[4:0]), - .dout(vc_dout) -); - -///////////////////////////////////////////////////////// - -localparam STRLEN = $size(CONF_STR)>>3; -localparam MAX_W = $clog2((32 > (STRLEN+2)) ? 32 : (STRLEN+2))-1; - -wire [7:0] conf_byte; -generate - if(CONF_STR_BRAM) begin - confstr_rom #(CONF_STR, STRLEN) confstr_rom(.*, .conf_addr(byte_cnt - 1'd1)); - end - else begin - assign conf_byte = CONF_STR[{(STRLEN - byte_cnt),3'b000} +:8]; - end -endgenerate - -assign gamma_bus[20:0] = {clk_sys, gamma_en, gamma_wr, gamma_wr_addr, gamma_value}; -reg gamma_en; -reg gamma_wr; -reg [9:0] gamma_wr_addr; -reg [7:0] gamma_value; - -reg [31:0] ps2_key_raw = 0; -wire pressed = (ps2_key_raw[15:8] != 8'hf0); -wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0)); - -reg [MAX_W:0] byte_cnt; -reg [3:0] sdn_ack; -wire [15:0] disk = 16'd1 << io_din[11:8]; - -always@(posedge clk_sys) begin : uio_block - reg [15:0] cmd; - reg [2:0] b_wr; - reg [3:0] stick_idx; - reg [3:0] pdsp_idx; - reg ps2skip = 0; - reg [3:0] stflg = 0; - reg[127:0] status_req; - reg old_status_set = 0; - reg old_upload_req = 0; - reg upload_req = 0; - reg old_info = 0; - reg [7:0] info_n = 0; - reg [15:0] tmp1; - reg [7:0] tmp2; - reg [3:0] sdn_r; - - old_status_set <= status_set; - if(~old_status_set & status_set) begin - stflg <= stflg + 1'd1; - status_req <= status_in; - end - - old_upload_req <= ioctl_upload_req; - if(~old_upload_req & ioctl_upload_req) upload_req <= 1; - - old_info <= info_req; - if(~old_info & info_req) info_n <= info; - - sd_buff_wr <= b_wr[0]; - if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1; - b_wr <= (b_wr<<1); - - if(PS2DIV) {kbd_rd,kbd_we,mouse_rd,mouse_we} <= 0; - - gamma_wr <= 0; - - if(~io_enable) begin - if(cmd == 4 && !ps2skip) ps2_mouse[24] <= ~ps2_mouse[24]; - if(cmd == 5 && !ps2skip) begin - ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]}; - if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed - if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released - if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed - end - if(cmd == 'h22) RTC[64] <= ~RTC[64]; - if(cmd == 'h24) TIMESTAMP[32] <= ~TIMESTAMP[32]; - cmd <= 0; - byte_cnt <= 0; - sd_ack <= 0; - io_dout <= 0; - ps2skip <= 0; - img_mounted <= 0; - end - else if(io_strobe) begin - - io_dout <= 0; - if(~&byte_cnt) byte_cnt <= byte_cnt + 1'd1; - - if(byte_cnt == 0) begin - cmd <= io_din; - - casex(io_din) - 'h16: begin io_dout <= {1'b1, sd_blk_cnt[sdn], BLKSZ[2:0], sdn, sd_wr[sdn], sd_rd[sdn]}; sdn_r <= sdn; end - 'h0X17, - 'h0X18: begin sd_ack <= disk[VD:0]; sdn_ack <= io_din[11:8]; end - 'h29: io_dout <= {4'hA, stflg}; -`ifdef MISTER_DISABLE_ADAPTIVE - 'h2B: io_dout <= {HPS_BUS[48:46],4'b0110}; -`else - 'h2B: io_dout <= {HPS_BUS[48:46],4'b0111}; -`endif - 'h2F: io_dout <= 1; - 'h32: io_dout <= gamma_bus[21]; - 'h36: begin io_dout <= info_n; info_n <= 0; end - 'h39: io_dout <= 1; - 'h3C: if(upload_req) begin io_dout <= {ioctl_upload_index, 8'd1}; upload_req <= 0; end - 'h3E: io_dout <= 1; // shadow mask - 'h003F: io_dout <= joystick_0_rumble; - 'h013F: io_dout <= joystick_1_rumble; - 'h023F: io_dout <= joystick_2_rumble; - 'h033F: io_dout <= joystick_3_rumble; - 'h043F: io_dout <= joystick_4_rumble; - 'h053F: io_dout <= joystick_5_rumble; - endcase - - sd_buff_addr <= 0; - if(io_din == 5) ps2_key_raw <= 0; - end else begin - - casex(cmd) - // buttons and switches - 'h01: cfg <= io_din; - 'h02: if(byte_cnt==1) joystick_0[15:0] <= io_din; else joystick_0[31:16] <= io_din; - 'h03: if(byte_cnt==1) joystick_1[15:0] <= io_din; else joystick_1[31:16] <= io_din; - 'h10: if(byte_cnt==1) joystick_2[15:0] <= io_din; else joystick_2[31:16] <= io_din; - 'h11: if(byte_cnt==1) joystick_3[15:0] <= io_din; else joystick_3[31:16] <= io_din; - 'h12: if(byte_cnt==1) joystick_4[15:0] <= io_din; else joystick_4[31:16] <= io_din; - 'h13: if(byte_cnt==1) joystick_5[15:0] <= io_din; else joystick_5[31:16] <= io_din; - - // store incoming ps2 mouse bytes - 'h04: begin - if(PS2DIV) begin - mouse_data <= io_din[7:0]; - mouse_we <= 1; - end - if(&io_din[15:8]) ps2skip <= 1; - if(~&io_din[15:8] && ~ps2skip && !byte_cnt[MAX_W:2]) begin - case(byte_cnt[1:0]) - 1: ps2_mouse[7:0] <= io_din[7:0]; - 2: ps2_mouse[15:8] <= io_din[7:0]; - 3: ps2_mouse[23:16] <= io_din[7:0]; - endcase - case(byte_cnt[1:0]) - 1: ps2_mouse_ext[7:0] <= {io_din[14], io_din[14:8]}; - 2: ps2_mouse_ext[11:8] <= io_din[11:8]; - 3: ps2_mouse_ext[15:12]<= io_din[11:8]; - endcase - end - end - - // store incoming ps2 keyboard bytes - 'h05: begin - if(&io_din[15:8]) ps2skip <= 1; - if(~&io_din[15:8] & ~ps2skip) ps2_key_raw[31:0] <= {ps2_key_raw[23:0], io_din[7:0]}; - if(PS2DIV) begin - kbd_data <= io_din[7:0]; - kbd_we <= 1; - end - end - - // reading config string, returning a byte from string - 'h14: if(byte_cnt <= STRLEN) io_dout[7:0] <= conf_byte; - - // reading sd card status - 'h16: if(!byte_cnt[MAX_W:2]) begin - case(byte_cnt[1:0]) - 1: sd_rrb <= (sd_rrb == VD) ? 4'd0 : (sd_rrb + 1'd1); - 2: io_dout <= sd_lba[sdn_r][15:0]; - 3: io_dout <= sd_lba[sdn_r][31:16]; - endcase - end - - // send sector IO -> FPGA - // flag that download begins - 'h0X17: begin - sd_buff_dout <= io_din[DW:0]; - b_wr <= 1; - end - - // reading sd card write data - 'h0X18: begin - if(~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; - io_dout <= sd_buff_din[sdn_ack]; - end - - // joystick left analog - 'h1a: if(!byte_cnt[MAX_W:2]) begin - case(byte_cnt[1:0]) - 1: {pdsp_idx,stick_idx} <= io_din[7:0]; // first byte is joystick index - 2: case(stick_idx) - 0: joystick_l_analog_0 <= io_din; - 1: joystick_l_analog_1 <= io_din; - 2: joystick_l_analog_2 <= io_din; - 3: joystick_l_analog_3 <= io_din; - 4: joystick_l_analog_4 <= io_din; - 5: joystick_l_analog_5 <= io_din; - 15: case(pdsp_idx) - 0: paddle_0 <= io_din[7:0]; - 1: paddle_1 <= io_din[7:0]; - 2: paddle_2 <= io_din[7:0]; - 3: paddle_3 <= io_din[7:0]; - 4: paddle_4 <= io_din[7:0]; - 5: paddle_5 <= io_din[7:0]; - 8: spinner_0 <= {~spinner_0[8],io_din[7:0]}; - 9: spinner_1 <= {~spinner_1[8],io_din[7:0]}; - 10: spinner_2 <= {~spinner_2[8],io_din[7:0]}; - 11: spinner_3 <= {~spinner_3[8],io_din[7:0]}; - 12: spinner_4 <= {~spinner_4[8],io_din[7:0]}; - 13: spinner_5 <= {~spinner_5[8],io_din[7:0]}; - endcase - endcase - endcase - end - - // joystick right analog - 'h3d: if(!byte_cnt[MAX_W:2]) begin - case(byte_cnt[1:0]) - 1: stick_idx <= io_din[3:0]; // first byte is joystick index - 2: case(stick_idx) - 0: joystick_r_analog_0 <= io_din; - 1: joystick_r_analog_1 <= io_din; - 2: joystick_r_analog_2 <= io_din; - 3: joystick_r_analog_3 <= io_din; - 4: joystick_r_analog_4 <= io_din; - 5: joystick_r_analog_5 <= io_din; - endcase - endcase - end - - // notify image selection - 'h1c: begin - img_mounted <= io_din[VD:0] ? io_din[VD:0] : 1'b1; - img_readonly <= io_din[7]; - end - - // send image info - 'h1d: if(byte_cnt<5) img_size[{byte_cnt-1'b1, 4'b0000} +:16] <= io_din; - - // status, 128bit version - 'h1e: if(!byte_cnt[MAX_W:4]) begin - case(byte_cnt[3:0]) - 1: status[15:00] <= io_din; - 2: status[31:16] <= io_din; - 3: status[47:32] <= io_din; - 4: status[63:48] <= io_din; - 5: status[79:64] <= io_din; - 6: status[95:80] <= io_din; - 7: status[111:96] <= io_din; - 8: status[127:112] <= io_din; - endcase - end - - // reading keyboard LED status - 'h1f: io_dout <= {|PS2WE, 2'b01, ps2_kbd_led_status[2], ps2_kbd_led_use[2], ps2_kbd_led_status[1], ps2_kbd_led_use[1], ps2_kbd_led_status[0], ps2_kbd_led_use[0]}; - - // reading ps2 keyboard/mouse control - 'h21: if(PS2DIV) begin - if(byte_cnt == 1) begin - io_dout <= kbd_data_host; - kbd_rd <= 1; - end - else - if(byte_cnt == 2) begin - io_dout <= mouse_data_host; - mouse_rd <= 1; - end - end - - //RTC - 'h22: RTC[(byte_cnt-6'd1)<<4 +:16] <= io_din; - - //Video res. - 'h23: if(!byte_cnt[MAX_W:5]) io_dout <= vc_dout; - - //RTC - 'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din; - - //status set - 'h29: if(!byte_cnt[MAX_W:4]) begin - case(byte_cnt[3:0]) - 1: io_dout <= status_req[15:00]; - 2: io_dout <= status_req[31:16]; - 3: io_dout <= status_req[47:32]; - 4: io_dout <= status_req[63:48]; - 5: io_dout <= status_req[79:64]; - 6: io_dout <= status_req[95:80]; - 7: io_dout <= status_req[111:96]; - 8: io_dout <= status_req[127:112]; - endcase - end - - //menu mask - 'h2E: if(byte_cnt == 1) io_dout <= status_menumask; - - //sdram size set - 'h31: if(byte_cnt == 1) sdram_sz <= io_din; - - // Gamma - 'h32: gamma_en <= io_din[0]; - 'h33: begin - gamma_wr_addr <= {(byte_cnt[1:0]-1'b1),io_din[15:8]}; - {gamma_wr, gamma_value} <= {1'b1,io_din[7:0]}; - if (byte_cnt[1:0] == 3) byte_cnt <= 1; - end - - // UART - 'h3b: if(!byte_cnt[MAX_W:2]) begin - case(byte_cnt[1:0]) - 1: tmp2 <= io_din[7:0]; - 2: tmp1 <= io_din; - 3: {uart_speed, uart_mode} <= {io_din, tmp1, tmp2}; - endcase - end - endcase - end - end -end - - -/////////////////////////////// PS2 /////////////////////////////// -generate - if(PS2DIV) begin - reg clk_ps2; - always @(posedge clk_sys) begin - integer cnt; - cnt <= cnt + 1'd1; - if(cnt == PS2DIV) begin - clk_ps2 <= ~clk_ps2; - cnt <= 0; - end - end - - reg [7:0] kbd_data; - reg kbd_we; - wire [8:0] kbd_data_host; - reg kbd_rd; - - ps2_device keyboard - ( - .clk_sys(clk_sys), - - .wdata(kbd_data), - .we(kbd_we), - - .ps2_clk(clk_ps2), - .ps2_clk_out(ps2_kbd_clk_out), - .ps2_dat_out(ps2_kbd_data_out), - - .ps2_clk_in(ps2_kbd_clk_in || !PS2WE), - .ps2_dat_in(ps2_kbd_data_in || !PS2WE), - - .rdata(kbd_data_host), - .rd(kbd_rd) - ); - - reg [7:0] mouse_data; - reg mouse_we; - wire [8:0] mouse_data_host; - reg mouse_rd; - - ps2_device mouse - ( - .clk_sys(clk_sys), - - .wdata(mouse_data), - .we(mouse_we), - - .ps2_clk(clk_ps2), - .ps2_clk_out(ps2_mouse_clk_out), - .ps2_dat_out(ps2_mouse_data_out), - - .ps2_clk_in(ps2_mouse_clk_in || !PS2WE), - .ps2_dat_in(ps2_mouse_data_in || !PS2WE), - - .rdata(mouse_data_host), - .rd(mouse_rd) - ); - end - else begin - assign ps2_kbd_clk_out = 0; - assign ps2_kbd_data_out = 0; - assign ps2_mouse_clk_out = 0; - assign ps2_mouse_data_out = 0; - end -endgenerate - -/////////////////////////////// DOWNLOADING /////////////////////////////// - -localparam FIO_FILE_TX = 8'h53; -localparam FIO_FILE_TX_DAT = 8'h54; -localparam FIO_FILE_INDEX = 8'h55; -localparam FIO_FILE_INFO = 8'h56; - -reg [15:0] fp_dout; -always@(posedge clk_sys) begin : fio_block - reg [15:0] cmd; - reg [2:0] cnt; - reg has_cmd; - reg [26:0] addr; - reg wr; - - ioctl_rd <= 0; - ioctl_wr <= wr; - wr <= 0; - - if(~fp_enable) has_cmd <= 0; - else begin - if(io_strobe) begin - - if(!has_cmd) begin - cmd <= io_din; - has_cmd <= 1; - cnt <= 0; - end else begin - - case(cmd) - FIO_FILE_INFO: - if(~cnt[1]) begin - case(cnt) - 0: ioctl_file_ext[31:16] <= io_din; - 1: ioctl_file_ext[15:00] <= io_din; - endcase - cnt <= cnt + 1'd1; - end - - FIO_FILE_INDEX: - begin - ioctl_index <= io_din[15:0]; - end - - FIO_FILE_TX: - begin - cnt <= cnt + 1'd1; - case(cnt) - 0: if(io_din[7:0] == 8'hAA) begin - ioctl_addr <= 0; - ioctl_upload <= 1; - ioctl_rd <= 1; - end - else if(io_din[7:0]) begin - addr <= 0; - ioctl_download <= 1; - end - else begin - if(ioctl_download) ioctl_addr <= addr; - ioctl_download <= 0; - ioctl_upload <= 0; - end - - 1: begin - ioctl_addr[15:0] <= io_din; - addr[15:0] <= io_din; - end - - 2: begin - ioctl_addr[26:16] <= io_din[10:0]; - addr[26:16] <= io_din[10:0]; - end - endcase - end - - FIO_FILE_TX_DAT: - if(ioctl_download) begin - ioctl_addr <= addr; - ioctl_dout <= io_din[DW:0]; - wr <= 1; - addr <= addr + (WIDE ? 2'd2 : 2'd1); - end - else begin - ioctl_addr <= ioctl_addr + (WIDE ? 2'd2 : 2'd1); - fp_dout <= ioctl_din; - ioctl_rd <= 1; - end - endcase - end - end - end -end - -endmodule - -////////////////////////////////////////////////////////////////////////////////// - - -module ps2_device #(parameter PS2_FIFO_BITS=5) -( - input clk_sys, - - input [7:0] wdata, - input we, - - input ps2_clk, - output reg ps2_clk_out, - output reg ps2_dat_out, - output reg tx_empty, - - input ps2_clk_in, - input ps2_dat_in, - - output [8:0] rdata, - input rd -); - - -(* ramstyle = "logic" *) reg [7:0] fifo[1<= 1)&&(tx_state < 9)) begin - ps2_dat_out <= tx_byte[0]; // data bits - tx_byte[6:0] <= tx_byte[7:1]; // shift down - if(tx_byte[0]) - parity <= !parity; - end - - // transmission of parity - if(tx_state == 9) ps2_dat_out <= parity; - - // transmission of stop bit - if(tx_state == 10) ps2_dat_out <= 1; // stop bit is 1 - - // advance state machine - if(tx_state < 11) tx_state <= tx_state + 1'd1; - else tx_state <= 0; - end - end - end - - if(~old_clk & ps2_clk) ps2_clk_out <= 1; - if(old_clk & ~ps2_clk) ps2_clk_out <= ((tx_state == 0) && (rx_state<2)); - -end - -endmodule - - -///////////////// calc video parameters ////////////////// -module video_calc -( - input clk_100, - input clk_vid, - input clk_sys, - - input ce_pix, - input de, - input hs, - input vs, - input vs_hdmi, - input f1, - input new_vmode, - input video_rotated, - - input [4:0] par_num, - output reg [15:0] dout -); - -always @(posedge clk_sys) begin - case(par_num) - 1: dout <= {video_rotated, |vid_int, vid_nres}; - 2: dout <= vid_hcnt[15:0]; - 3: dout <= vid_hcnt[31:16]; - 4: dout <= vid_vcnt[15:0]; - 5: dout <= vid_vcnt[31:16]; - 6: dout <= vid_htime[15:0]; - 7: dout <= vid_htime[31:16]; - 8: dout <= vid_vtime[15:0]; - 9: dout <= vid_vtime[31:16]; - 10: dout <= vid_pix[15:0]; - 11: dout <= vid_pix[31:16]; - 12: dout <= vid_vtime_hdmi[15:0]; - 13: dout <= vid_vtime_hdmi[31:16]; - 14: dout <= vid_ccnt[15:0]; - 15: dout <= vid_ccnt[31:16]; - 16: dout <= vid_pixrep; - 17: dout <= vid_de_h; - 18: dout <= vid_de_v; - default dout <= 0; - endcase -end - -reg [31:0] vid_hcnt = 0; -reg [31:0] vid_vcnt = 0; -reg [31:0] vid_ccnt = 0; -reg [7:0] vid_nres = 0; -reg [1:0] vid_int = 0; -reg [7:0] vid_pixrep; -reg [15:0] vid_de_h; -reg [7:0] vid_de_v; - -always @(posedge clk_vid) begin - integer hcnt; - integer vcnt; - integer ccnt; - reg [7:0] pcnt; - reg [7:0] de_v; - reg [15:0] de_h; - reg old_vs = 0, old_hs = 0, old_hs_vclk = 0, old_de = 0, old_de_vclk = 0, old_de1 = 0, old_vmode = 0; - reg [3:0] resto = 0; - reg calch = 0; - - if(calch & de) ccnt <= ccnt + 1; - pcnt <= pcnt + 1'd1; - - old_hs_vclk <= hs; - de_h <= de_h + 1'd1; - if(old_hs_vclk & ~hs) de_h <= 1; - - old_de_vclk <= de; - if(calch & ~old_de_vclk & de) vid_de_h <= de_h; - - if(ce_pix) begin - old_vs <= vs; - old_hs <= hs; - old_de <= de; - old_de1 <= old_de; - pcnt <= 1; - - if(~vs & ~old_de & de) vcnt <= vcnt + 1; - if(calch & de) hcnt <= hcnt + 1; - if(old_de & ~de) calch <= 0; - if(~old_de1 & old_de) vid_pixrep <= pcnt; - if(old_hs & ~hs) de_v <= de_v + 1'd1; - if(calch & ~old_de & de) vid_de_v <= de_v; - - if(old_vs & ~vs) begin - vid_int <= {vid_int[0],f1}; - if(~f1) begin - if(hcnt && vcnt) begin - old_vmode <= new_vmode; - - //report new resolution after timeout - if(resto) resto <= resto + 1'd1; - if(vid_hcnt != hcnt || vid_vcnt != vcnt || old_vmode != new_vmode) resto <= 1; - if(&resto) vid_nres <= vid_nres + 1'd1; - vid_hcnt <= hcnt; - vid_vcnt <= vcnt; - vid_ccnt <= ccnt; - end - vcnt <= 0; - hcnt <= 0; - ccnt <= 0; - calch <= 1; - de_v <= 0; - end - end - end -end - -reg [31:0] vid_htime = 0; -reg [31:0] vid_vtime = 0; -reg [31:0] vid_pix = 0; - -always @(posedge clk_100) begin - integer vtime, htime, hcnt; - reg old_vs, old_hs, old_vs2, old_hs2, old_de, old_de2; - reg calch = 0; - - old_vs <= vs; - old_hs <= hs; - - old_vs2 <= old_vs; - old_hs2 <= old_hs; - - vtime <= vtime + 1'd1; - htime <= htime + 1'd1; - - if(~old_vs2 & old_vs) begin - vid_pix <= hcnt; - vid_vtime <= vtime; - vtime <= 0; - hcnt <= 0; - end - - if(old_vs2 & ~old_vs) calch <= 1; - - if(~old_hs2 & old_hs) begin - vid_htime <= htime; - htime <= 0; - end - - old_de <= de; - old_de2 <= old_de; - - if(calch & old_de) hcnt <= hcnt + 1; - if(old_de2 & ~old_de) calch <= 0; -end - -reg [31:0] vid_vtime_hdmi; -always @(posedge clk_100) begin - integer vtime; - reg old_vs, old_vs2; - - old_vs <= vs_hdmi; - old_vs2 <= old_vs; - - vtime <= vtime + 1'd1; - - if(~old_vs2 & old_vs) begin - vid_vtime_hdmi <= vtime; - vtime <= 0; - end -end - -endmodule - -module confstr_rom #(parameter CONF_STR, STRLEN) -( - input clk_sys, - input [$clog2(STRLEN+1)-1:0] conf_addr, - output reg [7:0] conf_byte -); - -wire [7:0] rom[STRLEN]; -initial for(int i = 0; i < STRLEN; i++) rom[i] = CONF_STR[((STRLEN-i)*8)-1 -:8]; -always @ (posedge clk_sys) conf_byte <= rom[conf_addr]; - -endmodule diff --git a/sys/hq2x.sv b/sys/hq2x.sv deleted file mode 100644 index f5fcc71..0000000 --- a/sys/hq2x.sv +++ /dev/null @@ -1,371 +0,0 @@ -// -// -// Copyright (c) 2012-2013 Ludvig Strigeus -// Copyright (c) 2017,2018 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -// altera message_off 10030 - -module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) -( - input clk, - - input ce_in, - input [DWIDTH:0] inputpixel, - input mono, - input disable_hq2x, - input reset_frame, - input reset_line, - - input ce_out, - input [1:0] read_y, - input hblank, - output [DWIDTH:0] outpixel -); - - -localparam AWIDTH = $clog2(LENGTH)-1; -localparam DWIDTH = HALF_DEPTH ? 11 : 23; -localparam DWIDTH1 = DWIDTH+1; - -(* romstyle = "MLAB" *) reg [5:0] hqTable[256]; -initial begin - hqTable = '{ - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 - }; -end - -wire [5:0] hqrule = hqTable[nextpatt]; - -reg [23:0] Prev0, Prev1, Prev2, Curr0, Curr1, Curr2, Next0, Next1, Next2; -reg [23:0] A, B, D, F, G, H; -reg [7:0] pattern, nextpatt; -reg [1:0] cyc; - -reg curbuf; -reg prevbuf = 0; -wire iobuf = !curbuf; - -wire diff0, diff1; -DiffCheck diffcheck0(Curr1, (cyc == 0) ? Prev0 : (cyc == 1) ? Curr0 : (cyc == 2) ? Prev2 : Next1, diff0); -DiffCheck diffcheck1(Curr1, (cyc == 0) ? Prev1 : (cyc == 1) ? Next0 : (cyc == 2) ? Curr2 : Next2, diff1); - -wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; - -wire [23:0] X = (cyc == 0) ? A : (cyc == 1) ? Prev1 : (cyc == 2) ? Next1 : G; -wire [23:0] blend_result_pre; -Blend blender(clk, ce_in, disable_hq2x ? 6'd0 : hqrule, Curr0, X, B, D, F, H, blend_result_pre); - -wire [DWIDTH:0] Curr20tmp; -wire [23:0] Curr20 = HALF_DEPTH ? h2rgb(Curr20tmp) : Curr20tmp; -wire [DWIDTH:0] Curr21tmp; -wire [23:0] Curr21 = HALF_DEPTH ? h2rgb(Curr21tmp) : Curr21tmp; - -reg [AWIDTH:0] wrin_addr2; -reg [DWIDTH:0] wrpix; -reg wrin_en; - -function [23:0] h2rgb; - input [11:0] v; -begin - h2rgb = mono ? {v[7:0], v[7:0], v[7:0]} : {v[11:8],v[11:8],v[7:4],v[7:4],v[3:0],v[3:0]}; -end -endfunction - -function [11:0] rgb2h; - input [23:0] v; -begin - rgb2h = mono ? {4'b0000, v[23:20], v[19:16]} : {v[23:20], v[15:12], v[7:4]}; -end -endfunction - -hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in -( - .clk(clk), - - .rdaddr(offs), - .rdbuf0(prevbuf), - .rdbuf1(curbuf), - .q0(Curr20tmp), - .q1(Curr21tmp), - - .wraddr(wrin_addr2), - .wrbuf(iobuf), - .data(wrpix), - .wren(wrin_en) -); - -reg [AWIDTH+1:0] read_x; -reg [AWIDTH+1:0] wrout_addr; -reg wrout_en; -reg [DWIDTH1*4-1:0] wrdata, wrdata_pre; -wire [DWIDTH1*4-1:0] outpixel_x4; -reg [DWIDTH1*2-1:0] outpixel_x2; - -assign outpixel = read_x[0] ? outpixel_x2[DWIDTH1*2-1:DWIDTH1] : outpixel_x2[DWIDTH:0]; - -hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH+1), .DWIDTH(DWIDTH1*4-1)) hq2x_out -( - .clock(clk), - - .rdaddress({read_x[AWIDTH+1:1],read_y[1]}), - .q(outpixel_x4), - - .data(wrdata), - .wraddress(wrout_addr), - .wren(wrout_en) -); - -always @(posedge clk) begin - if(ce_out) begin - if(read_x[0]) outpixel_x2 <= read_y[0] ? outpixel_x4[DWIDTH1*4-1:DWIDTH1*2] : outpixel_x4[DWIDTH1*2-1:0]; - if(~hblank & ~&read_x) read_x <= read_x + 1'd1; - if(hblank) read_x <= 0; - end -end - -wire [DWIDTH:0] blend_result = HALF_DEPTH ? rgb2h(blend_result_pre) : blend_result_pre[DWIDTH:0]; - -reg [AWIDTH:0] offs; -always @(posedge clk) begin - reg old_reset_line; - reg old_reset_frame; - reg [3:0] wrdata_finished; - reg [AWIDTH+1:0] waddr; - - wrout_en <= 0; - wrin_en <= 0; - - if(ce_in) begin - - // blend_result has been delayed by 4 cycles - case(cyc) - 0: wrdata[DWIDTH:0] <= blend_result; - 1: wrdata[DWIDTH1+DWIDTH:DWIDTH1] <= blend_result; - 2: wrdata[DWIDTH1*3+DWIDTH:DWIDTH1*3] <= blend_result; - 3: wrdata[DWIDTH1*2+DWIDTH:DWIDTH1*2] <= blend_result; - endcase - - wrdata_finished <= wrdata_finished << 1; - if(wrdata_finished[3]) begin - wrout_en <= 1; - wrout_addr <= waddr; - end - - if(~&offs) begin - if (cyc == 1) begin - Prev2 <= Curr20; - Curr2 <= Curr21; - Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; - wrpix <= inputpixel; - wrin_addr2 <= offs; - wrin_en <= 1; - end - - if(cyc==3) begin - offs <= offs + 1'd1; - waddr <= {offs, curbuf}; - wrdata_finished[0] <= 1; - end - end - - pattern <= new_pattern; - if(cyc==3) begin - nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; - {A, G} <= {Prev0, Next0}; - {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; - {Prev0, Prev1} <= {Prev1, Prev2}; - {Curr0, Curr1} <= {Curr1, Curr2}; - {Next0, Next1} <= {Next1, Next2}; - end else begin - nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; - {B, F, H, D} <= {F, H, D, B}; - end - - cyc <= cyc + 1'b1; - if(old_reset_line && ~reset_line) begin - old_reset_frame <= reset_frame; - offs <= 0; - cyc <= 0; - curbuf <= ~curbuf; - prevbuf <= curbuf; - {Prev0, Prev1, Prev2, Curr0, Curr1, Curr2, Next0, Next1, Next2} <= '0; - if(old_reset_frame & ~reset_frame) begin - curbuf <= 0; - prevbuf <= 0; - end - end - - old_reset_line <= reset_line; - end -end - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -module hq2x_in #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input rdbuf0, rdbuf1, - output[DWIDTH:0] q0,q1, - - input [AWIDTH:0] wraddr, - input wrbuf, - input [DWIDTH:0] data, - input wren -); - -localparam AWIDTH = $clog2(LENGTH)-1; -wire [DWIDTH:0] out[2]; -assign q0 = out[rdbuf0]; -assign q1 = out[rdbuf1]; - -hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); -hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); - -endmodule - -module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) -( - input clock, - input [DWIDTH:0] data, - input [AWIDTH:0] rdaddress, - input [AWIDTH:0] wraddress, - input wren, - output reg [DWIDTH:0] q -); - -reg [DWIDTH:0] ram[0:NUMWORDS-1]; - -always_ff@(posedge clock) begin - if(wren) ram[wraddress] <= data; - q <= ram[rdaddress]; -end - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -module DiffCheck -( - input [23:0] rgb1, - input [23:0] rgb2, - output result -); - - wire [7:0] r = rgb1[7:1] - rgb2[7:1]; - wire [7:0] g = rgb1[15:9] - rgb2[15:9]; - wire [7:0] b = rgb1[23:17] - rgb2[23:17]; - wire [8:0] t = $signed(r) + $signed(b); - wire [9:0] y = $signed(t) + $signed({g[7], g}); - wire [8:0] u = $signed(r) - $signed(b); - wire [9:0] v = $signed({g, 1'b0}) - $signed(t); - - // if y is inside (-96..96) - wire y_inside = (y < 10'h60 || y >= 10'h3a0); - - // if u is inside (-16, 16) - wire u_inside = (!u[8:4] || &u[8:4]); //(u < 9'h10 || u >= 9'h1f0); - - // if v is inside (-24, 24) - wire v_inside = (v < 10'h18 || v >= 10'h3e8); - assign result = !(y_inside && u_inside && v_inside); - -endmodule - -module Blend -( - input clk, - input clk_en, - input [5:0] rule, - input [23:0] E, - input [23:0] A, - input [23:0] B, - input [23:0] D, - input [23:0] F, - input [23:0] H, - output [23:0] Result -); - - localparam BLEND1 = 7'b110_10_00; // (A * 12 + B * 4 ) >> 4 - localparam BLEND2 = 7'b100_10_10; // (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 7'b101_10_01; // (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 7'b110_01_01; // (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 7'b010_11_11; // (A * 4 + B * 6 + C * 6) >> 4 - localparam BLEND6 = 7'b111_00_00; // (A * 14 + B * 1 + C * 1) >> 4 - - reg [23:0] a,b,d,e,h,f; - reg [3:0] bl_rule; - reg [1:0] df_rule; - always @(posedge clk) if (clk_en) begin - {bl_rule,df_rule} <= rule; - a <= A; b <= B; d <= D; e <= E; f <= F; h <= H; - end - - wire is_diff; - DiffCheck diff_checker(df_rule[1] ? b : h, df_rule[0] ? d : f, is_diff); - - reg [23:0] i10,i20,i30; - reg [6:0] op0; - always @(posedge clk) if (clk_en) begin - i10 <= e; - case({!is_diff, bl_rule}) - 1,11,12,13,17: {op0, i20, i30} <= {BLEND1, a, 24'd0}; - 2,14,18: {op0, i20, i30} <= {BLEND1, d, 24'd0}; - 3,15,19: {op0, i20, i30} <= {BLEND1, b, 24'd0}; - 4,20,24,27: {op0, i20, i30} <= {BLEND2, d, b}; - 5,21: {op0, i20, i30} <= {BLEND2, a, b}; - 6,22: {op0, i20, i30} <= {BLEND2, a, d}; - 25,29: {op0, i20, i30} <= {BLEND5, d, b}; - 26: {op0, i20, i30} <= {BLEND6, d, b}; - 28: {op0, i20, i30} <= {BLEND4, d, b}; - 30: {op0, i20, i30} <= {BLEND3, b, d}; - 31: {op0, i20, i30} <= {BLEND3, d, b}; - default: {op0, i20, i30} <= {BLEND1, e, 24'd0}; - endcase - end - - reg [23:0] i1,i2,i3; - reg [6:0] op; - always @(posedge clk) if (clk_en) begin - op <= op0; i1 <= i10; i2 <= i20; i3 <= i30; - end - - function [34:0] mul24x3; - input [23:0] op1; - input [2:0] op2; - begin - mul24x3 = 0; - if(op2[0]) mul24x3 = mul24x3 + {op1[23:16], 4'b0000, op1[15:8], 4'b0000, op1[7:0]}; - if(op2[1]) mul24x3 = mul24x3 + {op1[23:16], 4'b0000, op1[15:8], 4'b0000, op1[7:0], 1'b0}; - if(op2[2]) mul24x3 = mul24x3 + {op1[23:16], 4'b0000, op1[15:8], 4'b0000, op1[7:0], 2'b00}; - end - endfunction - - wire [35:0] res = {mul24x3(i1, op[6:4]), 1'b0} + mul24x3(i2, {op[3:2], !op[3:2]}) + mul24x3(i3, {op[1:0], !op[3:2]}); - - always @(posedge clk) if (clk_en) Result <= {res[35:28],res[23:16],res[11:4]}; - -endmodule diff --git a/sys/i2c.v b/sys/i2c.v deleted file mode 100644 index 9ccba93..0000000 --- a/sys/i2c.v +++ /dev/null @@ -1,103 +0,0 @@ - -module i2c -( - input CLK, - - input START, - input READ, - input [6:0] I2C_ADDR, - input I2C_WLEN, // 0 - one byte, 1 - two bytes - input [7:0] I2C_WDATA1, - input [7:0] I2C_WDATA2, - output [7:0] I2C_RDATA, - output reg END = 1, - output reg ACK = 0, - - //I2C bus - output I2C_SCL, - inout I2C_SDA -); - - -// Clock Setting -parameter CLK_Freq = 50_000_000; // 50 MHz -parameter I2C_Freq = 400_000; // 400 KHz - -localparam I2C_FreqX2 = I2C_Freq*2; - -reg I2C_CLOCK; -reg [31:0] cnt; -wire [31:0] cnt_next = cnt + I2C_FreqX2; - -always @(posedge CLK) begin - cnt <= cnt_next; - if(cnt_next >= CLK_Freq) begin - cnt <= cnt_next - CLK_Freq; - I2C_CLOCK <= ~I2C_CLOCK; - end -end - -assign I2C_SCL = (SCLK | I2C_CLOCK) ? 1'bZ : 1'b0; -assign I2C_SDA = SDO[3] ? 1'bz : 1'b0; - -reg SCLK; -reg [3:0] SDO; -reg [0:7] rdata; - -reg [5:0] SD_COUNTER; -reg [0:31] SD; - -initial begin - SD_COUNTER = 'b111111; - SD = 'hFFFF; - SCLK = 1; - SDO = 4'b1111; -end - -assign I2C_RDATA = rdata; - -always @(posedge CLK) begin - reg old_clk; - reg old_st; - reg rd,len; - - old_clk <= I2C_CLOCK; - old_st <= START; - - // delay to make sure SDA changed while SCL is stabilized at low - if(old_clk && ~I2C_CLOCK && ~SD_COUNTER[5]) SDO[0] <= SD[SD_COUNTER[4:0]]; - SDO[3:1] <= SDO[2:0]; - - if(~old_st && START) begin - SCLK <= 1; - SDO <= 4'b1111; - ACK <= 0; - END <= 0; - rd <= READ; - len <= I2C_WLEN; - if(READ) SD <= {2'b10, I2C_ADDR, 1'b1, 1'b1, 8'b11111111, 1'b0, 3'b011, 9'b111111111}; - else SD <= {2'b10, I2C_ADDR, 1'b0, 1'b1, I2C_WDATA1, 1'b1, I2C_WDATA2, 4'b1011}; - SD_COUNTER <= 0; - end else begin - if(~old_clk && I2C_CLOCK && ~&SD_COUNTER) begin - SD_COUNTER <= SD_COUNTER + 6'd1; - case(SD_COUNTER) - 01: SCLK <= 0; - 10: ACK <= ACK | I2C_SDA; - 19: if(~rd) begin - ACK <= ACK | I2C_SDA; - if(~len) SD_COUNTER <= 29; - end - 20: if(rd) SCLK <= 1; - 23: if(rd) END <= 1; - 28: if(~rd) ACK <= ACK | I2C_SDA; - 29: if(~rd) SCLK <= 1; - 32: if(~rd) END <= 1; - endcase - - if(SD_COUNTER >= 11 && SD_COUNTER <= 18) rdata[SD_COUNTER[4:0]-11] <= I2C_SDA; - end - end -end - -endmodule diff --git a/sys/i2s.v b/sys/i2s.v deleted file mode 100644 index 7d4517b..0000000 --- a/sys/i2s.v +++ /dev/null @@ -1,54 +0,0 @@ - -module i2s -#( - parameter AUDIO_DW = 16 -) -( - input reset, - input clk, - input ce, - - output reg sclk, - output reg lrclk, - output reg sdata, - - input [AUDIO_DW-1:0] left_chan, - input [AUDIO_DW-1:0] right_chan -); - -always @(posedge clk) begin - reg [7:0] bit_cnt; - reg msclk; - - reg [AUDIO_DW-1:0] left; - reg [AUDIO_DW-1:0] right; - - if (reset) begin - bit_cnt <= 1; - lrclk <= 1; - sclk <= 1; - msclk <= 1; - end - else begin - sclk <= msclk; - if(ce) begin - msclk <= ~msclk; - if(msclk) begin - if(bit_cnt >= AUDIO_DW) begin - bit_cnt <= 1; - lrclk <= ~lrclk; - if(lrclk) begin - left <= left_chan; - right <= right_chan; - end - end - else begin - bit_cnt <= bit_cnt + 1'd1; - end - sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt]; - end - end - end -end - -endmodule diff --git a/sys/iir_filter.v b/sys/iir_filter.v deleted file mode 100644 index b8bcf4f..0000000 --- a/sys/iir_filter.v +++ /dev/null @@ -1,213 +0,0 @@ - -// 3-tap IIR filter for 2 channels. -// Copyright (C) 2020 Sorgelig -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - -// -// Can be converted to 2-tap (coeff_x2 = 0, coeff_y2 = 0) or 1-tap (coeff_x1,2 = 0, coeff_y1,2 = 0) -// -module IIR_filter -#( - parameter use_params = 1, // set to 1 to use following parameters, 0 for input port variables. - parameter stereo = 1, // 0 for mono (input_l) - - parameter coeff_x = 0.00000774701983513660, // Base gain value for X. Float. Range: 0.0 ... 0.999(9) - parameter coeff_x0 = 3, // Gain scale factor for X0. Integer. Range -7 ... +7 - parameter coeff_x1 = 3, // Gain scale factor for X1. Integer. Range -7 ... +7 - parameter coeff_x2 = 1, // Gain scale factor for X2. Integer. Range -7 ... +7 - parameter coeff_y0 = -2.96438150626551080000, // Coefficient for Y0. Float. Range -3.999(9) ... 3.999(9) - parameter coeff_y1 = 2.92939452735121100000, // Coefficient for Y1. Float. Range -3.999(9) ... 3.999(9) - parameter coeff_y2 = -0.96500747158831091000 // Coefficient for Y2. Float. Range -3.999(9) ... 3.999(9) -) -( - input clk, - input reset, - - input ce, // must be double of calculated rate for stereo! - input sample_ce, // desired output sample rate - - input [39:0] cx, - input [7:0] cx0, - input [7:0] cx1, - input [7:0] cx2, - input [23:0] cy0, - input [23:0] cy1, - input [23:0] cy2, - - input [15:0] input_l, input_r, // signed samples - output [15:0] output_l, output_r // signed samples -); - -localparam [39:0] pcoeff_x = coeff_x * 40'h8000000000; -localparam [31:0] pcoeff_y0 = coeff_y0 * 24'h200000; -localparam [31:0] pcoeff_y1 = coeff_y1 * 24'h200000; -localparam [31:0] pcoeff_y2 = coeff_y2 * 24'h200000; - -wire [39:0] vcoeff = use_params ? pcoeff_x : cx; -wire [23:0] vcoeff_y0 = use_params ? pcoeff_y0[23:0] : cy0; -wire [23:0] vcoeff_y1 = use_params ? pcoeff_y1[23:0] : cy1; -wire [23:0] vcoeff_y2 = use_params ? pcoeff_y2[23:0] : cy2; - -wire [59:0] inp_mul = $signed(inp) * $signed(vcoeff); - -wire [39:0] x = inp_mul[59:20]; -wire [39:0] y = x + tap0; - -wire [39:0] tap0; -iir_filter_tap iir_tap_0 -( - .clk(clk), - .reset(reset), - .ce(ce), - .ch(ch), - .cx(use_params ? coeff_x0[7:0] : cx0), - .cy(vcoeff_y0), - .x(x), - .y(y), - .z(tap1), - .tap(tap0) -); - -wire [39:0] tap1; -iir_filter_tap iir_tap_1 -( - .clk(clk), - .reset(reset), - .ce(ce), - .ch(ch), - .cx(use_params ? coeff_x1[7:0] : cx1), - .cy(vcoeff_y1), - .x(x), - .y(y), - .z(tap2), - .tap(tap1) -); - -wire [39:0] tap2; -iir_filter_tap iir_tap_2 -( - .clk(clk), - .reset(reset), - .ce(ce), - .ch(ch), - .cx(use_params ? coeff_x2[7:0] : cx2), - .cy(vcoeff_y2), - .x(x), - .y(y), - .z(0), - .tap(tap2) -); - -wire [15:0] y_clamp = (~y[39] & |y[38:35]) ? 16'h7FFF : (y[39] & ~&y[38:35]) ? 16'h8000 : y[35:20]; - -reg ch = 0; -reg [15:0] out_l, out_r, out_m; -reg [15:0] inp, inp_m; -always @(posedge clk) if (ce) begin - if(!stereo) begin - ch <= 0; - inp <= input_l; - out_l <= y_clamp; - out_r <= y_clamp; - end - else begin - ch <= ~ch; - if(ch) begin - out_m <= y_clamp; - inp <= inp_m; - end - else begin - out_l <= out_m; - out_r <= y_clamp; - inp <= input_l; - inp_m <= input_r; - end - end -end - -reg [31:0] out; -always @(posedge clk) if (sample_ce) out <= {out_l, out_r}; - -assign {output_l, output_r} = out; - -endmodule - -module iir_filter_tap -( - input clk, - input reset, - - input ce, - input ch, - - input [7:0] cx, - input [23:0] cy, - - input [39:0] x, - input [39:0] y, - input [39:0] z, - output [39:0] tap -); - -wire signed [60:0] y_mul = $signed(y[36:0]) * $signed(cy); - -function [39:0] x_mul; - input [39:0] x; -begin - x_mul = 0; - if(cx[0]) x_mul = x_mul + {{4{x[39]}}, x[39:4]}; - if(cx[1]) x_mul = x_mul + {{3{x[39]}}, x[39:3]}; - if(cx[2]) x_mul = x_mul + {{2{x[39]}}, x[39:2]}; - if(cx[7]) x_mul = ~x_mul; //cheap NEG -end -endfunction - -(* ramstyle = "logic" *) reg [39:0] intreg[2]; -always @(posedge clk, posedge reset) begin - if(reset) {intreg[0],intreg[1]} <= 80'd0; - else if(ce) intreg[ch] <= x_mul(x) - y_mul[60:21] + z; -end - -assign tap = intreg[ch]; - -endmodule - -// simplified IIR 1-tap. -module DC_blocker -( - input clk, - input ce, // 48/96 KHz - input mute, - - input sample_rate, - input [15:0] din, - output [15:0] dout -); - -wire [39:0] x = {din[15], din, 23'd0}; -wire [39:0] x0 = x - (sample_rate ? {{11{x[39]}}, x[39:11]} : {{10{x[39]}}, x[39:10]}); -wire [39:0] y1 = y - (sample_rate ? {{10{y[39]}}, y[39:10]} : {{09{y[39]}}, y[39:09]}); -wire [39:0] y0 = x0 - x1 + y1; - -reg [39:0] x1, y; -always @(posedge clk) if(ce) begin - x1 <= x0; - y <= ^y0[39:38] ? {{2{y0[39]}},{38{y0[38]}}} : y0; -end - -assign dout = mute ? 16'd0 : y[38:23]; - -endmodule diff --git a/sys/ltc2308.sv b/sys/ltc2308.sv deleted file mode 100644 index 4d3ccc1..0000000 --- a/sys/ltc2308.sv +++ /dev/null @@ -1,162 +0,0 @@ -//============================================================================ -// -// LTC2308 controller -// Copyright (C) 2019 Sorgelig -// -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -// -//============================================================================ - - -// NUM_CH 1..8 -// Sampling rate = ADC_RATE/NUM_CH -// ADC_RATE max is ~500KHz -// CLK_RATE max is ~80MHz -module ltc2308 #(parameter NUM_CH = 2, ADC_RATE = 96000, CLK_RATE = 50000000) -( - input reset, - input clk, - - inout [3:0] ADC_BUS, - - output reg dout_sync, // toggle with every ADC round - output reg [(NUM_CH*12)-1:0] dout // 12 bits per channel (unsigned) -); - -localparam TCONV = CLK_RATE/625000; - -reg sck; -wire sdo = cfg[5]; - -assign ADC_BUS[3] = sck; -wire sdi = ADC_BUS[2]; -assign ADC_BUS[1] = sdo; -assign ADC_BUS[0] = convst; - -reg convst; -reg [5:0] cfg; - -reg [31:0] sum; -wire [31:0] next_sum = sum + ADC_RATE; - -reg [2:0] pin; -wire [2:0] next_pin = (pin == (NUM_CH-1)) ? 3'd0 : (pin + 1'd1); - -always @(posedge clk) begin - reg [7:0] tconv; - reg [3:0] bitcnt; - reg [10:0] adcin; - - convst <= 0; - - if(reset) begin - sum <= 0; - tconv <= 0; - bitcnt <= 0; - sck <= 0; - cfg <= 0; - dout <= 0; - pin <= NUM_CH[2:0]-1'd1; - end - else begin - sum <= next_sum; - if(next_sum >= CLK_RATE) begin - sum <= next_sum - CLK_RATE; - tconv <= TCONV[7:0]; - convst <= 1; - bitcnt <= 12; - cfg <= {1'b1, next_pin[0], next_pin[2:1], 1'b1, 1'b0}; - if(!next_pin) dout_sync <= ~dout_sync; - end - - if(tconv) tconv <= tconv - 1'd1; - else if(bitcnt) begin - sck <= ~sck; - - if(sck) cfg <= cfg<<1; - else begin - adcin <= {adcin[9:0],sdi}; - bitcnt <= bitcnt - 1'd1; - if(bitcnt == 1) begin - dout[pin*12 +:12] <= {adcin,sdi}; - pin <= next_pin; - end - end - end - else sck <= 0; - end -end - -endmodule - -module ltc2308_tape #(parameter HIST_LOW = 16, HIST_HIGH = 64, ADC_RATE = 48000, CLK_RATE = 50000000, NUM_CH = 1) -( - input reset, - input clk, - - inout [3:0] ADC_BUS, - output reg dout, - output active, - output adc_sync, - output [(NUM_CH*12)-1:0] adc_data -); - -ltc2308 #(NUM_CH, ADC_RATE, CLK_RATE) adc -( - .reset(reset), - .clk(clk), - - .ADC_BUS(ADC_BUS), - .dout(adc_data), - .dout_sync(adc_sync) -); - -always @(posedge clk) begin - reg [13:0] data1,data2,data3,data4, sum; - reg adc_sync_d; - - adc_sync_d<=adc_sync; - if(adc_sync_d ^ adc_sync) begin - data1 <= data2; - data2 <= data3; - data3 <= data4; - data4 <= adc_data[11:0]; - - sum <= data1+data2+data3+data4; - - if(sum[13:2]HIST_HIGH) dout <= 1; - end -end - -assign active = |act; - -reg [1:0] act; -always @(posedge clk) begin - reg [31:0] onesec; - reg old_dout; - - onesec <= onesec + 1; - if(onesec>CLK_RATE) begin - onesec <= 0; - if(act) act <= act - 1'd1; - end - - old_dout <= dout; - if(old_dout ^ dout) act <= 2; -end - -endmodule diff --git a/sys/math.sv b/sys/math.sv deleted file mode 100644 index e7c0144..0000000 --- a/sys/math.sv +++ /dev/null @@ -1,109 +0,0 @@ - -// result = num/div -module sys_udiv -#( - parameter NB_NUM, - parameter NB_DIV -) -( - input clk, - input start, - output busy, - - input [NB_NUM-1:0] num, - input [NB_DIV-1:0] div, - output reg [NB_NUM-1:0] result, - output reg [NB_DIV-1:0] remainder -); - -reg run; -assign busy = run; - -always @(posedge clk) begin - reg [5:0] cpt; - reg [NB_NUM+NB_DIV+1:0] rem; - - if (start) begin - cpt <= 0; - run <= 1; - rem <= num; - end - else if (run) begin - cpt <= cpt + 1'd1; - run <= (cpt != NB_NUM + 1'd1); - remainder <= rem[NB_NUM+NB_DIV:NB_NUM+1]; - if (!rem[NB_DIV + NB_NUM + 1'd1]) - rem <= {rem[NB_DIV+NB_NUM:0] - (div << NB_NUM),1'b0}; - else - rem <= {rem[NB_DIV+NB_NUM:0] + (div << NB_NUM),1'b0}; - result <= {result[NB_NUM-2:0], !rem[NB_DIV + NB_NUM + 1'd1]}; - end -end - -endmodule - -// result = mul1*mul2 -module sys_umul -#( - parameter NB_MUL1, - parameter NB_MUL2 -) -( - input clk, - input start, - output busy, - - input [NB_MUL1-1:0] mul1, - input [NB_MUL2-1:0] mul2, - output reg [NB_MUL1+NB_MUL2-1:0] result -); - -reg run; -assign busy = run; - -always @(posedge clk) begin - reg [NB_MUL1+NB_MUL2-1:0] add; - reg [NB_MUL2-1:0] map; - - if (start) begin - run <= 1; - result <= 0; - add <= mul1; - map <= mul2; - end - else if (run) begin - if(!map) run <= 0; - if(map[0]) result <= result + add; - add <= add << 1; - map <= map >> 1; - end -end - -endmodule - -// result = (mul1*mul2)/div -module sys_umuldiv -#( - parameter NB_MUL1, - parameter NB_MUL2, - parameter NB_DIV -) -( - input clk, - input start, - output busy, - - input [NB_MUL1-1:0] mul1, - input [NB_MUL2-1:0] mul2, - input [NB_DIV-1:0] div, - output [NB_MUL1+NB_MUL2-1:0] result, - output [NB_DIV-1:0] remainder -); - -wire mul_run; -wire [NB_MUL1+NB_MUL2-1:0] mul_res; -sys_umul #(NB_MUL1,NB_MUL2) umul(clk,start,mul_run,mul1,mul2,mul_res); - -sys_udiv #(NB_MUL1+NB_MUL2,NB_DIV) udiv(clk,start|mul_run,busy,mul_res,div,result,remainder); - -endmodule diff --git a/sys/mcp23009.sv b/sys/mcp23009.sv deleted file mode 100644 index 82eaf37..0000000 --- a/sys/mcp23009.sv +++ /dev/null @@ -1,120 +0,0 @@ -// -// MCP23009 -// (C) 2019 Alexey Melnikov -// -module mcp23009 -( - input clk, - - output reg [2:0] btn, - input [2:0] led, - output reg flg_sd_cd, - output reg flg_present, - output reg flg_mode, - - output scl, - inout sda -); - - -reg start = 0; -wire ready; -wire error; -reg rw; -wire [7:0] dout; -reg [15:0] din; - -i2c #(50_000_000, 500_000) i2c -( - .CLK(clk), - .START(start), - .READ(rw), - .I2C_ADDR('h20), - .I2C_WLEN(1), - .I2C_WDATA1(din[15:8]), - .I2C_WDATA2(din[7:0]), - .I2C_RDATA(dout), - .END(ready), - .ACK(error), - .I2C_SCL(scl), - .I2C_SDA(sda) -); - -always@(posedge clk) begin - reg [3:0] idx = 0; - reg [1:0] state = 0; - reg [15:0] timeout = 0; - - if(~&timeout) begin - timeout <= timeout + 1'd1; - start <= 0; - state <= 0; - idx <= 0; - btn <= 0; - rw <= 0; - flg_sd_cd <= 1; - flg_present <= 0; - flg_mode <= 1; - end - else begin - if(~&init_data[idx]) begin - case(state) - 0: begin - start <= 1; - state <= 1; - din <= init_data[idx]; - end - 1: if(~ready) state <= 2; - 2: begin - start <= 0; - if(ready) begin - state <= 0; - if(!error) idx <= idx + 1'd1; - end - end - endcase - end - else begin - case(state) - 0: begin - start <= 1; - state <= 1; - din <= {8'h09,5'b00000,led}; - end - 1: if(~ready) state <= 2; - 2: begin - start <= 0; - if(ready) begin - state <= 0; - rw <= 0; - if(!error) begin - if(rw) begin - {flg_sd_cd, flg_mode, btn} <= {dout[7:3]}; - flg_present <= 1; - end - rw <= ~rw; - end - end - end - endcase - end - end -end - -wire [15:0] init_data[12] = -'{ - 16'h00F8, - 16'h0138, - 16'h0200, - 16'h0300, - 16'h0400, - 16'h0524, - 16'h06FF, - 16'h0700, - 16'h0800, - 16'h0900, - 16'h0A00, - 16'hFFFF -}; - -endmodule diff --git a/sys/mt32pi.sv b/sys/mt32pi.sv deleted file mode 100644 index 6704807..0000000 --- a/sys/mt32pi.sv +++ /dev/null @@ -1,283 +0,0 @@ -// -// Communication module to MT32-pi (external MIDI emulator on RPi) -// (C) 2020 Sorgelig, Kitrinx -// -// https://github.com/dwhinham/mt32-pi -// - -module mt32pi -( - input CLK_AUDIO, - - input CLK_VIDEO, - input CE_PIXEL, - input VGA_VS, - input VGA_DE, - - input [6:0] USER_IN, - output [6:0] USER_OUT, - - input reset, - input midi_tx, - output midi_rx, - - output reg [15:0] mt32_i2s_r, - output reg [15:0] mt32_i2s_l, - - output reg mt32_available, - - input mt32_mode_req, - input [1:0] mt32_rom_req, - input [7:0] mt32_sf_req, - - output reg [7:0] mt32_mode, - output reg [7:0] mt32_rom, - output reg [7:0] mt32_sf, - output reg mt32_newmode, - - output reg mt32_lcd_en, - output reg mt32_lcd_pix, - output reg mt32_lcd_update -); - -// -// Pin | USB Name | Signal -// ----+----------+-------------- -// 0 | D+ | I/O I2C_SDA / RX (midi in) -// 1 | D- | O TX (midi out) -// 2 | TX- | I I2S_WS (1 == right) -// 3 | GND_d | I I2C_SCL -// 4 | RX+ | I I2S_BCLK -// 5 | RX- | I I2S_DAT -// 6 | TX+ | - none -// - -assign USER_OUT[0] = sda_out; -assign USER_OUT[1] = midi_tx; -assign USER_OUT[6:2] = '1; - - -// -// crossed/straight cable selection -// - -generate - genvar i; - for(i = 0; i<2; i++) begin : clk_rate - wire clk_in = i ? USER_IN[6] : USER_IN[4]; - reg [4:0] cnt; - always @(posedge CLK_AUDIO) begin : clkr - reg clk_sr, clk, old_clk; - reg [4:0] cnt_tmp; - - clk_sr <= clk_in; - if (clk_sr == clk_in) clk <= clk_sr; - - if(~&cnt_tmp) cnt_tmp <= cnt_tmp + 1'd1; - else cnt <= '1; - - old_clk <= clk; - if(~old_clk & clk) begin - cnt <= cnt_tmp; - cnt_tmp <= 0; - end - end - end - - reg crossed; - always @(posedge CLK_AUDIO) crossed <= (clk_rate[0].cnt <= clk_rate[1].cnt); -endgenerate - -wire i2s_ws = crossed ? USER_IN[2] : USER_IN[5]; -wire i2s_data = crossed ? USER_IN[5] : USER_IN[2]; -wire i2s_bclk = crossed ? USER_IN[4] : USER_IN[6]; -assign midi_rx = ~mt32_available ? USER_IN[0] : crossed ? USER_IN[6] : USER_IN[4]; - - -// -// i2s receiver -// - -always @(posedge CLK_AUDIO) begin : i2s_proc - reg [15:0] i2s_buf = 0; - reg [4:0] i2s_cnt = 0; - reg clk_sr; - reg i2s_clk = 0; - reg old_clk, old_ws; - reg i2s_next = 0; - - // Debounce clock - clk_sr <= i2s_bclk; - if (clk_sr == i2s_bclk) i2s_clk <= clk_sr; - - // Latch data and ws on rising edge - old_clk <= i2s_clk; - if (i2s_clk && ~old_clk) begin - - if (~i2s_cnt[4]) begin - i2s_cnt <= i2s_cnt + 1'd1; - i2s_buf[~i2s_cnt[3:0]] <= i2s_data; - end - - // Word Select will change 1 clock before the new word starts - old_ws <= i2s_ws; - if (old_ws != i2s_ws) i2s_next <= 1; - end - - if (i2s_next) begin - i2s_next <= 0; - i2s_cnt <= 0; - i2s_buf <= 0; - - if (i2s_ws) mt32_i2s_l <= i2s_buf; - else mt32_i2s_r <= i2s_buf; - end - - if (reset) begin - i2s_buf <= 0; - mt32_i2s_l <= 0; - mt32_i2s_r <= 0; - end -end - - -// -// i2c slave -// - -reg sda_out; -reg [7:0] lcd_data[1024]; -reg lcd_sz; - -reg reset_r = 0; -wire [7:0] mode_req = reset_r ? 8'hA0 : mt32_mode_req ? 8'hA2 : 8'hA1; -wire [7:0] rom_req = {6'd0, mt32_rom_req}; - -always @(posedge CLK_AUDIO) begin : i2c_slave - reg sda_sr, scl_sr; - reg old_sda, old_scl; - reg sda, scl; - reg [7:0] tmp; - reg [3:0] cnt = 0; - reg [10:0] bcnt = 0; - reg ack; - reg i2c_rw; - reg disp, dispdata; - reg [2:0] div; - reg old_reset; - - old_reset <= reset; - if(old_reset & ~reset) sda_out <= 1; - - div <= div + 1'd1; - if(!div) begin - sda_sr <= USER_IN[0]; - if(sda_sr == USER_IN[0]) sda <= sda_sr; - old_sda <= sda; - - scl_sr <= USER_IN[3]; - if(scl_sr == USER_IN[3]) scl <= scl_sr; - old_scl <= scl; - - //start - if(old_scl & scl & old_sda & ~sda) begin - cnt <= 9; - bcnt <= 0; - ack <= 0; - i2c_rw <= 0; - disp <= 0; - dispdata <= 0; - end - - //stop - if(old_scl & scl & ~old_sda & sda) begin - cnt <= 0; - if(dispdata) begin - lcd_sz <= ~bcnt[9]; - mt32_lcd_update <= ~mt32_lcd_update; - end - end - - //data latch - if(~old_scl && scl && cnt) begin - tmp <= {tmp[6:0], sda}; - cnt <= cnt - 1'd1; - end - - if(!cnt) sda_out <= 1; - - //data set - if(old_scl && ~scl) begin - sda_out <= 1; - if(cnt == 1) begin - if(!bcnt) begin - if(tmp[7:1] == 'h45 || tmp[7:1] == 'h3c) begin - disp <= (tmp[7:1] == 'h3c); - sda_out <= 0; - mt32_available <= 1; - ack <= 1; - i2c_rw <= tmp[0]; - bcnt <= bcnt + 1'd1; - cnt <= 10; - end - else begin - // wrong address, stop - cnt <= 0; - end - end - else if(ack) begin - if(~i2c_rw) begin - if(disp) begin - if(bcnt == 1) dispdata <= (tmp[7:6] == 2'b01); - else if(dispdata) lcd_data[bcnt[9:0] - 2'd2] <= tmp; - end - else begin - if(bcnt == 1) mt32_mode <= tmp; - if(bcnt == 2) mt32_rom <= tmp; - if(bcnt == 3) mt32_sf <= tmp; - if(bcnt == 3) mt32_newmode <= ~mt32_newmode; - end - end - if(~&bcnt) bcnt <= bcnt + 1'd1; - sda_out <= 0; - cnt <= 10; - end - end - else if(i2c_rw && ack && cnt && ~disp) begin - if(bcnt == 1) sda_out <= mode_req[cnt[2:0] - 2'd2]; - if(bcnt == 2) sda_out <= rom_req[cnt[2:0] - 2'd2]; - if(bcnt == 3) sda_out <= mt32_sf_req[cnt[2:0] - 2'd2]; - if(bcnt == 3) reset_r <= 0; - end - end - end - - if(reset) begin - reset_r <= 1; - mt32_available <= 0; - end -end - -always @(posedge CLK_VIDEO) begin - reg old_de, old_vs; - reg [7:0] hcnt; - reg [6:0] vcnt; - reg [7:0] sh; - - if(CE_PIXEL) begin - old_de <= VGA_DE; - old_vs <= VGA_VS; - - if(~&hcnt) hcnt <= hcnt + 1'd1; - sh <= (sh << 1) | (~old_de & VGA_DE); - if(sh[7]) hcnt <= 0; - - if(old_de & ~VGA_DE & ~&vcnt) vcnt <= vcnt + 1'd1; - if(~old_vs & VGA_VS) vcnt <= 0; - - mt32_lcd_en <= mt32_available & ~hcnt[7] && (lcd_sz ? !vcnt[6] : !vcnt[6:5]); - mt32_lcd_pix <= lcd_data[{vcnt[5:3],hcnt[6:0]}][vcnt[2:0]]; - end -end - -endmodule diff --git a/sys/osd.v b/sys/osd.v deleted file mode 100644 index c354f6f..0000000 --- a/sys/osd.v +++ /dev/null @@ -1,286 +0,0 @@ -// A simple OSD implementation. Can be hooked up between a cores -// VGA output and the physical VGA pins - -module osd -( - input clk_sys, - input io_osd, - input io_strobe, - input [15:0] io_din, - - input clk_video, - input [23:0] din, - input de_in, - input vs_in, - input hs_in, - output [23:0] dout, - output reg de_out, - output reg vs_out, - output reg hs_out, - - output reg osd_status -); - -parameter OSD_COLOR = 3'd4; - -localparam OSD_WIDTH = 12'd256; -localparam OSD_HEIGHT = 12'd64; - -`ifdef OSD_HEADER -localparam OSD_HDR = 12'd24; -`else -localparam OSD_HDR = 12'd0; -`endif - -reg osd_enable; -(* ramstyle="no_rw_check" *) reg [7:0] osd_buffer[OSD_HDR ? (4096+1024) : 4096]; - -reg info = 0; -reg [8:0] infoh; -reg [8:0] infow; -reg [21:0] infox; -reg [21:0] infoy; -reg [21:0] osd_h; -reg [21:0] osd_t; -reg [21:0] osd_w; - -reg [1:0] rot = 0; - -always@(posedge clk_sys) begin - reg [12:0] bcnt; - reg [7:0] cmd; - reg has_cmd; - reg old_strobe; - reg highres = 0; - - osd_t <= rot[0] ? OSD_WIDTH : (OSD_HEIGHT<<1); - osd_h <= rot[0] ? (info ? infow : OSD_WIDTH) : info ? infoh : (OSD_HEIGHT<> (9-rot[0])) > 1) ? (((cnt+1'b1) >> (9-rot[0])) - 1'd1) : 22'd0; - pixcnt <= 0; - end -end - -reg [2:0] osd_de; -reg osd_pixel; -reg [21:0] v_cnt; -reg v_cnt_h, v_cnt_1, v_cnt_2, v_cnt_3, v_cnt_4; -reg [21:0] v_osd_start_h, v_osd_start_1, v_osd_start_2, v_osd_start_3, v_osd_start_4, v_osd_start_5; -reg [21:0] v_info_start_h, v_info_start_1, v_info_start_2, v_info_start_3, v_info_start_4, v_info_start_5; - -wire [21:0] osd_h_hdr = (info || rot) ? osd_h : (osd_h + OSD_HDR); - -// pipeline the comparisons a bit -always @(posedge clk_video) if(ce_pix) begin - v_cnt_h <= v_cnt <= osd_t; - v_cnt_1 <= v_cnt < 320; - v_cnt_2 <= v_cnt < 640; - v_cnt_3 <= v_cnt < 960; - v_cnt_4 <= v_cnt < 1280; - - v_osd_start_h <= (v_cnt-(osd_h_hdr>>1))>>1; - v_osd_start_1 <= (v_cnt-osd_h_hdr)>>1; - v_osd_start_2 <= (v_cnt-(osd_h_hdr<<1))>>1; - v_osd_start_3 <= (v_cnt-(osd_h_hdr + (osd_h_hdr<<1)))>>1; - v_osd_start_4 <= (v_cnt-(osd_h_hdr<<2))>>1; - v_osd_start_5 <= (v_cnt-(osd_h_hdr + (osd_h_hdr<<2)))>>1; - - v_info_start_h <= rot[0] ? infox : infoy; - v_info_start_1 <= rot[0] ? infox : infoy; - v_info_start_2 <= rot[0] ? (infox<<1) : (infoy<<1); - v_info_start_3 <= rot[0] ? (infox + (infox << 1)) : (infoy + (infoy << 1)); - v_info_start_4 <= rot[0] ? (infox << 2) : (infoy << 2); - v_info_start_5 <= rot[0] ? (infox + (infox << 2)) : (infoy + (infoy << 2)); -end - -always @(posedge clk_video) begin - reg deD; - reg [2:0] osd_div; - reg [2:0] multiscan; - reg [7:0] osd_byte; - reg [23:0] h_cnt; - reg [21:0] dsp_width; - reg [21:0] osd_vcnt; - reg [21:0] h_osd_start; - reg [21:0] v_osd_start; - reg [21:0] osd_hcnt; - reg [21:0] osd_hcnt2; - reg osd_de1,osd_de2; - reg [1:0] osd_en; - reg f1; - reg half; - - if(ce_pix) begin - - deD <= de_in; - if(~&h_cnt) h_cnt <= h_cnt + 1'd1; - - if(~&osd_hcnt) osd_hcnt <= osd_hcnt + 1'd1; - if(~&osd_hcnt2) osd_hcnt2 <= osd_hcnt2 + 1'd1; - - if (h_cnt == h_osd_start) begin - osd_de[0] <= osd_en[1] && osd_h && ( - osd_vcnt[11] ? (osd_vcnt[7] && (osd_vcnt[6:0] >= 4) && (osd_vcnt[6:0] < 19)) : - (info && (rot == 3)) ? !osd_vcnt[21:8] : - (osd_vcnt < osd_h) - ); - osd_hcnt <= 0; - osd_hcnt2 <= 0; - if(info && rot == 1) osd_hcnt2 <= 22'd128-infoh; - end - if (osd_hcnt+1 == osd_w) osd_de[0] <= 0; - - // falling edge of de - if(!de_in && deD) dsp_width <= h_cnt[21:0]; - - // rising edge of de - if(de_in && !deD) begin - h_cnt <= 0; - v_cnt <= v_cnt + 1'd1; - h_osd_start <= info ? (rot[0] ? infoy : infox) : (((dsp_width - osd_w)>>1) - 2'd2); - - if(h_cnt > {dsp_width, 2'b00}) begin - v_cnt <= 1; - f1 <= ~f1; // skip every other frame for interlace compatibility. - if(~f1) begin - - osd_en <= (osd_en << 1) | osd_enable; - if(~osd_enable) osd_en <= 0; - - half <= 0; - if(v_cnt_h) begin - multiscan <= 0; - v_osd_start <= info ? v_info_start_h : v_osd_start_h; - half <= 1; - end - else if(v_cnt_1 | (rot[0] & v_cnt_2)) begin - multiscan <= 0; - v_osd_start <= info ? v_info_start_1 : v_osd_start_1; - end - else if(rot[0] ? v_cnt_3 : v_cnt_2) begin - multiscan <= 1; - v_osd_start <= info ? v_info_start_2 : v_osd_start_2; - end - else if(rot[0] ? v_cnt_4 : v_cnt_3) begin - multiscan <= 2; - v_osd_start <= info ? v_info_start_3 : v_osd_start_3; - end - else if(rot[0] | v_cnt_4) begin - multiscan <= 3; - v_osd_start <= info ? v_info_start_4 : v_osd_start_4; - end - else begin - multiscan <= 4; - v_osd_start <= info ? v_info_start_5 : v_osd_start_5; - end - end - end - - osd_div <= osd_div + 1'd1; - if(osd_div == multiscan) begin - osd_div <= 0; - if(~osd_vcnt[10]) osd_vcnt <= osd_vcnt + 1'd1 + half; - if(osd_vcnt == 'b100010011111 && ~info) osd_vcnt <= 0; - end - if(v_osd_start == v_cnt) begin - {osd_div,osd_vcnt} <= 0; - if(info && rot == 3) osd_vcnt <= 22'd256-infow; - else if(OSD_HDR && !rot) osd_vcnt <= {~info, 3'b000, ~info, 7'b0000000}; - end - end - - osd_byte <= osd_buffer[rot[0] ? ({osd_hcnt2[6:3], osd_vcnt[7:0]} ^ { {4{~rot[1]}}, {8{rot[1]}} }) : {osd_vcnt[7:3], osd_hcnt[7:0]}]; - osd_pixel <= osd_byte[rot[0] ? ((osd_hcnt2[2:0]-1'd1) ^ {3{~rot[1]}}) : osd_vcnt[2:0]]; - osd_de[2:1] <= osd_de[1:0]; - end -end - -reg [23:0] rdout; -assign dout = rdout; - -always @(posedge clk_video) begin - reg [23:0] ordout1, nrdout1, rdout2, rdout3; - reg de1,de2,de3; - reg osd_mux; - reg vs1,vs2,vs3; - reg hs1,hs2,hs3; - - nrdout1 <= din; - ordout1 <= {{osd_pixel, osd_pixel, OSD_COLOR[2], din[23:19]},// 23:16 - {osd_pixel, osd_pixel, OSD_COLOR[1], din[15:11]},// 15:8 - {osd_pixel, osd_pixel, OSD_COLOR[0], din[7:3]}}; // 7:0 - - osd_mux <= ~osd_de[2]; - rdout2 <= osd_mux ? nrdout1 : ordout1; - rdout3 <= rdout2; - - de1 <= de_in; de2 <= de1; de3 <= de2; - hs1 <= hs_in; hs2 <= hs1; hs3 <= hs2; - vs1 <= vs_in; vs2 <= vs1; vs3 <= vs2; - - rdout <= rdout3; - de_out <= de3; - hs_out <= hs3; - vs_out <= vs3; -end - -endmodule diff --git a/sys/pll.13.qip b/sys/pll.13.qip deleted file mode 100644 index a6a1dca..0000000 --- a/sys/pll.13.qip +++ /dev/null @@ -1,17 +0,0 @@ -set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll" -set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "13.1" -set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim" -set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] -set_global_assignment -name SYNTHESIS_ONLY_QIP ON - -set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll.v -set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll/pll_0002.v - -set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" -set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" -set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" -set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" - -set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "13.1" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim" diff --git a/sys/pll_audio.13.qip b/sys/pll_audio.13.qip deleted file mode 100644 index e987931..0000000 --- a/sys/pll_audio.13.qip +++ /dev/null @@ -1,17 +0,0 @@ -set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_NAME "altera_pll" -set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_VERSION "13.1" -set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_ENV "mwpim" -set_global_assignment -library "pll_audio" -name MISC_FILE [file join $::quartus(qip_path) "pll_audio.cmp"] -set_global_assignment -name SYNTHESIS_ONLY_QIP ON - -set_global_assignment -library "pll_audio" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_audio.v"] -set_global_assignment -library "pll_audio" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_audio/pll_audio_0002.v"] - -set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" -set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" -set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" -set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" - -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_NAME "altera_pll" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_VERSION "13.1" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_ENV "mwpim" diff --git a/sys/pll_audio.qip b/sys/pll_audio.qip deleted file mode 100644 index abb013b..0000000 --- a/sys/pll_audio.qip +++ /dev/null @@ -1,337 +0,0 @@ -set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_NAME "altera_pll" -set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_VERSION "17.0" -set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_ENV "mwpim" -set_global_assignment -library "pll_audio" -name MISC_FILE [file join $::quartus(qip_path) "pll_audio.cmp"] -set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" -set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" -set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_QSYS_MODE "UNKNOWN" -set_global_assignment -name SYNTHESIS_ONLY_QIP ON -set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_NAME "cGxsX2F1ZGlv" -set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA==" -set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_VERSION "MTcuMA==" -set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_NAME "cGxsX2F1ZGlvXzAwMDI=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_VERSION "MTcuMA==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::MQ==::TnVtYmVyIE9mIENsb2Nrcw==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::MQ==::bnVtYmVyX29mX2Nsb2Nrcw==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MjQuNTc2::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MTUyODMyMTE2Mw==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MTc=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MjQuNTc2MDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NCw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSw5LDgsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwyLDIwLDQwMDAsNDE3Ljc5MiBNSHosMTUyODMyMTE2Myxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw==" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw=" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw=" - -set_global_assignment -library "pll_audio" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_audio.v"] -set_global_assignment -library "pll_audio" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_audio/pll_audio_0002.v"] -set_global_assignment -library "pll_audio" -name QIP_FILE [file join $::quartus(qip_path) "pll_audio/pll_audio_0002.qip"] - -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_NAME "altera_pll" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_VERSION "17.0" -set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_ENV "mwpim" diff --git a/sys/pll_audio.v b/sys/pll_audio.v deleted file mode 100644 index 185a94c..0000000 --- a/sys/pll_audio.v +++ /dev/null @@ -1,252 +0,0 @@ -// megafunction wizard: %Altera PLL v17.0% -// GENERATION: XML -// pll_audio.v - -// Generated using ACDS version 17.0 602 - -`timescale 1 ps / 1 ps -module pll_audio ( - input wire refclk, // refclk.clk - input wire rst, // reset.reset - output wire outclk_0 // outclk0.clk - ); - - pll_audio_0002 pll_audio_inst ( - .refclk (refclk), // refclk.clk - .rst (rst), // reset.reset - .outclk_0 (outclk_0), // outclk0.clk - .locked () // (terminated) - ); - -endmodule -// Retrieval info: -// -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// IPFS_FILES : pll_audio.vo -// RELATED_FILES: pll_audio.v, pll_audio_0002.v diff --git a/sys/pll_audio/pll_audio_0002.qip b/sys/pll_audio/pll_audio_0002.qip deleted file mode 100644 index dadd4b8..0000000 --- a/sys/pll_audio/pll_audio_0002.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" -set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" -set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" -set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" diff --git a/sys/pll_audio/pll_audio_0002.v b/sys/pll_audio/pll_audio_0002.v deleted file mode 100644 index 7898914..0000000 --- a/sys/pll_audio/pll_audio_0002.v +++ /dev/null @@ -1,87 +0,0 @@ -`timescale 1ns/10ps -module pll_audio_0002( - - // interface 'refclk' - input wire refclk, - - // interface 'reset' - input wire rst, - - // interface 'outclk0' - output wire outclk_0, - - // interface 'locked' - output wire locked -); - - altera_pll #( - .fractional_vco_multiplier("true"), - .reference_clock_frequency("50.0 MHz"), - .operation_mode("direct"), - .number_of_clocks(1), - .output_clock_frequency0("24.576000 MHz"), - .phase_shift0("0 ps"), - .duty_cycle0(50), - .output_clock_frequency1("0 MHz"), - .phase_shift1("0 ps"), - .duty_cycle1(50), - .output_clock_frequency2("0 MHz"), - .phase_shift2("0 ps"), - .duty_cycle2(50), - .output_clock_frequency3("0 MHz"), - .phase_shift3("0 ps"), - .duty_cycle3(50), - .output_clock_frequency4("0 MHz"), - .phase_shift4("0 ps"), - .duty_cycle4(50), - .output_clock_frequency5("0 MHz"), - .phase_shift5("0 ps"), - .duty_cycle5(50), - .output_clock_frequency6("0 MHz"), - .phase_shift6("0 ps"), - .duty_cycle6(50), - .output_clock_frequency7("0 MHz"), - .phase_shift7("0 ps"), - .duty_cycle7(50), - .output_clock_frequency8("0 MHz"), - .phase_shift8("0 ps"), - .duty_cycle8(50), - .output_clock_frequency9("0 MHz"), - .phase_shift9("0 ps"), - .duty_cycle9(50), - .output_clock_frequency10("0 MHz"), - .phase_shift10("0 ps"), - .duty_cycle10(50), - .output_clock_frequency11("0 MHz"), - .phase_shift11("0 ps"), - .duty_cycle11(50), - .output_clock_frequency12("0 MHz"), - .phase_shift12("0 ps"), - .duty_cycle12(50), - .output_clock_frequency13("0 MHz"), - .phase_shift13("0 ps"), - .duty_cycle13(50), - .output_clock_frequency14("0 MHz"), - .phase_shift14("0 ps"), - .duty_cycle14(50), - .output_clock_frequency15("0 MHz"), - .phase_shift15("0 ps"), - .duty_cycle15(50), - .output_clock_frequency16("0 MHz"), - .phase_shift16("0 ps"), - .duty_cycle16(50), - .output_clock_frequency17("0 MHz"), - .phase_shift17("0 ps"), - .duty_cycle17(50), - .pll_type("General"), - .pll_subtype("General") - ) altera_pll_i ( - .rst (rst), - .outclk ({outclk_0}), - .locked (locked), - .fboutclk ( ), - .fbclk (1'b0), - .refclk (refclk) - ); -endmodule - diff --git a/sys/pll_cfg.qip b/sys/pll_cfg.qip deleted file mode 100644 index 0b560f9..0000000 --- a/sys/pll_cfg.qip +++ /dev/null @@ -1,5 +0,0 @@ -set_global_assignment -name SYNTHESIS_ONLY_QIP ON -set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/pll_cfg.v"] -set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/pll_cfg_hdmi.v"] -set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_top.v"] -set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_core.v"] diff --git a/sys/pll_cfg/altera_pll_reconfig_core.v b/sys/pll_cfg/altera_pll_reconfig_core.v deleted file mode 100644 index a9e2b8c..0000000 --- a/sys/pll_cfg/altera_pll_reconfig_core.v +++ /dev/null @@ -1,2184 +0,0 @@ -// (C) 2001-2017 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Intel Program License Subscription -// Agreement, Intel MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Intel and sold by -// Intel or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -`timescale 1ps/1ps - -module altera_pll_reconfig_core -#( - parameter reconf_width = 64, - parameter device_family = "Cyclone V", - // MIF Streaming parameters - parameter RECONFIG_ADDR_WIDTH = 6, - parameter RECONFIG_DATA_WIDTH = 32, - parameter ROM_ADDR_WIDTH = 9, - parameter ROM_DATA_WIDTH = 32, - parameter ROM_NUM_WORDS = 512 -) ( - - //input - input wire mgmt_clk, - input wire mgmt_reset, - - - //conduits - output wire [reconf_width-1:0] reconfig_to_pll, - input wire [reconf_width-1:0] reconfig_from_pll, - - // user data (avalon-MM slave interface) - output wire [31:0] mgmt_readdata, - output wire mgmt_waitrequest, - input wire [5:0] mgmt_address, - input wire mgmt_read, - input wire mgmt_write, - input wire [31:0] mgmt_writedata, - - //other - output wire mif_start_out, - output reg [ROM_ADDR_WIDTH-1:0] mif_base_addr -); - localparam mode_WR = 1'b0; - localparam mode_POLL = 1'b1; - localparam MODE_REG = 6'b000000; - localparam STATUS_REG = 6'b000001; - localparam START_REG = 6'b000010; - localparam N_REG = 6'b000011; - localparam M_REG = 6'b000100; - localparam C_COUNTERS_REG = 6'b000101; - localparam DPS_REG = 6'b000110; - localparam DSM_REG = 6'b000111; - localparam BWCTRL_REG = 6'b001000; - localparam CP_CURRENT_REG = 6'b001001; - localparam ANY_DPRIO = 6'b100000; - localparam CNT_BASE = 5'b001010; - localparam VCO_REG = 6'b011100; - localparam MIF_REG = 6'b011111; - - //C Counters - localparam number_of_counters = 5'd18; - localparam CNT_0 = 1'd0, CNT_1 = 5'd1, CNT_2 = 5'd2, - CNT_3 = 5'd3, CNT_4 = 5'd4, CNT_5 = 5'd5, - CNT_6 = 5'd6, CNT_7 = 5'd7, CNT_8 = 5'd8, - CNT_9 = 5'd9, CNT_10 = 5'd10, CNT_11 = 5'd11, - CNT_12 = 5'd12, CNT_13 = 5'd13, CNT_14 = 5'd14, - CNT_15 = 5'd15, CNT_16 = 5'd16, CNT_17 = 5'd17; - //C counter addresses - localparam C_CNT_0_DIV_ADDR = 5'h00; - localparam C_CNT_0_DIV_ADDR_DPRIO_1 = 5'h11; - localparam C_CNT_0_3_BYPASS_EN_ADDR = 5'h15; - localparam C_CNT_0_3_ODD_DIV_EN_ADDR = 5'h17; - localparam C_CNT_4_17_BYPASS_EN_ADDR = 5'h14; - localparam C_CNT_4_17_ODD_DIV_EN_ADDR = 5'h16; - //N counter addresses - localparam N_CNT_DIV_ADDR = 5'h13; - localparam N_CNT_BYPASS_EN_ADDR = 5'h15; - localparam N_CNT_ODD_DIV_EN_ADDR = 5'h17; - //M counter addresses - localparam M_CNT_DIV_ADDR = 5'h12; - localparam M_CNT_BYPASS_EN_ADDR = 5'h15; - localparam M_CNT_ODD_DIV_EN_ADDR = 5'h17; - - //DSM address - localparam DSM_K_FRACTIONAL_DIVISION_ADDR_0 = 5'h18; - localparam DSM_K_FRACTIONAL_DIVISION_ADDR_1 = 5'h19; - localparam DSM_K_READY_ADDR = 5'h17; - localparam DSM_K_DITHER_ADDR = 5'h17; - localparam DSM_OUT_SEL_ADDR = 6'h30; - - //Other DSM params - localparam DSM_K_READY_BIT_INDEX = 4'd11; - //BWCTRL address - //Bit 0-3 of addr - localparam BWCTRL_ADDR = 6'h30; - //CP_CURRENT address - //Bit 0-2 of addr - localparam CP_CURRENT_ADDR = 6'h31; - - // VCODIV address - localparam VCO_ADDR = 5'h17; - - localparam DPRIO_IDLE = 3'd0, ONE = 3'd1, TWO = 3'd2, THREE = 3'd3, FOUR = 3'd4, - FIVE = 3'd5, SIX = 3'd6, SEVEN = 3'd7, EIGHT = 4'd8, NINE = 4'd9, TEN = 4'd10, - ELEVEN = 4'd11, TWELVE = 4'd12, THIRTEEN = 4'd13, FOURTEEN = 4'd14, DPRIO_DONE = 4'd15; - localparam IDLE = 2'b00, WAIT_ON_LOCK = 2'b01, LOCKED = 2'b10; - - wire clk; - wire reset; - wire gnd; - - wire [5: 0] slave_address; - wire slave_read; - wire slave_write; - wire [31: 0] slave_writedata; - - reg [31: 0] slave_readdata_d; - reg [31: 0] slave_readdata_q; - wire slave_waitrequest; - reg slave_mode; - - assign clk = mgmt_clk; - - assign slave_address = mgmt_address; - assign slave_read = mgmt_read; - assign slave_write = mgmt_write; - assign slave_writedata = mgmt_writedata; - - reg read_waitrequest; - // Outputs - assign mgmt_readdata = slave_readdata_q; - assign mgmt_waitrequest = slave_waitrequest | read_waitrequest; //Read waitrequest asserted in polling mode - - //internal signals - wire locked_orig; - wire locked; - - wire pll_start; - wire pll_start_valid; - reg status_read; - wire read_slave_mode_asserted; - - wire pll_start_asserted; - - reg [1:0] current_state; - reg [1:0] next_state; - - reg status;//0=busy, 1=ready - //user_mode_init user_mode_init_inst (clk, reset, dprio_mdio_dis, ser_shift_load); - //declaring the init wires. These will have 0 on them for 64 clk cycles - wire [ 5:0] init_dprio_address; - wire init_dprio_read; - wire [ 1:0] init_dprio_byteen; - wire init_dprio_write; - wire [15:0] init_dprio_writedata; - - wire init_atpgmode; - wire init_mdio_dis; - wire init_scanen; - wire init_ser_shift_load; - wire dprio_init_done; - - //DPRIO output signals after initialization is done - wire dprio_clk; - reg avmm_dprio_write; - reg avmm_dprio_read; - reg [5:0] avmm_dprio_address; - reg [15:0] avmm_dprio_writedata; - reg [1:0] avmm_dprio_byteen; - wire avmm_atpgmode; - wire avmm_mdio_dis; - wire avmm_scanen; - - //Final output wires that are muxed between the init and avmm wires. - wire dprio_init_reset; - wire [5:0] dprio_address /*synthesis keep*/; - wire dprio_read/*synthesis keep*/; - wire [1:0] dprio_byteen/*synthesis keep*/; - wire dprio_write/*synthesis keep*/; - wire [15:0] dprio_writedata/*synthesis keep*/; - wire dprio_mdio_dis/*synthesis keep*/; - wire dprio_ser_shift_load/*synthesis keep*/; - wire dprio_atpgmode/*synthesis keep*/; - wire dprio_scanen/*synthesis keep*/; - - - //other PLL signals for dyn ph shift - wire phase_done/*synthesis keep*/; - wire phase_en/*synthesis keep*/; - wire up_dn/*synthesis keep*/; - wire [4:0] cnt_sel; - - //DPRIO input signals - wire [15:0] dprio_readdata; - - //internal logic signals - //storage registers for user sent data - reg dprio_temp_read_1; - reg dprio_temp_read_2; - reg dprio_start; - reg mif_start_assert; - reg dps_start_assert; - wire usr_valid_changes; - reg [3:0] dprio_cur_state; - reg [3:0] dprio_next_state; - reg [15:0] dprio_temp_m_n_c_readdata_1_d; - reg [15:0] dprio_temp_m_n_c_readdata_2_d; - reg [15:0] dprio_temp_m_n_c_readdata_1_q; - reg [15:0] dprio_temp_m_n_c_readdata_2_q; - reg dprio_write_done; - //C counters signals - reg [7:0] usr_c_cnt_lo; - reg [7:0] usr_c_cnt_hi; - reg usr_c_cnt_bypass_en; - reg usr_c_cnt_odd_duty_div_en; - reg [7:0] temp_c_cnt_lo [0:17]; - reg [7:0] temp_c_cnt_hi [0:17]; - reg temp_c_cnt_bypass_en [0:17]; - reg temp_c_cnt_odd_duty_div_en [0:17]; - reg any_c_cnt_changed; - reg all_c_cnt_done_q; - reg all_c_cnt_done_d; - reg [17:0] c_cnt_changed; - reg [17:0] c_cnt_done_d; - reg [17:0] c_cnt_done_q; - //N counter signals - reg [7:0] usr_n_cnt_lo; - reg [7:0] usr_n_cnt_hi; - reg usr_n_cnt_bypass_en; - reg usr_n_cnt_odd_duty_div_en; - reg n_cnt_changed; - reg n_cnt_done_d; - reg n_cnt_done_q; - //M counter signals - reg [7:0] usr_m_cnt_lo; - reg [7:0] usr_m_cnt_hi; - reg usr_m_cnt_bypass_en; - reg usr_m_cnt_odd_duty_div_en; - reg m_cnt_changed; - reg m_cnt_done_d; - reg m_cnt_done_q; - //dyn phase regs - reg [15:0] usr_num_shifts; - reg [4:0] usr_cnt_sel /*synthesis preserve*/; - reg usr_up_dn; - reg dps_changed; - wire dps_changed_valid; - wire dps_done; - - //DSM Signals - reg [31:0] usr_k_value; - reg dsm_k_changed; - reg dsm_k_done_d; - reg dsm_k_done_q; - reg dsm_k_ready_false_done_d; - //BW signals - reg [3:0] usr_bwctrl_value; - reg bwctrl_changed; - reg bwctrl_done_d; - reg bwctrl_done_q; - //CP signals - reg [2:0] usr_cp_current_value; - reg cp_current_changed; - reg cp_current_done_d; - reg cp_current_done_q; - //VCO signals - reg usr_vco_value; - reg vco_changed; - reg vco_done_d; - reg vco_done_q; - //Manual DPRIO signals - reg manual_dprio_done_q; - reg manual_dprio_done_d; - reg manual_dprio_changed; - reg [5:0] usr_dprio_address; - reg [15:0] usr_dprio_writedata_0; - reg usr_r_w; - //keeping track of which operation happened last - reg [5:0] operation_address; - // Address wires for all C_counter DPRIO registers - // These are outputs of LUTS, changing depending - // on whether PLL_0 or PLL_1 being used - - - //Fitter will tell if FPLL1 is being used - wire fpll_1; - - // other - reg mif_reg_asserted; - // MAIN FSM - - // Synchronize locked signal - altera_std_synchronizer #( - .depth(3) - ) altera_std_synchronizer_inst ( - .clk(mgmt_clk), - .reset_n(~mgmt_reset), - .din(locked_orig), - .dout(locked) - ); - - always @(posedge clk) - begin - if (reset) - begin - dprio_cur_state <= DPRIO_IDLE; - current_state <= IDLE; - end - else - begin - current_state <= next_state; - dprio_cur_state <= dprio_next_state; - end - end - - always @(*) - begin - case(current_state) - IDLE: - begin - if (pll_start & !slave_waitrequest & usr_valid_changes) - next_state = WAIT_ON_LOCK; - else - next_state = IDLE; - end - WAIT_ON_LOCK: - begin - if (locked & dps_done & dprio_write_done) // received locked high from PLL - begin - if (slave_mode==mode_WR) //if the mode is waitrequest, then - // goto IDLE state directly - next_state = IDLE; - else - next_state = LOCKED; //otherwise go the locked state - end - else - next_state = WAIT_ON_LOCK; - end - - LOCKED: - begin - if (status_read) // stay in LOCKED until user reads status - next_state = IDLE; - else - next_state = LOCKED; - end - - default: next_state = 2'bxx; - - endcase - end - - - // ask the pll to start reconfig - assign pll_start = (pll_start_asserted & (current_state==IDLE)) ; - assign pll_start_valid = (pll_start & (next_state==WAIT_ON_LOCK)) ; - - - - // WRITE OPERATIONS - assign pll_start_asserted = slave_write & (slave_address == START_REG); - assign mif_start_out = pll_start & mif_reg_asserted; - - //reading the mode register to determine what mode the slave will operate - //in. - always @(posedge clk) - begin - if (reset) - slave_mode <= mode_WR; - else if (slave_write & (slave_address == MODE_REG) & !slave_waitrequest) - slave_mode <= slave_writedata[0]; - end - - //record which values user wants to change. - - //reading in the actual values that need to be reconfigged and sending - //them to the PLL - always @(posedge clk) - begin - if (reset) - begin - //reset all regs here - //BW signals reset - usr_bwctrl_value <= 0; - bwctrl_changed <= 0; - bwctrl_done_q <= 0; - //CP signals reset - usr_cp_current_value <= 0; - cp_current_changed <= 0; - cp_current_done_q <= 0; - //VCO signals reset - usr_vco_value <= 0; - vco_changed <= 0; - vco_done_q <= 0; - //DSM signals reset - usr_k_value <= 0; - dsm_k_changed <= 0; - dsm_k_done_q <= 0; - //N counter signals reset - usr_n_cnt_lo <= 0; - usr_n_cnt_hi <= 0; - usr_n_cnt_bypass_en <= 0; - usr_n_cnt_odd_duty_div_en <= 0; - n_cnt_changed <= 0; - n_cnt_done_q <= 0; - //M counter signals reset - usr_m_cnt_lo <= 0; - usr_m_cnt_hi <= 0; - usr_m_cnt_bypass_en <= 0; - usr_m_cnt_odd_duty_div_en <= 0; - m_cnt_changed <= 0; - m_cnt_done_q <= 0; - //C counter signals reset - usr_c_cnt_lo <= 0; - usr_c_cnt_hi <= 0; - usr_c_cnt_bypass_en <= 0; - usr_c_cnt_odd_duty_div_en <= 0; - any_c_cnt_changed <= 0; - all_c_cnt_done_q <= 0; - c_cnt_done_q <= 0; - //generic signals - dprio_start <= 0; - mif_start_assert <= 0; - dps_start_assert <= 0; - dprio_temp_m_n_c_readdata_1_q <= 0; - dprio_temp_m_n_c_readdata_2_q <= 0; - c_cnt_done_q <= 0; - //DPS signals - usr_up_dn <= 0; - usr_cnt_sel <= 0; - usr_num_shifts <= 0; - dps_changed <= 0; - //manual DPRIO signals - manual_dprio_changed <= 0; - usr_dprio_address <= 0; - usr_dprio_writedata_0 <= 0; - usr_r_w <= 0; - operation_address <= 0; - mif_reg_asserted <= 0; - mif_base_addr <= 0; - end - else - begin - if (dprio_temp_read_1) - begin - dprio_temp_m_n_c_readdata_1_q <= dprio_temp_m_n_c_readdata_1_d; - end - if (dprio_temp_read_2) - begin - dprio_temp_m_n_c_readdata_2_q <= dprio_temp_m_n_c_readdata_2_d; - end - if ((dps_done)) dps_changed <= 0; - if (dsm_k_done_d) dsm_k_done_q <= dsm_k_done_d; - if (n_cnt_done_d) n_cnt_done_q <= n_cnt_done_d; - if (m_cnt_done_d) m_cnt_done_q <= m_cnt_done_d; - if (all_c_cnt_done_d) all_c_cnt_done_q <= all_c_cnt_done_d; - if (c_cnt_done_d != 0) c_cnt_done_q <= c_cnt_done_q | c_cnt_done_d; - if (bwctrl_done_d) bwctrl_done_q <= bwctrl_done_d; - if (cp_current_done_d) cp_current_done_q <= cp_current_done_d; - if (vco_done_d) vco_done_q <= vco_done_d; - if (manual_dprio_done_d) manual_dprio_done_q <= manual_dprio_done_d; - - if (mif_start_out == 1'b1) - mif_start_assert <= 0; // Signaled MIF block to start, so deassert on next cycle - - if (dps_done != 1'b1) - dps_start_assert <= 0; // DPS has started, so dessert its start signal on next cycle - - if (dprio_next_state == ONE) - dprio_start <= 0; - if (dprio_write_done) - begin - bwctrl_done_q <= 0; - cp_current_done_q <= 0; - vco_done_q <= 0; - dsm_k_done_q <= 0; - dsm_k_done_q <= 0; - n_cnt_done_q <= 0; - m_cnt_done_q <= 0; - all_c_cnt_done_q <= 0; - c_cnt_done_q <= 0; - dsm_k_changed <= 0; - n_cnt_changed <= 0; - m_cnt_changed <= 0; - any_c_cnt_changed <= 0; - bwctrl_changed <= 0; - cp_current_changed <= 0; - vco_changed <= 0; - manual_dprio_changed <= 0; - manual_dprio_done_q <= 0; - if (dps_changed | dps_changed_valid | !dps_done ) - begin - usr_cnt_sel <= usr_cnt_sel; - end - else - begin - usr_cnt_sel <= 0; - end - mif_reg_asserted <= 0; - end - else - begin - dsm_k_changed <= dsm_k_changed; - n_cnt_changed <= n_cnt_changed; - m_cnt_changed <= m_cnt_changed; - any_c_cnt_changed <= any_c_cnt_changed; - manual_dprio_changed <= manual_dprio_changed; - mif_reg_asserted <= mif_reg_asserted; - usr_cnt_sel <= usr_cnt_sel; - end - - - if(slave_write & !slave_waitrequest) - begin - case(slave_address) - //read in the values here from the user and act on them - DSM_REG: - begin - operation_address <= DSM_REG; - usr_k_value <= slave_writedata[31:0]; - dsm_k_changed <= 1'b1; - dsm_k_done_q <= 0; - dprio_start <= 1'b1; - end - N_REG: - begin - operation_address <= N_REG; - usr_n_cnt_lo <= slave_writedata[7:0]; - usr_n_cnt_hi <= slave_writedata[15:8]; - usr_n_cnt_bypass_en <= slave_writedata[16]; - usr_n_cnt_odd_duty_div_en <= slave_writedata[17]; - n_cnt_changed <= 1'b1; - n_cnt_done_q <= 0; - dprio_start <= 1'b1; - end - M_REG: - begin - operation_address <= M_REG; - usr_m_cnt_lo <= slave_writedata[7:0]; - usr_m_cnt_hi <= slave_writedata[15:8]; - usr_m_cnt_bypass_en <= slave_writedata[16]; - usr_m_cnt_odd_duty_div_en <= slave_writedata[17]; - m_cnt_changed <= 1'b1; - m_cnt_done_q <= 0; - dprio_start <= 1'b1; - end - DPS_REG: - begin - operation_address <= DPS_REG; - usr_num_shifts <= slave_writedata[15:0]; - usr_cnt_sel <= slave_writedata[20:16]; - usr_up_dn <= slave_writedata[21]; - dps_changed <= 1; - dps_start_assert <= 1; - end - C_COUNTERS_REG: - begin - operation_address <= C_COUNTERS_REG; - usr_c_cnt_lo <= slave_writedata[7:0]; - usr_c_cnt_hi <= slave_writedata[15:8]; - usr_c_cnt_bypass_en <= slave_writedata[16]; - usr_c_cnt_odd_duty_div_en <= slave_writedata[17]; - usr_cnt_sel <= slave_writedata[22:18]; - any_c_cnt_changed <= 1'b1; - all_c_cnt_done_q <= 0; - dprio_start <= 1'b1; - end - BWCTRL_REG: - begin - usr_bwctrl_value <= slave_writedata[3:0]; - bwctrl_changed <= 1'b1; - bwctrl_done_q <= 0; - dprio_start <= 1'b1; - operation_address <= BWCTRL_REG; - end - CP_CURRENT_REG: - begin - usr_cp_current_value <= slave_writedata[2:0]; - cp_current_changed <= 1'b1; - cp_current_done_q <= 0; - dprio_start <= 1'b1; - operation_address <= CP_CURRENT_REG; - end - VCO_REG: - begin - usr_vco_value <= slave_writedata[0]; - vco_changed <= 1'b1; - vco_done_q <= 0; - dprio_start <= 1'b1; - operation_address <= VCO_REG; - end - ANY_DPRIO: - begin - operation_address <= ANY_DPRIO; - manual_dprio_changed <= 1'b1; - usr_dprio_address <= slave_writedata[5:0]; - usr_dprio_writedata_0 <= slave_writedata[21:6]; - usr_r_w <= slave_writedata[22]; - manual_dprio_done_q <= 0; - dprio_start <= 1'b1; - end - MIF_REG: - begin - mif_reg_asserted <= 1'b1; - mif_base_addr <= slave_writedata[ROM_ADDR_WIDTH-1:0]; - mif_start_assert <= 1'b1; - end - endcase - end - end - end - //C Counter assigning values to the 2-d array of values for each C counter - - reg [4:0] j; - always @(posedge clk) - begin - - if (reset) - begin - c_cnt_changed[17:0] <= 0; - for (j = 0; j < number_of_counters; j = j + 1'b1) - begin : c_cnt_reset - temp_c_cnt_bypass_en[j] <= 0; - temp_c_cnt_odd_duty_div_en[j] <= 0; - temp_c_cnt_lo[j][7:0] <= 0; - temp_c_cnt_hi[j][7:0] <= 0; - end - end - else - begin - if (dprio_write_done) - begin - c_cnt_changed <= 0; - end - if (any_c_cnt_changed && (operation_address == C_COUNTERS_REG)) - begin - case (cnt_sel) - CNT_0: - begin - temp_c_cnt_lo [0] <= usr_c_cnt_lo; - temp_c_cnt_hi [0] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [0] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [0] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [0] <= 1'b1; - end - CNT_1: - begin - temp_c_cnt_lo [1] <= usr_c_cnt_lo; - temp_c_cnt_hi [1] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [1] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [1] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [1] <= 1'b1; - end - CNT_2: - begin - temp_c_cnt_lo [2] <= usr_c_cnt_lo; - temp_c_cnt_hi [2] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [2] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [2] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [2] <= 1'b1; - end - CNT_3: - begin - temp_c_cnt_lo [3] <= usr_c_cnt_lo; - temp_c_cnt_hi [3] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [3] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [3] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [3] <= 1'b1; - end - CNT_4: - begin - temp_c_cnt_lo [4] <= usr_c_cnt_lo; - temp_c_cnt_hi [4] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [4] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [4] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [4] <= 1'b1; - end - CNT_5: - begin - temp_c_cnt_lo [5] <= usr_c_cnt_lo; - temp_c_cnt_hi [5] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [5] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [5] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [5] <= 1'b1; - end - CNT_6: - begin - temp_c_cnt_lo [6] <= usr_c_cnt_lo; - temp_c_cnt_hi [6] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [6] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [6] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [6] <= 1'b1; - end - CNT_7: - begin - temp_c_cnt_lo [7] <= usr_c_cnt_lo; - temp_c_cnt_hi [7] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [7] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [7] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [7] <= 1'b1; - end - CNT_8: - begin - temp_c_cnt_lo [8] <= usr_c_cnt_lo; - temp_c_cnt_hi [8] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [8] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [8] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [8] <= 1'b1; - end - CNT_9: - begin - temp_c_cnt_lo [9] <= usr_c_cnt_lo; - temp_c_cnt_hi [9] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [9] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [9] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [9] <= 1'b1; - end - CNT_10: - begin - temp_c_cnt_lo [10] <= usr_c_cnt_lo; - temp_c_cnt_hi [10] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [10] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [10] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [10] <= 1'b1; - end - CNT_11: - begin - temp_c_cnt_lo [11] <= usr_c_cnt_lo; - temp_c_cnt_hi [11] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [11] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [11] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [11] <= 1'b1; - end - CNT_12: - begin - temp_c_cnt_lo [12] <= usr_c_cnt_lo; - temp_c_cnt_hi [12] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [12] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [12] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [12] <= 1'b1; - end - CNT_13: - begin - temp_c_cnt_lo [13] <= usr_c_cnt_lo; - temp_c_cnt_hi [13] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [13] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [13] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [13] <= 1'b1; - end - CNT_14: - begin - temp_c_cnt_lo [14] <= usr_c_cnt_lo; - temp_c_cnt_hi [14] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [14] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [14] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [14] <= 1'b1; - end - CNT_15: - begin - temp_c_cnt_lo [15] <= usr_c_cnt_lo; - temp_c_cnt_hi [15] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [15] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [15] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [15] <= 1'b1; - end - CNT_16: - begin - temp_c_cnt_lo [16] <= usr_c_cnt_lo; - temp_c_cnt_hi [16] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [16] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [16] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [16] <= 1'b1; - end - CNT_17: - begin - temp_c_cnt_lo [17] <= usr_c_cnt_lo; - temp_c_cnt_hi [17] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [17] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [17] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [17] <= 1'b1; - end - endcase - - end - end - end - - - //logic to handle which writes the user indicated and wants to start. - assign usr_valid_changes =dsm_k_changed| any_c_cnt_changed |n_cnt_changed | m_cnt_changed | dps_changed_valid |manual_dprio_changed |cp_current_changed|bwctrl_changed|vco_changed; - - - //start the reconfig operations by writing to the DPRIO - reg break_loop; - reg [4:0] i; - always @(*) - begin - dprio_temp_read_1 = 0; - dprio_temp_read_2 = 0; - dprio_temp_m_n_c_readdata_1_d = 0; - dprio_temp_m_n_c_readdata_2_d = 0; - break_loop = 0; - dprio_next_state = DPRIO_IDLE; - avmm_dprio_write = 0; - avmm_dprio_read = 0; - avmm_dprio_address = 0; - avmm_dprio_writedata = 0; - avmm_dprio_byteen = 0; - dprio_write_done = 1; - manual_dprio_done_d = 0; - n_cnt_done_d = 0; - dsm_k_done_d = 0; - dsm_k_ready_false_done_d = 0; - m_cnt_done_d = 0; - c_cnt_done_d[17:0] = 0; - all_c_cnt_done_d = 0; - bwctrl_done_d = 0; - cp_current_done_d = 0; - vco_done_d = 0; - i = 0; - - // Deassert dprio_write_done so it doesn't reset mif_reg_asserted (toggled writes) - if (dprio_start | mif_start_assert) - dprio_write_done = 0; - - if (current_state == WAIT_ON_LOCK) - begin - case (dprio_cur_state) - ONE: - begin - if (n_cnt_changed & !n_cnt_done_q) - begin - dprio_write_done = 0; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - dprio_next_state = TWO; - avmm_dprio_address = N_CNT_DIV_ADDR; - avmm_dprio_writedata[7:0] = usr_n_cnt_lo; - avmm_dprio_writedata[15:8] = usr_n_cnt_hi; - end - else if (m_cnt_changed & !m_cnt_done_q) - begin - dprio_write_done = 0; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - dprio_next_state = TWO; - avmm_dprio_address = M_CNT_DIV_ADDR; - avmm_dprio_writedata[7:0] = usr_m_cnt_lo; - avmm_dprio_writedata[15:8] = usr_m_cnt_hi; - end - else if (any_c_cnt_changed & !all_c_cnt_done_q) - begin - - for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) - begin : c_cnt_write_hilo - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - dprio_write_done = 0; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - dprio_next_state = TWO; - if (fpll_1) avmm_dprio_address = C_CNT_0_DIV_ADDR + C_CNT_0_DIV_ADDR_DPRIO_1 - i; - else avmm_dprio_address = C_CNT_0_DIV_ADDR + i; - avmm_dprio_writedata[7:0] = temp_c_cnt_lo[i]; - avmm_dprio_writedata[15:8] = temp_c_cnt_hi[i]; - //To break from the loop, since only one counter - //is addressed at a time - break_loop = 1'b1; - end - end - end - else if (dsm_k_changed & !dsm_k_done_q) - begin - dprio_write_done = 0; - avmm_dprio_write = 0; - dprio_next_state = TWO; - end - else if (bwctrl_changed & !bwctrl_done_q) - begin - dprio_write_done = 0; - avmm_dprio_write = 0; - dprio_next_state = TWO; - end - else if (cp_current_changed & !cp_current_done_q) - begin - dprio_write_done = 0; - avmm_dprio_write = 0; - dprio_next_state = TWO; - end - else if (vco_changed & !vco_done_q) - begin - dprio_write_done = 0; - avmm_dprio_write = 0; - dprio_next_state = TWO; - end - else if (manual_dprio_changed & !manual_dprio_done_q) - begin - dprio_write_done = 0; - avmm_dprio_byteen = 2'b11; - dprio_next_state = TWO; - avmm_dprio_write = usr_r_w; - avmm_dprio_address = usr_dprio_address; - avmm_dprio_writedata[15:0] = usr_dprio_writedata_0; - end - else dprio_next_state = DPRIO_IDLE; - end - - TWO: - begin - //handle reading the two setting bits on n_cnt, then - //writing them back while preserving other bits. - //Issue two consecutive reads then wait; readLatency=3 - dprio_write_done = 0; - dprio_next_state = THREE; - avmm_dprio_byteen = 2'b11; - avmm_dprio_read = 1'b1; - if (n_cnt_changed & !n_cnt_done_q) - begin - avmm_dprio_address = N_CNT_BYPASS_EN_ADDR; - end - else if (m_cnt_changed & !m_cnt_done_q) - begin - avmm_dprio_address = M_CNT_BYPASS_EN_ADDR; - end - - else if (any_c_cnt_changed & !all_c_cnt_done_q) - begin - for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) - begin : c_cnt_read_bypass - if (fpll_1) - begin - if (i > 13) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; - break_loop = 1'b1; - end - end - end - else - begin - if (i < 4) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; - break_loop = 1'b1; - end - end - end - end - end - //reading the K ready 16 bit word. Need to write 0 to it - //afterwards to indicate that K has not been done writing - else if (dsm_k_changed & !dsm_k_done_q) - begin - avmm_dprio_address = DSM_K_READY_ADDR; - dprio_next_state = FOUR; - end - else if (bwctrl_changed & !bwctrl_done_q) - begin - avmm_dprio_address = BWCTRL_ADDR; - dprio_next_state = FOUR; - end - else if (cp_current_changed & !cp_current_done_q) - begin - avmm_dprio_address = CP_CURRENT_ADDR; - dprio_next_state = FOUR; - end - else if (vco_changed & !vco_done_q) - begin - avmm_dprio_address = VCO_ADDR; - dprio_next_state = FOUR; - end - else if (manual_dprio_changed & !manual_dprio_done_q) - begin - avmm_dprio_read = ~usr_r_w; - avmm_dprio_address = usr_dprio_address; - dprio_next_state = DPRIO_DONE; - end - else dprio_next_state = DPRIO_IDLE; - end - THREE: - begin - dprio_write_done = 0; - avmm_dprio_byteen = 2'b11; - avmm_dprio_read = 1'b1; - dprio_next_state = FOUR; - if (n_cnt_changed & !n_cnt_done_q) - begin - avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR; - end - else if (m_cnt_changed & !m_cnt_done_q) - begin - avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR; - end - else if (any_c_cnt_changed & !all_c_cnt_done_q) - begin - for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) - begin : c_cnt_read_odd_div - if (fpll_1) - begin - if (i > 13) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; - break_loop = 1'b1; - end - end - end - else - begin - if (i < 4) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; - break_loop = 1'b1; - end - end - end - end - end - else dprio_next_state = DPRIO_IDLE; - end - FOUR: - begin - dprio_temp_read_1 = 1'b1; - dprio_write_done = 0; - if (vco_changed|cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed) - begin - dprio_temp_m_n_c_readdata_1_d = dprio_readdata; - dprio_next_state = FIVE; - end - else dprio_next_state = DPRIO_IDLE; - end - FIVE: - begin - dprio_write_done = 0; - dprio_temp_read_2 = 1'b1; - if (vco_changed|cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed) - begin - //this is where DSM ready value comes. - //Need to store in a register to be used later - dprio_temp_m_n_c_readdata_2_d = dprio_readdata; - dprio_next_state = SIX; - end - else dprio_next_state = DPRIO_IDLE; - end - SIX: - begin - dprio_write_done = 0; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - dprio_next_state = SEVEN; - avmm_dprio_writedata = dprio_temp_m_n_c_readdata_1_q; - if (n_cnt_changed & !n_cnt_done_q) - begin - avmm_dprio_address = N_CNT_BYPASS_EN_ADDR; - avmm_dprio_writedata[5] = usr_n_cnt_bypass_en; - end - else if (m_cnt_changed & !m_cnt_done_q) - begin - avmm_dprio_address = M_CNT_BYPASS_EN_ADDR; - avmm_dprio_writedata[4] = usr_m_cnt_bypass_en; - end - else if (any_c_cnt_changed & !all_c_cnt_done_q) - begin - for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) - begin : c_cnt_write_bypass - if (fpll_1) - begin - if (i > 13) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; - avmm_dprio_writedata[i-14] = temp_c_cnt_bypass_en[i]; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; - avmm_dprio_writedata[i] = temp_c_cnt_bypass_en[i]; - break_loop = 1'b1; - end - end - end - else - begin - if (i < 4) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; - avmm_dprio_writedata[3-i] = temp_c_cnt_bypass_en[i]; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; - avmm_dprio_writedata[17-i] = temp_c_cnt_bypass_en[i]; - break_loop = 1'b1; - end - end - end - end - end - else if (dsm_k_changed & !dsm_k_done_q) - begin - avmm_dprio_write = 0; - end - else if (bwctrl_changed & !bwctrl_done_q) - begin - avmm_dprio_write = 0; - end - else if (cp_current_changed & !cp_current_done_q) - begin - avmm_dprio_write = 0; - end - else if (vco_changed & !vco_done_q) - begin - avmm_dprio_write = 0; - end - else dprio_next_state = DPRIO_IDLE; - end - SEVEN: - begin - dprio_write_done = 0; - dprio_next_state = EIGHT; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q; - if (n_cnt_changed & !n_cnt_done_q) - begin - avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR; - avmm_dprio_writedata[5] = usr_n_cnt_odd_duty_div_en; - n_cnt_done_d = 1'b1; - end - else if (m_cnt_changed & !m_cnt_done_q) - begin - avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR; - avmm_dprio_writedata[4] = usr_m_cnt_odd_duty_div_en; - m_cnt_done_d = 1'b1; - end - - else if (any_c_cnt_changed & !all_c_cnt_done_q) - begin - for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) - begin : c_cnt_write_odd_div - if (fpll_1) - begin - if (i > 13) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; - avmm_dprio_writedata[i-14] = temp_c_cnt_odd_duty_div_en[i]; - c_cnt_done_d[i] = 1'b1; - //have to OR the signals to prevent - //overwriting of previous dones - c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; - avmm_dprio_writedata[i] = temp_c_cnt_odd_duty_div_en[i]; - c_cnt_done_d[i] = 1'b1; - c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; - break_loop = 1'b1; - end - end - end - else - begin - if (i < 4) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; - avmm_dprio_writedata[3-i] = temp_c_cnt_odd_duty_div_en[i]; - c_cnt_done_d[i] = 1'b1; - //have to OR the signals to prevent - //overwriting of previous dones - c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; - avmm_dprio_writedata[17-i] = temp_c_cnt_odd_duty_div_en[i]; - c_cnt_done_d[i] = 1'b1; - c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; - break_loop = 1'b1; - end - end - end - end - end - else if (dsm_k_changed & !dsm_k_done_q) - begin - avmm_dprio_address = DSM_K_READY_ADDR; - avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b0; - dsm_k_ready_false_done_d = 1'b1; - end - else if (bwctrl_changed & !bwctrl_done_q) - begin - avmm_dprio_address = BWCTRL_ADDR; - avmm_dprio_writedata[3:0] = usr_bwctrl_value; - bwctrl_done_d = 1'b1; - end - else if (cp_current_changed & !cp_current_done_q) - begin - avmm_dprio_address = CP_CURRENT_ADDR; - avmm_dprio_writedata[2:0] = usr_cp_current_value; - cp_current_done_d = 1'b1; - end - else if (vco_changed & !vco_done_q) - begin - avmm_dprio_address = VCO_ADDR; - avmm_dprio_writedata[8] = usr_vco_value; - vco_done_d = 1'b1; - end - - - //if all C_cnt that were changed are done, then assert all_c_cnt_done - if (c_cnt_done_d == c_cnt_changed) - all_c_cnt_done_d = 1'b1; - if (n_cnt_changed & n_cnt_done_d) - dprio_next_state = DPRIO_DONE; - if (any_c_cnt_changed & !all_c_cnt_done_d & !all_c_cnt_done_q) - dprio_next_state = ONE; - else if (m_cnt_changed & !m_cnt_done_d & !m_cnt_done_q) - dprio_next_state = ONE; - else if (dsm_k_changed & !dsm_k_ready_false_done_d) - dprio_next_state = TWO; - else if (dsm_k_changed & !dsm_k_done_q) - dprio_next_state = EIGHT; - else if (bwctrl_changed & !bwctrl_done_d) - dprio_next_state = TWO; - else if (cp_current_changed & !cp_current_done_d) - dprio_next_state = TWO; - else if (vco_changed & !vco_done_d) - dprio_next_state = TWO; - else - begin - dprio_next_state = DPRIO_DONE; - dprio_write_done = 1'b1; - end - end - //finish the rest of the DSM reads/writes - //writing k value, writing k_ready to 1. - EIGHT: - begin - dprio_write_done = 0; - dprio_next_state = NINE; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - if (dsm_k_changed & !dsm_k_done_q) - begin - avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_0; - avmm_dprio_writedata[15:0] = usr_k_value[15:0]; - end - end - NINE: - begin - dprio_write_done = 0; - dprio_next_state = TEN; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - if (dsm_k_changed & !dsm_k_done_q) - begin - avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_1; - avmm_dprio_writedata[15:0] = usr_k_value[31:16]; - end - end - TEN: - begin - dprio_write_done = 0; - dprio_next_state = ONE; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - if (dsm_k_changed & !dsm_k_done_q) - begin - avmm_dprio_address = DSM_K_READY_ADDR; - //already have the readdata for DSM_K_READY_ADDR since we read it - //earlier. Just reuse here - avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q; - avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b1; - dsm_k_done_d = 1'b1; - end - end - DPRIO_DONE: - begin - dprio_write_done = 1'b1; - if (dprio_start) dprio_next_state = DPRIO_IDLE; - else dprio_next_state = DPRIO_DONE; - end - DPRIO_IDLE: - begin - if (dprio_start) dprio_next_state = ONE; - else dprio_next_state = DPRIO_IDLE; - end - default: dprio_next_state = 4'bxxxx; - endcase - end - - end - - - //assert the waitreq signal according to the state of the slave - assign slave_waitrequest = (slave_mode==mode_WR) ? ((locked === 1'b1) ? (((current_state==WAIT_ON_LOCK) & !dprio_write_done) | !dps_done |reset|!dprio_init_done) : 1'b1) : 1'b0; - - // Read operations - always @(*) - begin - status = 0; - if (slave_mode == mode_POLL) - //asserting status to 1 if the slave is done. - status = (current_state == LOCKED); - end - //************************************************************// - //************************************************************// - //******************** READ STATE MACHINE ********************// - //************************************************************// - //************************************************************// - reg [1:0] current_read_state; - reg [1:0] next_read_state; - reg [5:0] slave_address_int_d; - reg [5:0] slave_address_int_q; - reg dprio_read_1; - reg [5:0] dprio_address_1; - reg [1:0] dprio_byteen_1; - reg [4:0] usr_cnt_sel_1; - localparam READ = 2'b00, READ_WAIT = 2'b01, READ_IDLE = 2'b10, READ_POST_WAIT = 2'b11; - - always @(*) - begin - if(next_read_state == READ_IDLE) - begin - read_waitrequest <= 1'b0; - end - else - begin - read_waitrequest <= 1'b1; - end - end - - always @(posedge clk) - begin - if (reset) - begin - current_read_state <= READ_IDLE; - slave_address_int_q <= 0; - slave_readdata_q <= 0; - end - else - begin - current_read_state <= next_read_state; - slave_address_int_q <= slave_address_int_d; - slave_readdata_q <= slave_readdata_d; - end - end - always @(*) - begin - dprio_read_1 = 0; - dprio_address_1 = 0; - dprio_byteen_1 = 0; - slave_address_int_d = 0; - slave_readdata_d = 0; - status_read = 0; - usr_cnt_sel_1 = 0; - case(current_read_state) - READ_IDLE: - begin - slave_address_int_d = 0; - next_read_state = READ_IDLE; - if ((current_state != WAIT_ON_LOCK) && slave_read) - begin - slave_address_int_d = slave_address; - if ((slave_address >= CNT_BASE) && (slave_address < CNT_BASE+18)) - begin - next_read_state = READ_WAIT; - dprio_byteen_1 = 2'b11; - dprio_read_1 = 1'b1; - usr_cnt_sel_1 = (slave_address[4:0] - CNT_BASE); - if (fpll_1) dprio_address_1 = C_CNT_0_DIV_ADDR + C_CNT_0_DIV_ADDR_DPRIO_1 - cnt_sel; - else dprio_address_1 = C_CNT_0_DIV_ADDR + cnt_sel; - end - else - begin - case (slave_address) - MODE_REG: - begin - next_read_state = READ_WAIT; - slave_readdata_d = slave_mode; - end - STATUS_REG: - begin - next_read_state = READ_WAIT; - status_read = 1'b1; - slave_readdata_d = status; - end - N_REG: - begin - dprio_byteen_1 = 2'b11; - dprio_read_1 = 1'b1; - dprio_address_1 = N_CNT_DIV_ADDR; - next_read_state = READ_WAIT; - end - M_REG: - begin - dprio_byteen_1 = 2'b11; - dprio_read_1 = 1'b1; - dprio_address_1 = M_CNT_DIV_ADDR; - next_read_state = READ_WAIT; - end - BWCTRL_REG: - begin - dprio_byteen_1 = 2'b11; - dprio_read_1 = 1'b1; - dprio_address_1 = BWCTRL_ADDR; - next_read_state = READ_WAIT; - end - CP_CURRENT_REG: - begin - dprio_byteen_1 = 2'b11; - dprio_read_1 = 1'b1; - dprio_address_1 = CP_CURRENT_ADDR; - next_read_state = READ_WAIT; - end - VCO_REG: - begin - dprio_byteen_1 = 2'b11; - dprio_read_1 = 1'b1; - dprio_address_1 = VCO_ADDR; - next_read_state = READ_WAIT; - end - ANY_DPRIO: - begin - dprio_byteen_1 = 2'b11; - dprio_read_1 = ~slave_writedata[22]; - dprio_address_1 = slave_writedata[5:0]; - next_read_state = READ_WAIT; - end - default : next_read_state = READ_IDLE; - endcase - end - end - else - next_read_state = READ_IDLE; - end - READ_WAIT: - begin - next_read_state = READ; - slave_address_int_d = slave_address_int_q; - case (slave_address_int_q) - MODE_REG: - begin - slave_readdata_d = slave_readdata_q; - end - STATUS_REG: - begin - slave_readdata_d = slave_readdata_q; - end - endcase - end - READ: - begin - next_read_state = READ_POST_WAIT; - slave_address_int_d = slave_address_int_q; - slave_readdata_d = dprio_readdata; - case (slave_address_int_q) - MODE_REG: - begin - slave_readdata_d = slave_readdata_q; - end - STATUS_REG: - begin - slave_readdata_d = slave_readdata_q; - end - BWCTRL_REG: - begin - slave_readdata_d = dprio_readdata[3:0]; - end - CP_CURRENT_REG: - begin - slave_readdata_d = dprio_readdata[2:0]; - end - VCO_REG: - begin - slave_readdata_d = dprio_readdata[8]; - end - ANY_DPRIO: - begin - slave_readdata_d = dprio_readdata; - end - endcase - end - READ_POST_WAIT: - begin - next_read_state = READ_IDLE; - end - default: next_read_state = 2'bxx; - endcase - end - - - dyn_phase_shift dyn_phase_shift_inst ( - .clk(clk), - .reset(reset), - .phase_done(phase_done), - .pll_start_valid(pll_start_valid), - .dps_changed(dps_changed), - .dps_changed_valid(dps_changed_valid), - .dprio_write_done(dprio_write_done), - .usr_num_shifts(usr_num_shifts), - .usr_cnt_sel(usr_cnt_sel|usr_cnt_sel_1), - .usr_up_dn(usr_up_dn), - .locked(locked), - .dps_done(dps_done), - .phase_en(phase_en), - .up_dn(up_dn), - .cnt_sel(cnt_sel)); - defparam dyn_phase_shift_inst.device_family = device_family; - - assign dprio_clk = clk; - self_reset self_reset_inst (mgmt_reset, clk, reset, dprio_init_reset); - - dprio_mux dprio_mux_inst ( - .init_dprio_address(init_dprio_address), - .init_dprio_read(init_dprio_read), - .init_dprio_byteen(init_dprio_byteen), - .init_dprio_write(init_dprio_write), - .init_dprio_writedata(init_dprio_writedata), - - - .init_atpgmode(init_atpgmode), - .init_mdio_dis(init_mdio_dis), - .init_scanen(init_scanen), - .init_ser_shift_load(init_ser_shift_load), - .dprio_init_done(dprio_init_done), - - // Inputs from avmm master - .avmm_dprio_address(avmm_dprio_address | dprio_address_1), - .avmm_dprio_read(avmm_dprio_read | dprio_read_1), - .avmm_dprio_byteen(avmm_dprio_byteen | dprio_byteen_1), - .avmm_dprio_write(avmm_dprio_write), - .avmm_dprio_writedata(avmm_dprio_writedata), - - .avmm_atpgmode(avmm_atpgmode), - .avmm_mdio_dis(avmm_mdio_dis), - .avmm_scanen(avmm_scanen), - - // Outputs to fpll - .dprio_address(dprio_address), - .dprio_read(dprio_read), - .dprio_byteen(dprio_byteen), - .dprio_write(dprio_write), - .dprio_writedata(dprio_writedata), - - .atpgmode(dprio_atpgmode), - .mdio_dis(dprio_mdio_dis), - .scanen(dprio_scanen), - .ser_shift_load(dprio_ser_shift_load) - ); - - - fpll_dprio_init fpll_dprio_init_inst ( - .clk(clk), - .reset_n(~reset), - .locked(locked), - - //outputs - .dprio_address(init_dprio_address), - .dprio_read(init_dprio_read), - .dprio_byteen(init_dprio_byteen), - .dprio_write(init_dprio_write), - .dprio_writedata(init_dprio_writedata), - - .atpgmode(init_atpgmode), - .mdio_dis(init_mdio_dis), - .scanen(init_scanen), - .ser_shift_load(init_ser_shift_load), - .dprio_init_done(dprio_init_done)); - - //address luts, to be reconfigged by the Fitter - //FPLL_1 or 0 address lut - generic_lcell_comb lcell_fpll_0_1 ( - .dataa(1'b0), - .combout (fpll_1)); - defparam lcell_fpll_0_1.lut_mask = 64'hAAAAAAAAAAAAAAAA; - defparam lcell_fpll_0_1.dont_touch = "on"; - defparam lcell_fpll_0_1.family = device_family; - - - wire dprio_read_combout; - generic_lcell_comb lcell_dprio_read ( - .dataa(fpll_1), - .datab(dprio_read), - .datac(1'b0), - .datad(1'b0), - .datae(1'b0), - .dataf(1'b0), - .combout (dprio_read_combout)); - defparam lcell_dprio_read.lut_mask = 64'hCCCCCCCCCCCCCCCC; - defparam lcell_dprio_read.dont_touch = "on"; - defparam lcell_dprio_read.family = device_family; - - - - - - //assign reconfig_to_pll signals - assign reconfig_to_pll[0] = dprio_clk; - assign reconfig_to_pll[1] = ~dprio_init_reset; - assign reconfig_to_pll[2] = dprio_write; - assign reconfig_to_pll[3] = dprio_read_combout; - assign reconfig_to_pll[9:4] = dprio_address; - assign reconfig_to_pll[25:10] = dprio_writedata; - assign reconfig_to_pll[27:26] = dprio_byteen; - assign reconfig_to_pll[28] = dprio_ser_shift_load; - assign reconfig_to_pll[29] = dprio_mdio_dis; - assign reconfig_to_pll[30] = phase_en; - assign reconfig_to_pll[31] = up_dn; - assign reconfig_to_pll[36:32] = cnt_sel; - assign reconfig_to_pll[37] = dprio_scanen; - assign reconfig_to_pll[38] = dprio_atpgmode; - //assign reconfig_to_pll[40:37] = clken; - assign reconfig_to_pll[63:39] = 0; - - //assign reconfig_from_pll signals - assign dprio_readdata = reconfig_from_pll [15:0]; - assign locked_orig = reconfig_from_pll [16]; - assign phase_done = reconfig_from_pll [17]; - -endmodule -module self_reset (input wire mgmt_reset, input wire clk, output wire reset, output wire init_reset); - - localparam RESET_COUNTER_VALUE = 3'd2; - localparam INITIAL_WAIT_VALUE = 9'd340; - reg [9:0]counter; - reg local_reset; - reg usr_mode_init_wait; - initial - begin - local_reset = 1'b1; - counter = 0; - usr_mode_init_wait = 0; - end - - always @(posedge clk) - begin - if (mgmt_reset) - begin - counter <= 0; - end - else - begin - if (!usr_mode_init_wait) - begin - if (counter == INITIAL_WAIT_VALUE) - begin - local_reset <= 0; - usr_mode_init_wait <= 1'b1; - counter <= 0; - end - else - begin - counter <= counter + 1'b1; - end - end - else - begin - if (counter == RESET_COUNTER_VALUE) - local_reset <= 0; - else - counter <= counter + 1'b1; - end - end - end - assign reset = mgmt_reset | local_reset; - assign init_reset = local_reset; -endmodule - -module dprio_mux ( - // Inputs from init block - input [ 5:0] init_dprio_address, - input init_dprio_read, - input [ 1:0] init_dprio_byteen, - input init_dprio_write, - input [15:0] init_dprio_writedata, - - input init_atpgmode, - input init_mdio_dis, - input init_scanen, - input init_ser_shift_load, - input dprio_init_done, - - // Inputs from avmm master - input [ 5:0] avmm_dprio_address, - input avmm_dprio_read, - input [ 1:0] avmm_dprio_byteen, - input avmm_dprio_write, - input [15:0] avmm_dprio_writedata, - - input avmm_atpgmode, - input avmm_mdio_dis, - input avmm_scanen, - input avmm_ser_shift_load, - - // Outputs to fpll - output [ 5:0] dprio_address, - output dprio_read, - output [ 1:0] dprio_byteen, - output dprio_write, - output [15:0] dprio_writedata, - - output atpgmode, - output mdio_dis, - output scanen, - output ser_shift_load -); - - assign dprio_address = dprio_init_done ? avmm_dprio_address : init_dprio_address; - assign dprio_read = dprio_init_done ? avmm_dprio_read : init_dprio_read; - assign dprio_byteen = dprio_init_done ? avmm_dprio_byteen : init_dprio_byteen; - assign dprio_write = dprio_init_done ? avmm_dprio_write : init_dprio_write; - assign dprio_writedata = dprio_init_done ? avmm_dprio_writedata : init_dprio_writedata; - - assign atpgmode = init_atpgmode; - assign scanen = init_scanen; - assign mdio_dis = init_mdio_dis; - assign ser_shift_load = init_ser_shift_load ; -endmodule -module fpll_dprio_init ( - input clk, - input reset_n, - input locked, - - output [ 5:0] dprio_address, - output dprio_read, - output [ 1:0] dprio_byteen, - output dprio_write, - output [15:0] dprio_writedata, - - output reg atpgmode, - output reg mdio_dis, - output reg scanen, - output reg ser_shift_load, - output reg dprio_init_done -); - - reg [1:0] rst_n = 2'b00; - reg [6:0] count = 7'd0; - reg init_done_forever; - - // Internal versions of control signals - wire int_mdio_dis; - wire int_ser_shift_load; - wire int_dprio_init_done; - wire int_atpgmode/*synthesis keep*/; - wire int_scanen/*synthesis keep*/; - - - assign dprio_address = count[6] ? 5'b0 : count[5:0] ; - assign dprio_byteen = 2'b11; // always enabled - assign dprio_write = ~count[6] & reset_n ; // write for first 64 cycles - assign dprio_read = 1'b0; - assign dprio_writedata = 16'd0; - - assign int_ser_shift_load = count[6] ? |count[2:1] : 1'b1; - assign int_mdio_dis = count[6] ? ~count[2] : 1'b1; - assign int_dprio_init_done = ~init_done_forever ? (count[6] ? &count[2:0] : 1'b0) - : 1'b1; - assign int_atpgmode = 0; - assign int_scanen = 0; - - initial begin - count = 7'd0; - init_done_forever = 0; - mdio_dis = 1'b1; - ser_shift_load = 1'b1; - dprio_init_done = 1'b0; - scanen = 1'b0; - atpgmode = 1'b0; - end - - // reset synch. - always @(posedge clk or negedge reset_n) - if(!reset_n) rst_n <= 2'b00; - else rst_n <= {rst_n[0],1'b1}; - - // counter - always @(posedge clk) - begin - if (!rst_n[1]) - init_done_forever <= 1'b0; - else - begin - if (count[6] && &count[1:0]) - init_done_forever <= 1'b1; - end - end - always @(posedge clk or negedge rst_n[1]) - begin - if(!rst_n[1]) - begin - count <= 7'd0; - end - else if(~int_dprio_init_done) - begin - count <= count + 7'd1; - end - else - begin - count <= count; - end - end - - // outputs - always @(posedge clk) begin - mdio_dis <= int_mdio_dis; - ser_shift_load <= int_ser_shift_load; - dprio_init_done <= int_dprio_init_done; - atpgmode <= int_atpgmode; - scanen <= int_scanen; - end - -endmodule -module dyn_phase_shift -#( - parameter device_family = "Cyclone V" -) ( - - input wire clk, - input wire reset, - input wire phase_done, - input wire pll_start_valid, - input wire dps_changed, - input wire dprio_write_done, - input wire [15:0] usr_num_shifts, - input wire [4:0] usr_cnt_sel, - input wire usr_up_dn, - input wire locked, - - //output - output wire dps_done, - output reg phase_en, - output wire up_dn, - output wire dps_changed_valid, - output wire [4:0] cnt_sel); - - - - reg first_phase_shift_d; - reg first_phase_shift_q; - reg [15:0] phase_en_counter; - reg [3:0] dps_current_state; - reg [3:0] dps_next_state; - localparam DPS_START = 4'd0, DPS_WAIT_PHASE_DONE = 4'd1, DPS_DONE = 4'd2, DPS_WAIT_PHASE_EN = 4'd3, DPS_WAIT_DPRIO_WRITING = 4'd4, DPS_CHANGED = 4'd5; - localparam PHASE_EN_WAIT_COUNTER = 5'd1; - - reg [15:0] shifts_done_counter; - reg phase_done_final; - wire gnd /*synthesis keep*/; - - //fsm - //always block controlling the state regs - always @(posedge clk) - begin - if (reset) - begin - dps_current_state <= DPS_DONE; - end - else - begin - dps_current_state <= dps_next_state; - end - end - //the combinational part. assigning the next state - //this turns on the phase_done_final signal when phase_done does this: - //_____ ______ - // |______| - always @(*) - begin - phase_done_final = 0; - first_phase_shift_d = 0; - phase_en = 0; - dps_next_state = DPS_DONE; - case (dps_current_state) - DPS_START: - begin - phase_en = 1'b1; - dps_next_state = DPS_WAIT_PHASE_EN; - end - DPS_WAIT_PHASE_EN: - begin - phase_en = 1'b1; - if (first_phase_shift_q) - begin - first_phase_shift_d = 1'b1; - dps_next_state = DPS_WAIT_PHASE_EN; - end - else - begin - if (phase_en_counter == PHASE_EN_WAIT_COUNTER) - dps_next_state = DPS_WAIT_PHASE_DONE; - else dps_next_state = DPS_WAIT_PHASE_EN; - end - end - DPS_WAIT_PHASE_DONE: - begin - if (!phase_done | !locked) - begin - dps_next_state = DPS_WAIT_PHASE_DONE; - end - else - begin - if ((usr_num_shifts != shifts_done_counter) & (usr_num_shifts != 0)) - begin - dps_next_state = DPS_START; - phase_done_final = 1'b1; - end - else - begin - dps_next_state = DPS_DONE; - end - - end - end - DPS_DONE: - begin - phase_done_final = 0; - if (dps_changed) - dps_next_state = DPS_CHANGED; - else dps_next_state = DPS_DONE; - - end - DPS_CHANGED: - begin - if (pll_start_valid) - dps_next_state = DPS_WAIT_DPRIO_WRITING; - else - dps_next_state = DPS_CHANGED; - end - DPS_WAIT_DPRIO_WRITING: - begin - if (dprio_write_done) - dps_next_state = DPS_START; - else - dps_next_state = DPS_WAIT_DPRIO_WRITING; - end - - default: dps_next_state = 4'bxxxx; - endcase - - - end - - always @(posedge clk) - begin - - - if (dps_current_state == DPS_WAIT_PHASE_DONE) - phase_en_counter <= 0; - else if (dps_current_state == DPS_WAIT_PHASE_EN) - phase_en_counter <= phase_en_counter + 1'b1; - - if (reset) - begin - phase_en_counter <= 0; - shifts_done_counter <= 1'b1; - first_phase_shift_q <= 1; - end - else - begin - if (first_phase_shift_d) - first_phase_shift_q <= 0; - if (dps_done) - begin - shifts_done_counter <= 1'b1; - end - else - begin - if (phase_done_final & (dps_next_state!= DPS_DONE)) - shifts_done_counter <= shifts_done_counter + 1'b1; - else - shifts_done_counter <= shifts_done_counter; - end - end - end - - assign dps_changed_valid = (dps_current_state == DPS_CHANGED); - assign dps_done =(dps_current_state == DPS_DONE) | (dps_current_state == DPS_CHANGED); - assign up_dn = usr_up_dn; - assign gnd = 1'b0; - - //cnt select luts (5) - generic_lcell_comb lcell_cnt_sel_0 ( - .dataa(usr_cnt_sel[0]), - .datab(usr_cnt_sel[1]), - .datac(usr_cnt_sel[2]), - .datad(usr_cnt_sel[3]), - .datae(usr_cnt_sel[4]), - .dataf(gnd), - .combout (cnt_sel[0])); - defparam lcell_cnt_sel_0.lut_mask = 64'hAAAAAAAAAAAAAAAA; - defparam lcell_cnt_sel_0.dont_touch = "on"; - defparam lcell_cnt_sel_0.family = device_family; - generic_lcell_comb lcell_cnt_sel_1 ( - .dataa(usr_cnt_sel[0]), - .datab(usr_cnt_sel[1]), - .datac(usr_cnt_sel[2]), - .datad(usr_cnt_sel[3]), - .datae(usr_cnt_sel[4]), - .dataf(gnd), - .combout (cnt_sel[1])); - defparam lcell_cnt_sel_1.lut_mask = 64'hCCCCCCCCCCCCCCCC; - defparam lcell_cnt_sel_1.dont_touch = "on"; - defparam lcell_cnt_sel_1.family = device_family; - generic_lcell_comb lcell_cnt_sel_2 ( - .dataa(usr_cnt_sel[0]), - .datab(usr_cnt_sel[1]), - .datac(usr_cnt_sel[2]), - .datad(usr_cnt_sel[3]), - .datae(usr_cnt_sel[4]), - .dataf(gnd), - .combout (cnt_sel[2])); - defparam lcell_cnt_sel_2.lut_mask = 64'hF0F0F0F0F0F0F0F0; - defparam lcell_cnt_sel_2.dont_touch = "on"; - defparam lcell_cnt_sel_2.family = device_family; - generic_lcell_comb lcell_cnt_sel_3 ( - .dataa(usr_cnt_sel[0]), - .datab(usr_cnt_sel[1]), - .datac(usr_cnt_sel[2]), - .datad(usr_cnt_sel[3]), - .datae(usr_cnt_sel[4]), - .dataf(gnd), - .combout (cnt_sel[3])); - defparam lcell_cnt_sel_3.lut_mask = 64'hFF00FF00FF00FF00; - defparam lcell_cnt_sel_3.dont_touch = "on"; - defparam lcell_cnt_sel_3.family = device_family; - generic_lcell_comb lcell_cnt_sel_4 ( - .dataa(usr_cnt_sel[0]), - .datab(usr_cnt_sel[1]), - .datac(usr_cnt_sel[2]), - .datad(usr_cnt_sel[3]), - .datae(usr_cnt_sel[4]), - .dataf(gnd), - .combout (cnt_sel[4])); - defparam lcell_cnt_sel_4.lut_mask = 64'hFFFF0000FFFF0000; - defparam lcell_cnt_sel_4.dont_touch = "on"; - defparam lcell_cnt_sel_4.family = device_family; - - -endmodule - -module generic_lcell_comb -#( - //parameter - parameter family = "Cyclone V", - parameter lut_mask = 64'hAAAAAAAAAAAAAAAA, - parameter dont_touch = "on" -) ( - - input dataa, - input datab, - input datac, - input datad, - input datae, - input dataf, - - output combout -); - - generate - if (family == "Stratix V") - begin - stratixv_lcell_comb lcell_inst ( - .dataa(dataa), - .datab(datab), - .datac(datac), - .datad(datad), - .datae(datae), - .dataf(dataf), - .combout (combout)); - defparam lcell_inst.lut_mask = lut_mask; - defparam lcell_inst.dont_touch = dont_touch; - end - else if (family == "Arria V") - begin - arriav_lcell_comb lcell_inst ( - .dataa(dataa), - .datab(datab), - .datac(datac), - .datad(datad), - .datae(datae), - .dataf(dataf), - .combout (combout)); - defparam lcell_inst.lut_mask = lut_mask; - defparam lcell_inst.dont_touch = dont_touch; - end - else if (family == "Arria V GZ") - begin - arriavgz_lcell_comb lcell_inst ( - .dataa(dataa), - .datab(datab), - .datac(datac), - .datad(datad), - .datae(datae), - .dataf(dataf), - .combout (combout)); - defparam lcell_inst.lut_mask = lut_mask; - defparam lcell_inst.dont_touch = dont_touch; - end - else if (family == "Cyclone V") - begin - cyclonev_lcell_comb lcell_inst ( - .dataa(dataa), - .datab(datab), - .datac(datac), - .datad(datad), - .datae(datae), - .dataf(dataf), - .combout (combout)); - defparam lcell_inst.lut_mask = lut_mask; - defparam lcell_inst.dont_touch = dont_touch; - end - endgenerate -endmodule diff --git a/sys/pll_cfg/altera_pll_reconfig_top.v b/sys/pll_cfg/altera_pll_reconfig_top.v deleted file mode 100644 index 843c970..0000000 --- a/sys/pll_cfg/altera_pll_reconfig_top.v +++ /dev/null @@ -1,428 +0,0 @@ -// (C) 2001-2017 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Intel Program License Subscription -// Agreement, Intel MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Intel and sold by -// Intel or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -`timescale 1ps/1ps - -module altera_pll_reconfig_top -#( - parameter reconf_width = 64, - parameter device_family = "Cyclone V", - parameter RECONFIG_ADDR_WIDTH = 6, - parameter RECONFIG_DATA_WIDTH = 32, - - parameter ROM_ADDR_WIDTH = 9, - parameter ROM_DATA_WIDTH = 32, - parameter ROM_NUM_WORDS = 512, - - parameter ENABLE_MIF = 0, - parameter MIF_FILE_NAME = "", - - parameter ENABLE_BYTEENABLE = 0, - parameter BYTEENABLE_WIDTH = 4, - parameter WAIT_FOR_LOCK = 1 -) ( - - //input - input wire mgmt_clk, - input wire mgmt_reset, - - - //conduits - output wire [reconf_width-1:0] reconfig_to_pll, - input wire [reconf_width-1:0] reconfig_from_pll, - - // user data (avalon-MM slave interface) - output wire [RECONFIG_DATA_WIDTH-1:0] mgmt_readdata, - output wire mgmt_waitrequest, - input wire [RECONFIG_ADDR_WIDTH-1:0] mgmt_address, - input wire mgmt_read, - input wire mgmt_write, - input wire [RECONFIG_DATA_WIDTH-1:0] mgmt_writedata, - - //conditional input - input wire [BYTEENABLE_WIDTH-1:0] mgmt_byteenable -); - -localparam NM28_START_REG = 6'b000010; -localparam NM20_START_REG = 9'b000000000; -localparam NM20_MIFSTART_ADDR = 9'b000010000; - -localparam MIF_STATE_DONE = 2'b00; -localparam MIF_STATE_START = 2'b01; -localparam MIF_STATE_BUSY = 2'b10; - -wire mgmt_byteenable_write; -assign mgmt_byteenable_write = (ENABLE_BYTEENABLE == 1) ? - ((mgmt_byteenable == {BYTEENABLE_WIDTH{1'b1}}) ? mgmt_write : 1'b0) : - mgmt_write; - -generate -if (device_family == "Arria 10") -begin:nm20_reconfig - if(ENABLE_MIF == 1) - begin:mif_reconfig_20nm // Generate Reconfig with MIF - - // MIF-related regs/wires - reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_mgmt_addr; - reg reconfig_mgmt_read; - reg reconfig_mgmt_write; - reg [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_writedata; - wire reconfig_mgmt_waitrequest; - wire [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_readdata; - - wire [RECONFIG_ADDR_WIDTH-1:0] mif2reconfig_addr; - wire mif_busy; - wire mif2reconfig_read; - wire mif2reconfig_write; - wire [RECONFIG_DATA_WIDTH-1:0] mif2reconfig_writedata; - wire [ROM_ADDR_WIDTH-1:0] mif_base_addr; - reg mif_select; - //wire mif_user_start; // start signal provided by user to start mif - //reg user_start; - - reg [1:0] mif_curstate; - reg [1:0] mif_nextstate; - - wire mif_start; //start signal to mif reader - - assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif_busy;// | user_start; - // Don't output readdata if MIF streaming is taking place - assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata; - - //user must lower this by the time mif streaming is done - suggest to lower after 1 cycle - assign mif_start = mgmt_byteenable_write & (mgmt_address == NM20_MIFSTART_ADDR); - - //mif base addr is initially specified by the user - assign mif_base_addr = mgmt_writedata[ROM_ADDR_WIDTH-1:0]; - - //MIF statemachine - always @(posedge mgmt_clk) - begin - if(mgmt_reset) - mif_curstate <= MIF_STATE_DONE; - else - mif_curstate <= mif_nextstate; - end - - always @(*) - begin - case (mif_curstate) - MIF_STATE_DONE: - begin - if(mif_start) - mif_nextstate <= MIF_STATE_START; - else - mif_nextstate <= MIF_STATE_DONE; - end - MIF_STATE_START: - begin - mif_nextstate <= MIF_STATE_BUSY; - end - MIF_STATE_BUSY: - begin - if(mif_busy) - mif_nextstate <= MIF_STATE_BUSY; - else - mif_nextstate <= MIF_STATE_DONE; - end - endcase - end - - //Mif muxes - always @(*) - begin - if (mgmt_reset) - begin - reconfig_mgmt_addr <= 0; - reconfig_mgmt_read <= 0; - reconfig_mgmt_write <= 0; - reconfig_mgmt_writedata <= 0; - //user_start <= 0; - end - else - begin - reconfig_mgmt_addr <= (mif_select) ? mif2reconfig_addr : mgmt_address; - reconfig_mgmt_read <= (mif_select) ? mif2reconfig_read : mgmt_read; - reconfig_mgmt_write <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write; - reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata; - //user_start <= (mgmt_address == NM20_START_REG && mgmt_write == 1'b1) ? 1'b1 : 1'b0; - end - end - - always @(*) - begin - if (mgmt_reset) - begin - mif_select <= 0; - end - else - begin - mif_select <= (mif_start || mif_busy) ? 1'b1 : 1'b0; - end - end - - twentynm_pll_reconfig_mif_reader - #( - .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH), - .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH), - .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH), - .ROM_DATA_WIDTH(ROM_DATA_WIDTH), - .ROM_NUM_WORDS(ROM_NUM_WORDS), - .DEVICE_FAMILY(device_family), - .ENABLE_MIF(ENABLE_MIF), - .MIF_FILE_NAME(MIF_FILE_NAME) - ) twentynm_pll_reconfig_mif_reader_inst0 ( - .mif_clk(mgmt_clk), - .mif_rst(mgmt_reset), - - //Altera_PLL Reconfig interface - //inputs - .reconfig_waitrequest(reconfig_mgmt_waitrequest), - //.reconfig_read_data(reconfig_mgmt_readdata), - //outputs - .reconfig_write_data(mif2reconfig_writedata), - .reconfig_addr(mif2reconfig_addr), - .reconfig_write(mif2reconfig_write), - .reconfig_read(mif2reconfig_read), - - //MIF Ctrl Interface - //inputs - .mif_base_addr(mif_base_addr), - .mif_start(mif_start), - //outputs - .mif_busy(mif_busy) - ); - - // ------ END MIF-RELATED MANAGEMENT ------ - - twentynm_iopll_reconfig_core - #( - .WAIT_FOR_LOCK(WAIT_FOR_LOCK) - ) twentynm_iopll_reconfig_core_inst ( - // Inputs - .mgmt_clk(mgmt_clk), - .mgmt_rst_n(~mgmt_reset), - .mgmt_read(reconfig_mgmt_read), - .mgmt_write(reconfig_mgmt_write), - .mgmt_address(reconfig_mgmt_addr), - .mgmt_writedata(reconfig_mgmt_writedata), - - // Outputs - .mgmt_readdata(reconfig_mgmt_readdata), - .mgmt_waitrequest(reconfig_mgmt_waitrequest), - - // PLL Conduits - .reconfig_to_pll(reconfig_to_pll), - .reconfig_from_pll(reconfig_from_pll) - ); - - end // End generate reconfig with MIF - else - begin:reconfig_core_20nm - twentynm_iopll_reconfig_core - #( - .WAIT_FOR_LOCK(WAIT_FOR_LOCK) - ) twentynm_iopll_reconfig_core_inst ( - // Inputs - .mgmt_clk(mgmt_clk), - .mgmt_rst_n(~mgmt_reset), - .mgmt_read(mgmt_read), - .mgmt_write(mgmt_byteenable_write), - .mgmt_address(mgmt_address), - .mgmt_writedata(mgmt_writedata), - - // Outputs - .mgmt_readdata(mgmt_readdata), - .mgmt_waitrequest(mgmt_waitrequest), - - // PLL Conduits - .reconfig_to_pll(reconfig_to_pll), - .reconfig_from_pll(reconfig_from_pll) - ); - end -end // 20nm reconfig -else -begin:NM28_reconfig - if (ENABLE_MIF == 1) - begin:mif_reconfig // Generate Reconfig with MIF - - // MIF-related regs/wires - reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_mgmt_addr; - reg reconfig_mgmt_read; - reg reconfig_mgmt_write; - reg [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_writedata; - wire reconfig_mgmt_waitrequest; - wire [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_readdata; - - wire [RECONFIG_ADDR_WIDTH-1:0] mif2reconfig_addr; - wire mif2reconfig_busy; - wire mif2reconfig_read; - wire mif2reconfig_write; - wire [RECONFIG_DATA_WIDTH-1:0] mif2reconfig_writedata; - wire [ROM_ADDR_WIDTH-1:0] mif_base_addr; - reg mif_select; - reg user_start; - - wire reconfig2mif_start_out; - - assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif2reconfig_busy | user_start; - // Don't output readdata if MIF streaming is taking place - assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata; - - always @(posedge mgmt_clk) - begin - if (mgmt_reset) - begin - reconfig_mgmt_addr <= 0; - reconfig_mgmt_read <= 0; - reconfig_mgmt_write <= 0; - reconfig_mgmt_writedata <= 0; - user_start <= 0; - end - else - begin - reconfig_mgmt_addr <= (mif_select) ? mif2reconfig_addr : mgmt_address; - reconfig_mgmt_read <= (mif_select) ? mif2reconfig_read : mgmt_read; - reconfig_mgmt_write <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write; - reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata; - user_start <= (mgmt_address == NM28_START_REG && mgmt_byteenable_write == 1'b1) ? 1'b1 : 1'b0; - end - end - - always @(*) - begin - if (mgmt_reset) - begin - mif_select <= 0; - end - else - begin - mif_select <= (reconfig2mif_start_out || mif2reconfig_busy) ? 1'b1 : 1'b0; - end - end - - altera_pll_reconfig_mif_reader - #( - .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH), - .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH), - .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH), - .ROM_DATA_WIDTH(ROM_DATA_WIDTH), - .ROM_NUM_WORDS(ROM_NUM_WORDS), - .DEVICE_FAMILY(device_family), - .ENABLE_MIF(ENABLE_MIF), - .MIF_FILE_NAME(MIF_FILE_NAME) - ) altera_pll_reconfig_mif_reader_inst0 ( - .mif_clk(mgmt_clk), - .mif_rst(mgmt_reset), - - //Altera_PLL Reconfig interface - //inputs - .reconfig_busy(reconfig_mgmt_waitrequest), - .reconfig_read_data(reconfig_mgmt_readdata), - //outputs - .reconfig_write_data(mif2reconfig_writedata), - .reconfig_addr(mif2reconfig_addr), - .reconfig_write(mif2reconfig_write), - .reconfig_read(mif2reconfig_read), - - //MIF Ctrl Interface - //inputs - .mif_base_addr(mif_base_addr), - .mif_start(reconfig2mif_start_out), - //outputs - .mif_busy(mif2reconfig_busy) - ); - - // ------ END MIF-RELATED MANAGEMENT ------ - - - altera_pll_reconfig_core - #( - .reconf_width(reconf_width), - .device_family(device_family), - .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH), - .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH), - .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH), - .ROM_DATA_WIDTH(ROM_DATA_WIDTH), - .ROM_NUM_WORDS(ROM_NUM_WORDS) - ) altera_pll_reconfig_core_inst0 ( - //inputs - .mgmt_clk(mgmt_clk), - .mgmt_reset(mgmt_reset), - - //PLL interface conduits - .reconfig_to_pll(reconfig_to_pll), - .reconfig_from_pll(reconfig_from_pll), - - //User data outputs - .mgmt_readdata(reconfig_mgmt_readdata), - .mgmt_waitrequest(reconfig_mgmt_waitrequest), - - //User data inputs - .mgmt_address(reconfig_mgmt_addr), - .mgmt_read(reconfig_mgmt_read), - .mgmt_write(reconfig_mgmt_write), - .mgmt_writedata(reconfig_mgmt_writedata), - - // other - .mif_start_out(reconfig2mif_start_out), - .mif_base_addr(mif_base_addr) - ); - - end // End generate reconfig with MIF - else - begin:reconfig_core // Generate Reconfig core only - - wire reconfig2mif_start_out; - wire [ROM_ADDR_WIDTH-1:0] mif_base_addr; - - altera_pll_reconfig_core - #( - .reconf_width(reconf_width), - .device_family(device_family), - .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH), - .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH), - .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH), - .ROM_DATA_WIDTH(ROM_DATA_WIDTH), - .ROM_NUM_WORDS(ROM_NUM_WORDS) - ) altera_pll_reconfig_core_inst0 ( - //inputs - .mgmt_clk(mgmt_clk), - .mgmt_reset(mgmt_reset), - - //PLL interface conduits - .reconfig_to_pll(reconfig_to_pll), - .reconfig_from_pll(reconfig_from_pll), - - //User data outputs - .mgmt_readdata(mgmt_readdata), - .mgmt_waitrequest(mgmt_waitrequest), - - //User data inputs - .mgmt_address(mgmt_address), - .mgmt_read(mgmt_read), - .mgmt_write(mgmt_byteenable_write), - .mgmt_writedata(mgmt_writedata), - - // other - .mif_start_out(reconfig2mif_start_out), - .mif_base_addr(mif_base_addr) - ); - - - end // End generate reconfig core only -end // End 28nm Reconfig -endgenerate - -endmodule - diff --git a/sys/pll_cfg/pll_cfg.v b/sys/pll_cfg/pll_cfg.v deleted file mode 100644 index 0adc36f..0000000 --- a/sys/pll_cfg/pll_cfg.v +++ /dev/null @@ -1,86 +0,0 @@ -// megafunction wizard: %Altera PLL Reconfig v17.0% -// GENERATION: XML -// pll_cfg.v - -// Generated using ACDS version 17.0 598 - -`timescale 1 ps / 1 ps -module pll_cfg #( - parameter ENABLE_BYTEENABLE = 0, - parameter BYTEENABLE_WIDTH = 4, - parameter RECONFIG_ADDR_WIDTH = 6, - parameter RECONFIG_DATA_WIDTH = 32, - parameter reconf_width = 64, - parameter WAIT_FOR_LOCK = 1 - ) ( - input wire mgmt_clk, // mgmt_clk.clk - input wire mgmt_reset, // mgmt_reset.reset - output wire mgmt_waitrequest, // mgmt_avalon_slave.waitrequest - input wire mgmt_read, // .read - input wire mgmt_write, // .write - output wire [31:0] mgmt_readdata, // .readdata - input wire [5:0] mgmt_address, // .address - input wire [31:0] mgmt_writedata, // .writedata - output wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll - input wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll - ); - - altera_pll_reconfig_top #( - .device_family ("Cyclone V"), - .ENABLE_MIF (0), - .MIF_FILE_NAME ("sys/pll_cfg.mif"), - .ENABLE_BYTEENABLE (ENABLE_BYTEENABLE), - .BYTEENABLE_WIDTH (BYTEENABLE_WIDTH), - .RECONFIG_ADDR_WIDTH (RECONFIG_ADDR_WIDTH), - .RECONFIG_DATA_WIDTH (RECONFIG_DATA_WIDTH), - .reconf_width (reconf_width), - .WAIT_FOR_LOCK (WAIT_FOR_LOCK) - ) pll_cfg_inst ( - .mgmt_clk (mgmt_clk), // mgmt_clk.clk - .mgmt_reset (mgmt_reset), // mgmt_reset.reset - .mgmt_waitrequest (mgmt_waitrequest), // mgmt_avalon_slave.waitrequest - .mgmt_read (mgmt_read), // .read - .mgmt_write (mgmt_write), // .write - .mgmt_readdata (mgmt_readdata), // .readdata - .mgmt_address (mgmt_address), // .address - .mgmt_writedata (mgmt_writedata), // .writedata - .reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll - .reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll - .mgmt_byteenable (4'b0000) // (terminated) - ); - -endmodule -// Retrieval info: -// -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// IPFS_FILES : pll_cfg.vo -// RELATED_FILES: pll_cfg.v, altera_pll_reconfig_top.v, altera_pll_reconfig_core.v, altera_std_synchronizer.v diff --git a/sys/pll_cfg/pll_cfg_hdmi.v b/sys/pll_cfg/pll_cfg_hdmi.v deleted file mode 100644 index 1912c2a..0000000 --- a/sys/pll_cfg/pll_cfg_hdmi.v +++ /dev/null @@ -1,1282 +0,0 @@ -// (C) 2001-2017 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Intel Program License Subscription -// Agreement, Intel MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Intel and sold by -// Intel or its authorized distributors. Please refer to the applicable -// agreement for further details. - -// original file was altera_pll_reconfig_core.v -// not needed functionality was cut out to reduce ressource consumption - -module pll_cfg_hdmi -#( - parameter reconf_width = 64, - parameter device_family = "Cyclone V" -) ( - - //input - input wire mgmt_clk, - input wire mgmt_reset, - - - //conduits - output wire [reconf_width-1:0] reconfig_to_pll, - input wire [reconf_width-1:0] reconfig_from_pll, - - // user data (avalon-MM slave interface) - output wire mgmt_waitrequest, - input wire [5:0] mgmt_address, - input wire mgmt_write, - input wire [31:0] mgmt_writedata -); - localparam mode_WR = 1'b0; - localparam MODE_REG = 6'b000000; - localparam START_REG = 6'b000010; - localparam N_REG = 6'b000011; - localparam M_REG = 6'b000100; - localparam C_COUNTERS_REG = 6'b000101; - //localparam DPS_REG = 6'b000110; // unused - localparam DSM_REG = 6'b000111; - localparam BWCTRL_REG = 6'b001000; - localparam CP_CURRENT_REG = 6'b001001; - //localparam ANY_DPRIO = 6'b100000; // unused - //localparam CNT_BASE = 5'b001010; // unused - //localparam VCO_REG = 6'b011100; // unused - - //C Counters - localparam number_of_counters = 5'd6; - //C counter addresses - localparam C_CNT_0_DIV_ADDR = 5'h00; - localparam C_CNT_0_DIV_ADDR_DPRIO_1 = 5'h11; - localparam C_CNT_0_3_BYPASS_EN_ADDR = 5'h15; - localparam C_CNT_0_3_ODD_DIV_EN_ADDR = 5'h17; - localparam C_CNT_4_17_BYPASS_EN_ADDR = 5'h14; - localparam C_CNT_4_17_ODD_DIV_EN_ADDR = 5'h16; - //N counter addresses - localparam N_CNT_DIV_ADDR = 5'h13; - localparam N_CNT_BYPASS_EN_ADDR = 5'h15; - localparam N_CNT_ODD_DIV_EN_ADDR = 5'h17; - //M counter addresses - localparam M_CNT_DIV_ADDR = 5'h12; - localparam M_CNT_BYPASS_EN_ADDR = 5'h15; - localparam M_CNT_ODD_DIV_EN_ADDR = 5'h17; - - //DSM address - localparam DSM_K_FRACTIONAL_DIVISION_ADDR_0 = 5'h18; - localparam DSM_K_FRACTIONAL_DIVISION_ADDR_1 = 5'h19; - localparam DSM_K_READY_ADDR = 5'h17; - localparam DSM_K_DITHER_ADDR = 5'h17; - localparam DSM_OUT_SEL_ADDR = 6'h30; - - //Other DSM params - localparam DSM_K_READY_BIT_INDEX = 4'd11; - //BWCTRL address - //Bit 0-3 of addr - localparam BWCTRL_ADDR = 6'h30; - //CP_CURRENT address - //Bit 0-2 of addr - localparam CP_CURRENT_ADDR = 6'h31; - - // VCODIV address - localparam VCO_ADDR = 5'h17; - - localparam DPRIO_IDLE = 3'd0, ONE = 3'd1, TWO = 3'd2, THREE = 3'd3, FOUR = 3'd4, - FIVE = 3'd5, SIX = 3'd6, SEVEN = 3'd7, EIGHT = 4'd8, NINE = 4'd9, TEN = 4'd10, - ELEVEN = 4'd11, TWELVE = 4'd12, THIRTEEN = 4'd13, FOURTEEN = 4'd14, DPRIO_DONE = 4'd15; - localparam IDLE = 2'b00, WAIT_ON_LOCK = 2'b01, LOCKED = 2'b10; - - wire clk; - wire reset; - wire gnd; - - wire [5: 0] slave_address; - wire slave_write; - wire [31: 0] slave_writedata; - - wire slave_waitrequest; - reg slave_mode; - - assign clk = mgmt_clk; - - assign slave_address = mgmt_address; - assign slave_write = mgmt_write; - assign slave_writedata = mgmt_writedata; - - // Outputs - assign mgmt_waitrequest = slave_waitrequest; //Read waitrequest asserted in polling mode - - //internal signals - wire locked_orig; - wire locked; - - wire pll_start; - wire pll_start_valid; - - wire pll_start_asserted; - - reg [1:0] current_state; - reg [1:0] next_state; - - reg status;//0=busy, 1=ready - //user_mode_init user_mode_init_inst (clk, reset, dprio_mdio_dis, ser_shift_load); - //declaring the init wires. These will have 0 on them for 64 clk cycles - wire [ 5:0] init_dprio_address; - wire init_dprio_read; - wire [ 1:0] init_dprio_byteen; - wire init_dprio_write; - wire [15:0] init_dprio_writedata; - - wire init_atpgmode; - wire init_mdio_dis; - wire init_scanen; - wire init_ser_shift_load; - wire dprio_init_done; - - //DPRIO output signals after initialization is done - wire dprio_clk; - reg avmm_dprio_write; - reg avmm_dprio_read; - reg [5:0] avmm_dprio_address; - reg [15:0] avmm_dprio_writedata; - reg [1:0] avmm_dprio_byteen; - wire avmm_atpgmode; - wire avmm_mdio_dis; - wire avmm_scanen; - - //Final output wires that are muxed between the init and avmm wires. - wire dprio_init_reset; - wire [5:0] dprio_address /*synthesis keep*/; - wire dprio_read/*synthesis keep*/; - wire [1:0] dprio_byteen/*synthesis keep*/; - wire dprio_write/*synthesis keep*/; - wire [15:0] dprio_writedata/*synthesis keep*/; - wire dprio_mdio_dis/*synthesis keep*/; - wire dprio_ser_shift_load/*synthesis keep*/; - wire dprio_atpgmode/*synthesis keep*/; - wire dprio_scanen/*synthesis keep*/; - - - //other PLL signals for dyn ph shift - wire phase_done/*synthesis keep*/; - wire phase_en/*synthesis keep*/; - wire up_dn/*synthesis keep*/; - wire [4:0] cnt_sel; - - //DPRIO input signals - wire [15:0] dprio_readdata; - - //internal logic signals - //storage registers for user sent data - reg dprio_temp_read_1; - reg dprio_temp_read_2; - reg dprio_start; - wire usr_valid_changes; - reg [3:0] dprio_cur_state; - reg [3:0] dprio_next_state; - reg [15:0] dprio_temp_m_n_c_readdata_1_d; - reg [15:0] dprio_temp_m_n_c_readdata_2_d; - reg [15:0] dprio_temp_m_n_c_readdata_1_q; - reg [15:0] dprio_temp_m_n_c_readdata_2_q; - reg dprio_write_done; - //C counters signals - reg [7:0] usr_c_cnt_lo; - reg [7:0] usr_c_cnt_hi; - reg usr_c_cnt_bypass_en; - reg usr_c_cnt_odd_duty_div_en; - reg temp_c_cnt_bypass_en [0:17]; - reg temp_c_cnt_odd_duty_div_en [0:17]; - reg any_c_cnt_changed; - reg all_c_cnt_done_q; - reg all_c_cnt_done_d; - reg [17:0] c_cnt_changed; - reg [17:0] c_cnt_done_d; - reg [17:0] c_cnt_done_q; - //N counter signals - reg [7:0] usr_n_cnt_lo; - reg [7:0] usr_n_cnt_hi; - reg usr_n_cnt_bypass_en; - reg usr_n_cnt_odd_duty_div_en; - reg n_cnt_changed; - reg n_cnt_done_d; - reg n_cnt_done_q; - //M counter signals - reg [7:0] usr_m_cnt_lo; - reg [7:0] usr_m_cnt_hi; - reg usr_m_cnt_bypass_en; - reg usr_m_cnt_odd_duty_div_en; - reg m_cnt_changed; - reg m_cnt_done_d; - reg m_cnt_done_q; - //dyn phase regs - reg [15:0] usr_num_shifts; - reg [4:0] usr_cnt_sel /*synthesis preserve*/; - reg usr_up_dn; - reg dps_changed; - wire dps_changed_valid; - wire dps_done; - - //DSM Signals - reg [31:0] usr_k_value; - reg dsm_k_changed; - reg dsm_k_done_d; - reg dsm_k_done_q; - reg dsm_k_ready_false_done_d; - //BW signals - reg [3:0] usr_bwctrl_value; - reg bwctrl_changed; - reg bwctrl_done_d; - reg bwctrl_done_q; - //CP signals - reg [2:0] usr_cp_current_value; - reg cp_current_changed; - reg cp_current_done_d; - reg cp_current_done_q; - //VCO signals - reg usr_vco_value; - reg vco_changed; - reg vco_done_d; - reg vco_done_q; - //Manual DPRIO signals - reg manual_dprio_done_q; - reg manual_dprio_done_d; - reg manual_dprio_changed; - reg [5:0] usr_dprio_address; - reg [15:0] usr_dprio_writedata_0; - reg usr_r_w; - //keeping track of which operation happened last - reg [5:0] operation_address; - // Address wires for all C_counter DPRIO registers - // These are outputs of LUTS, changing depending - // on whether PLL_0 or PLL_1 being used - - - //Fitter will tell if FPLL1 is being used - wire fpll_1; - - // MAIN FSM - - // Synchronize locked signal - altera_std_synchronizer #( - .depth(3) - ) altera_std_synchronizer_inst ( - .clk(mgmt_clk), - .reset_n(~mgmt_reset), - .din(locked_orig), - .dout(locked) - ); - - always @(posedge clk) - begin - if (reset) - begin - dprio_cur_state <= DPRIO_IDLE; - current_state <= IDLE; - end - else - begin - current_state <= next_state; - dprio_cur_state <= dprio_next_state; - end - end - - always @(*) - begin - case(current_state) - IDLE: - begin - if (pll_start & !slave_waitrequest & usr_valid_changes) - next_state = WAIT_ON_LOCK; - else - next_state = IDLE; - end - WAIT_ON_LOCK: - begin - if (locked & dps_done & dprio_write_done) // received locked high from PLL - begin - if (slave_mode==mode_WR) //if the mode is waitrequest, then - // goto IDLE state directly - next_state = IDLE; - else - next_state = LOCKED; //otherwise go the locked state - end - else - next_state = WAIT_ON_LOCK; - end - - LOCKED: - begin - next_state = LOCKED; - end - - default: next_state = 2'bxx; - - endcase - end - - - // ask the pll to start reconfig - assign pll_start = (pll_start_asserted & (current_state==IDLE)) ; - assign pll_start_valid = (pll_start & (next_state==WAIT_ON_LOCK)) ; - - - - // WRITE OPERATIONS - assign pll_start_asserted = slave_write & (slave_address == START_REG); - - //reading the mode register to determine what mode the slave will operate - //in. - always @(posedge clk) - begin - if (reset) - slave_mode <= mode_WR; - else if (slave_write & (slave_address == MODE_REG) & !slave_waitrequest) - slave_mode <= slave_writedata[0]; - end - - //record which values user wants to change. - - //reading in the actual values that need to be reconfigged and sending - //them to the PLL - always @(posedge clk) - begin - if (reset) - begin - //reset all regs here - //BW signals reset - usr_bwctrl_value <= 0; - bwctrl_changed <= 0; - bwctrl_done_q <= 0; - //CP signals reset - usr_cp_current_value <= 0; - cp_current_changed <= 0; - cp_current_done_q <= 0; - //VCO signals reset - usr_vco_value <= 0; - vco_changed <= 0; - vco_done_q <= 0; - //DSM signals reset - usr_k_value <= 0; - dsm_k_changed <= 0; - dsm_k_done_q <= 0; - //N counter signals reset - usr_n_cnt_lo <= 0; - usr_n_cnt_hi <= 0; - usr_n_cnt_bypass_en <= 0; - usr_n_cnt_odd_duty_div_en <= 0; - n_cnt_changed <= 0; - n_cnt_done_q <= 0; - //M counter signals reset - usr_m_cnt_lo <= 0; - usr_m_cnt_hi <= 0; - usr_m_cnt_bypass_en <= 0; - usr_m_cnt_odd_duty_div_en <= 0; - m_cnt_changed <= 0; - m_cnt_done_q <= 0; - //C counter signals reset - usr_c_cnt_lo <= 0; - usr_c_cnt_hi <= 0; - usr_c_cnt_bypass_en <= 0; - usr_c_cnt_odd_duty_div_en <= 0; - any_c_cnt_changed <= 0; - all_c_cnt_done_q <= 0; - c_cnt_done_q <= 0; - //generic signals - dprio_start <= 0; - dprio_temp_m_n_c_readdata_1_q <= 0; - dprio_temp_m_n_c_readdata_2_q <= 0; - c_cnt_done_q <= 0; - //DPS signals - usr_up_dn <= 0; - usr_cnt_sel <= 0; - usr_num_shifts <= 0; - dps_changed <= 0; - //manual DPRIO signals - manual_dprio_changed <= 0; - usr_dprio_address <= 0; - usr_dprio_writedata_0 <= 0; - usr_r_w <= 0; - operation_address <= 0; - end - else - begin - if (dprio_temp_read_1) - begin - dprio_temp_m_n_c_readdata_1_q <= dprio_temp_m_n_c_readdata_1_d; - end - if (dprio_temp_read_2) - begin - dprio_temp_m_n_c_readdata_2_q <= dprio_temp_m_n_c_readdata_2_d; - end - if ((dps_done)) dps_changed <= 0; - if (dsm_k_done_d) dsm_k_done_q <= dsm_k_done_d; - if (n_cnt_done_d) n_cnt_done_q <= n_cnt_done_d; - if (m_cnt_done_d) m_cnt_done_q <= m_cnt_done_d; - if (all_c_cnt_done_d) all_c_cnt_done_q <= all_c_cnt_done_d; - if (c_cnt_done_d != 0) c_cnt_done_q <= c_cnt_done_q | c_cnt_done_d; - if (bwctrl_done_d) bwctrl_done_q <= bwctrl_done_d; - if (cp_current_done_d) cp_current_done_q <= cp_current_done_d; - if (vco_done_d) vco_done_q <= vco_done_d; - if (manual_dprio_done_d) manual_dprio_done_q <= manual_dprio_done_d; - - if (dprio_next_state == ONE) - dprio_start <= 0; - if (dprio_write_done) - begin - bwctrl_done_q <= 0; - cp_current_done_q <= 0; - vco_done_q <= 0; - dsm_k_done_q <= 0; - dsm_k_done_q <= 0; - n_cnt_done_q <= 0; - m_cnt_done_q <= 0; - all_c_cnt_done_q <= 0; - c_cnt_done_q <= 0; - dsm_k_changed <= 0; - n_cnt_changed <= 0; - m_cnt_changed <= 0; - any_c_cnt_changed <= 0; - bwctrl_changed <= 0; - cp_current_changed <= 0; - vco_changed <= 0; - manual_dprio_changed <= 0; - manual_dprio_done_q <= 0; - - end - else - begin - dsm_k_changed <= dsm_k_changed; - n_cnt_changed <= n_cnt_changed; - m_cnt_changed <= m_cnt_changed; - any_c_cnt_changed <= any_c_cnt_changed; - manual_dprio_changed <= manual_dprio_changed; - end - - - if(slave_write & !slave_waitrequest) - begin - case(slave_address) - //read in the values here from the user and act on them - DSM_REG: - begin - operation_address <= DSM_REG; - usr_k_value <= slave_writedata[31:0]; - dsm_k_changed <= 1'b1; - dsm_k_done_q <= 0; - dprio_start <= 1'b1; - end - N_REG: - begin - operation_address <= N_REG; - usr_n_cnt_lo <= slave_writedata[7:0]; - usr_n_cnt_hi <= slave_writedata[15:8]; - usr_n_cnt_bypass_en <= slave_writedata[16]; - usr_n_cnt_odd_duty_div_en <= slave_writedata[17]; - n_cnt_changed <= 1'b1; - n_cnt_done_q <= 0; - dprio_start <= 1'b1; - end - M_REG: - begin - operation_address <= M_REG; - usr_m_cnt_lo <= slave_writedata[7:0]; - usr_m_cnt_hi <= slave_writedata[15:8]; - usr_m_cnt_bypass_en <= slave_writedata[16]; - usr_m_cnt_odd_duty_div_en <= slave_writedata[17]; - m_cnt_changed <= 1'b1; - m_cnt_done_q <= 0; - dprio_start <= 1'b1; - end - //DPS_REG: - //begin - // operation_address <= DPS_REG; - // usr_num_shifts <= slave_writedata[15:0]; - // usr_up_dn <= slave_writedata[21]; - // dps_changed <= 1; - //end - C_COUNTERS_REG: - begin - operation_address <= C_COUNTERS_REG; - usr_c_cnt_lo <= slave_writedata[7:0]; - usr_c_cnt_hi <= slave_writedata[15:8]; - usr_c_cnt_bypass_en <= slave_writedata[16]; - usr_c_cnt_odd_duty_div_en <= slave_writedata[17]; - any_c_cnt_changed <= 1'b1; - all_c_cnt_done_q <= 0; - dprio_start <= 1'b1; - end - BWCTRL_REG: - begin - usr_bwctrl_value <= slave_writedata[3:0]; - bwctrl_changed <= 1'b1; - bwctrl_done_q <= 0; - dprio_start <= 1'b1; - operation_address <= BWCTRL_REG; - end - CP_CURRENT_REG: - begin - usr_cp_current_value <= slave_writedata[2:0]; - cp_current_changed <= 1'b1; - cp_current_done_q <= 0; - dprio_start <= 1'b1; - operation_address <= CP_CURRENT_REG; - end - //VCO_REG: - //begin - // usr_vco_value <= slave_writedata[0]; - // vco_changed <= 1'b1; - // vco_done_q <= 0; - // dprio_start <= 1'b1; - // operation_address <= VCO_REG; - //end - //ANY_DPRIO: - //begin - // operation_address <= ANY_DPRIO; - // manual_dprio_changed <= 1'b1; - // usr_dprio_address <= slave_writedata[5:0]; - // usr_dprio_writedata_0 <= slave_writedata[21:6]; - // usr_r_w <= slave_writedata[22]; - // manual_dprio_done_q <= 0; - // dprio_start <= 1'b1; - //end - endcase - end - end - end - //C Counter assigning values to the 2-d array of values for each C counter - - reg [4:0] j; - always @(posedge clk) - begin - - if (reset) - begin - c_cnt_changed[17:0] <= 0; - for (j = 0; j < number_of_counters; j = j + 1'b1) - begin : c_cnt_reset - temp_c_cnt_bypass_en[j] <= 0; - temp_c_cnt_odd_duty_div_en[j] <= 0; - end - end - else - begin - if (dprio_write_done) - begin - c_cnt_changed <= 0; - end - if (any_c_cnt_changed && (operation_address == C_COUNTERS_REG)) - begin - temp_c_cnt_bypass_en [5] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [5] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [5] <= 1'b1; - end - end - end - - - //logic to handle which writes the user indicated and wants to start. - assign usr_valid_changes =dsm_k_changed| any_c_cnt_changed |n_cnt_changed | m_cnt_changed | dps_changed_valid |manual_dprio_changed |cp_current_changed|bwctrl_changed|vco_changed; - - - //start the reconfig operations by writing to the DPRIO - reg break_loop; - reg [4:0] i; - always @(*) - begin - dprio_temp_read_1 = 0; - dprio_temp_read_2 = 0; - dprio_temp_m_n_c_readdata_1_d = 0; - dprio_temp_m_n_c_readdata_2_d = 0; - break_loop = 0; - dprio_next_state = DPRIO_IDLE; - avmm_dprio_write = 0; - avmm_dprio_read = 0; - avmm_dprio_address = 0; - avmm_dprio_writedata = 0; - avmm_dprio_byteen = 0; - dprio_write_done = 1; - manual_dprio_done_d = 0; - n_cnt_done_d = 0; - dsm_k_done_d = 0; - dsm_k_ready_false_done_d = 0; - m_cnt_done_d = 0; - c_cnt_done_d[17:0] = 0; - all_c_cnt_done_d = 0; - bwctrl_done_d = 0; - cp_current_done_d = 0; - vco_done_d = 0; - i = 0; - - // Deassert dprio_write_done so it doesn't reset mif_reg_asserted (toggled writes) - if (dprio_start) - dprio_write_done = 0; - - if (current_state == WAIT_ON_LOCK) - begin - case (dprio_cur_state) - ONE: - begin - if (n_cnt_changed & !n_cnt_done_q) - begin - dprio_write_done = 0; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - dprio_next_state = TWO; - avmm_dprio_address = N_CNT_DIV_ADDR; - avmm_dprio_writedata[7:0] = usr_n_cnt_lo; - avmm_dprio_writedata[15:8] = usr_n_cnt_hi; - end - else if (m_cnt_changed & !m_cnt_done_q) - begin - dprio_write_done = 0; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - dprio_next_state = TWO; - avmm_dprio_address = M_CNT_DIV_ADDR; - avmm_dprio_writedata[7:0] = usr_m_cnt_lo; - avmm_dprio_writedata[15:8] = usr_m_cnt_hi; - end - else if (any_c_cnt_changed & !all_c_cnt_done_q) - begin - - for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) - begin : c_cnt_write_hilo - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - dprio_write_done = 0; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - dprio_next_state = TWO; - if (fpll_1) avmm_dprio_address = C_CNT_0_DIV_ADDR + C_CNT_0_DIV_ADDR_DPRIO_1 - i; - else avmm_dprio_address = C_CNT_0_DIV_ADDR + i; - avmm_dprio_writedata[7:0] = usr_c_cnt_lo; - avmm_dprio_writedata[15:8] = usr_c_cnt_hi; - //To break from the loop, since only one counter - //is addressed at a time - break_loop = 1'b1; - end - end - end - else if (dsm_k_changed & !dsm_k_done_q) - begin - dprio_write_done = 0; - avmm_dprio_write = 0; - dprio_next_state = TWO; - end - else if (bwctrl_changed & !bwctrl_done_q) - begin - dprio_write_done = 0; - avmm_dprio_write = 0; - dprio_next_state = TWO; - end - else if (cp_current_changed & !cp_current_done_q) - begin - dprio_write_done = 0; - avmm_dprio_write = 0; - dprio_next_state = TWO; - end - else if (vco_changed & !vco_done_q) - begin - dprio_write_done = 0; - avmm_dprio_write = 0; - dprio_next_state = TWO; - end - else if (manual_dprio_changed & !manual_dprio_done_q) - begin - dprio_write_done = 0; - avmm_dprio_byteen = 2'b11; - dprio_next_state = TWO; - avmm_dprio_write = usr_r_w; - avmm_dprio_address = usr_dprio_address; - avmm_dprio_writedata[15:0] = usr_dprio_writedata_0; - end - else dprio_next_state = DPRIO_IDLE; - end - - TWO: - begin - //handle reading the two setting bits on n_cnt, then - //writing them back while preserving other bits. - //Issue two consecutive reads then wait; readLatency=3 - dprio_write_done = 0; - dprio_next_state = THREE; - avmm_dprio_byteen = 2'b11; - avmm_dprio_read = 1'b1; - if (n_cnt_changed & !n_cnt_done_q) - begin - avmm_dprio_address = N_CNT_BYPASS_EN_ADDR; - end - else if (m_cnt_changed & !m_cnt_done_q) - begin - avmm_dprio_address = M_CNT_BYPASS_EN_ADDR; - end - - else if (any_c_cnt_changed & !all_c_cnt_done_q) - begin - for (i = 5; (i < number_of_counters) & !break_loop; i = i + 1'b1) - begin : c_cnt_read_bypass - if (fpll_1) - begin - if (i > 13) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; - break_loop = 1'b1; - end - end - end - else - begin - if (i < 4) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; - break_loop = 1'b1; - end - end - end - end - end - //reading the K ready 16 bit word. Need to write 0 to it - //afterwards to indicate that K has not been done writing - else if (dsm_k_changed & !dsm_k_done_q) - begin - avmm_dprio_address = DSM_K_READY_ADDR; - dprio_next_state = FOUR; - end - else if (bwctrl_changed & !bwctrl_done_q) - begin - avmm_dprio_address = BWCTRL_ADDR; - dprio_next_state = FOUR; - end - else if (cp_current_changed & !cp_current_done_q) - begin - avmm_dprio_address = CP_CURRENT_ADDR; - dprio_next_state = FOUR; - end - else if (vco_changed & !vco_done_q) - begin - avmm_dprio_address = VCO_ADDR; - dprio_next_state = FOUR; - end - else if (manual_dprio_changed & !manual_dprio_done_q) - begin - avmm_dprio_read = ~usr_r_w; - avmm_dprio_address = usr_dprio_address; - dprio_next_state = DPRIO_DONE; - end - else dprio_next_state = DPRIO_IDLE; - end - THREE: - begin - dprio_write_done = 0; - avmm_dprio_byteen = 2'b11; - avmm_dprio_read = 1'b1; - dprio_next_state = FOUR; - if (n_cnt_changed & !n_cnt_done_q) - begin - avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR; - end - else if (m_cnt_changed & !m_cnt_done_q) - begin - avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR; - end - else if (any_c_cnt_changed & !all_c_cnt_done_q) - begin - for (i = 5; (i < number_of_counters) & !break_loop; i = i + 1'b1) - begin : c_cnt_read_odd_div - if (fpll_1) - begin - if (i > 13) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; - break_loop = 1'b1; - end - end - end - else - begin - if (i < 4) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; - break_loop = 1'b1; - end - end - end - end - end - else dprio_next_state = DPRIO_IDLE; - end - FOUR: - begin - dprio_temp_read_1 = 1'b1; - dprio_write_done = 0; - if (vco_changed|cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed) - begin - dprio_temp_m_n_c_readdata_1_d = dprio_readdata; - dprio_next_state = FIVE; - end - else dprio_next_state = DPRIO_IDLE; - end - FIVE: - begin - dprio_write_done = 0; - dprio_temp_read_2 = 1'b1; - if (vco_changed|cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed) - begin - //this is where DSM ready value comes. - //Need to store in a register to be used later - dprio_temp_m_n_c_readdata_2_d = dprio_readdata; - dprio_next_state = SIX; - end - else dprio_next_state = DPRIO_IDLE; - end - SIX: - begin - dprio_write_done = 0; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - dprio_next_state = SEVEN; - avmm_dprio_writedata = dprio_temp_m_n_c_readdata_1_q; - if (n_cnt_changed & !n_cnt_done_q) - begin - avmm_dprio_address = N_CNT_BYPASS_EN_ADDR; - avmm_dprio_writedata[5] = usr_n_cnt_bypass_en; - end - else if (m_cnt_changed & !m_cnt_done_q) - begin - avmm_dprio_address = M_CNT_BYPASS_EN_ADDR; - avmm_dprio_writedata[4] = usr_m_cnt_bypass_en; - end - else if (any_c_cnt_changed & !all_c_cnt_done_q) - begin - for (i = 5; (i < number_of_counters) & !break_loop; i = i + 1'b1) - begin : c_cnt_write_bypass - if (fpll_1) - begin - if (i > 13) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; - avmm_dprio_writedata[i-14] = temp_c_cnt_bypass_en[i]; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; - avmm_dprio_writedata[i] = temp_c_cnt_bypass_en[i]; - break_loop = 1'b1; - end - end - end - else - begin - if (i < 4) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; - avmm_dprio_writedata[3-i] = temp_c_cnt_bypass_en[i]; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; - avmm_dprio_writedata[17-i] = temp_c_cnt_bypass_en[i]; - break_loop = 1'b1; - end - end - end - end - end - else if (dsm_k_changed & !dsm_k_done_q) - begin - avmm_dprio_write = 0; - end - else if (bwctrl_changed & !bwctrl_done_q) - begin - avmm_dprio_write = 0; - end - else if (cp_current_changed & !cp_current_done_q) - begin - avmm_dprio_write = 0; - end - else if (vco_changed & !vco_done_q) - begin - avmm_dprio_write = 0; - end - else dprio_next_state = DPRIO_IDLE; - end - SEVEN: - begin - dprio_write_done = 0; - dprio_next_state = EIGHT; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q; - if (n_cnt_changed & !n_cnt_done_q) - begin - avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR; - avmm_dprio_writedata[5] = usr_n_cnt_odd_duty_div_en; - n_cnt_done_d = 1'b1; - end - else if (m_cnt_changed & !m_cnt_done_q) - begin - avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR; - avmm_dprio_writedata[4] = usr_m_cnt_odd_duty_div_en; - m_cnt_done_d = 1'b1; - end - - else if (any_c_cnt_changed & !all_c_cnt_done_q) - begin - for (i = 5; (i < number_of_counters) & !break_loop; i = i + 1'b1) - begin : c_cnt_write_odd_div - if (fpll_1) - begin - if (i > 13) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; - avmm_dprio_writedata[i-14] = temp_c_cnt_odd_duty_div_en[i]; - c_cnt_done_d[i] = 1'b1; - //have to OR the signals to prevent - //overwriting of previous dones - c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; - avmm_dprio_writedata[i] = temp_c_cnt_odd_duty_div_en[i]; - c_cnt_done_d[i] = 1'b1; - c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; - break_loop = 1'b1; - end - end - end - else - begin - if (i < 4) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; - avmm_dprio_writedata[3-i] = temp_c_cnt_odd_duty_div_en[i]; - c_cnt_done_d[i] = 1'b1; - //have to OR the signals to prevent - //overwriting of previous dones - c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; - avmm_dprio_writedata[17-i] = temp_c_cnt_odd_duty_div_en[i]; - c_cnt_done_d[i] = 1'b1; - c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; - break_loop = 1'b1; - end - end - end - end - end - else if (dsm_k_changed & !dsm_k_done_q) - begin - avmm_dprio_address = DSM_K_READY_ADDR; - avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b0; - dsm_k_ready_false_done_d = 1'b1; - end - else if (bwctrl_changed & !bwctrl_done_q) - begin - avmm_dprio_address = BWCTRL_ADDR; - avmm_dprio_writedata[3:0] = usr_bwctrl_value; - bwctrl_done_d = 1'b1; - end - else if (cp_current_changed & !cp_current_done_q) - begin - avmm_dprio_address = CP_CURRENT_ADDR; - avmm_dprio_writedata[2:0] = usr_cp_current_value; - cp_current_done_d = 1'b1; - end - else if (vco_changed & !vco_done_q) - begin - avmm_dprio_address = VCO_ADDR; - avmm_dprio_writedata[8] = usr_vco_value; - vco_done_d = 1'b1; - end - - - //if all C_cnt that were changed are done, then assert all_c_cnt_done - if (c_cnt_done_d == c_cnt_changed) - all_c_cnt_done_d = 1'b1; - if (n_cnt_changed & n_cnt_done_d) - dprio_next_state = DPRIO_DONE; - if (any_c_cnt_changed & !all_c_cnt_done_d & !all_c_cnt_done_q) - dprio_next_state = ONE; - else if (m_cnt_changed & !m_cnt_done_d & !m_cnt_done_q) - dprio_next_state = ONE; - else if (dsm_k_changed & !dsm_k_ready_false_done_d) - dprio_next_state = TWO; - else if (dsm_k_changed & !dsm_k_done_q) - dprio_next_state = EIGHT; - else if (bwctrl_changed & !bwctrl_done_d) - dprio_next_state = TWO; - else if (cp_current_changed & !cp_current_done_d) - dprio_next_state = TWO; - else if (vco_changed & !vco_done_d) - dprio_next_state = TWO; - else - begin - dprio_next_state = DPRIO_DONE; - dprio_write_done = 1'b1; - end - end - //finish the rest of the DSM reads/writes - //writing k value, writing k_ready to 1. - EIGHT: - begin - dprio_write_done = 0; - dprio_next_state = NINE; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - if (dsm_k_changed & !dsm_k_done_q) - begin - avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_0; - avmm_dprio_writedata[15:0] = usr_k_value[15:0]; - end - end - NINE: - begin - dprio_write_done = 0; - dprio_next_state = TEN; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - if (dsm_k_changed & !dsm_k_done_q) - begin - avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_1; - avmm_dprio_writedata[15:0] = usr_k_value[31:16]; - end - end - TEN: - begin - dprio_write_done = 0; - dprio_next_state = ONE; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - if (dsm_k_changed & !dsm_k_done_q) - begin - avmm_dprio_address = DSM_K_READY_ADDR; - //already have the readdata for DSM_K_READY_ADDR since we read it - //earlier. Just reuse here - avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q; - avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b1; - dsm_k_done_d = 1'b1; - end - end - DPRIO_DONE: - begin - dprio_write_done = 1'b1; - if (dprio_start) dprio_next_state = DPRIO_IDLE; - else dprio_next_state = DPRIO_DONE; - end - DPRIO_IDLE: - begin - if (dprio_start) dprio_next_state = ONE; - else dprio_next_state = DPRIO_IDLE; - end - default: dprio_next_state = 4'bxxxx; - endcase - end - - end - - - //assert the waitreq signal according to the state of the slave - assign slave_waitrequest = (slave_mode==mode_WR) ? ((locked === 1'b1) ? (((current_state==WAIT_ON_LOCK) & !dprio_write_done) | !dps_done |reset|!dprio_init_done) : 1'b1) : 1'b0; - - - dyn_phase_shift dyn_phase_shift_inst ( - .clk(clk), - .reset(reset), - .phase_done(phase_done), - .pll_start_valid(pll_start_valid), - .dps_changed(dps_changed), - .dps_changed_valid(dps_changed_valid), - .dprio_write_done(dprio_write_done), - .usr_num_shifts(usr_num_shifts), - .usr_cnt_sel(usr_cnt_sel), - .usr_up_dn(usr_up_dn), - .locked(locked), - .dps_done(dps_done), - .phase_en(phase_en), - .up_dn(up_dn), - .cnt_sel(cnt_sel)); - defparam dyn_phase_shift_inst.device_family = device_family; - - assign dprio_clk = clk; - self_reset self_reset_inst (mgmt_reset, clk, reset, dprio_init_reset); - - dprio_mux dprio_mux_inst ( - .init_dprio_address(init_dprio_address), - .init_dprio_read(init_dprio_read), - .init_dprio_byteen(init_dprio_byteen), - .init_dprio_write(init_dprio_write), - .init_dprio_writedata(init_dprio_writedata), - - - .init_atpgmode(init_atpgmode), - .init_mdio_dis(init_mdio_dis), - .init_scanen(init_scanen), - .init_ser_shift_load(init_ser_shift_load), - .dprio_init_done(dprio_init_done), - - // Inputs from avmm master - .avmm_dprio_address(avmm_dprio_address), - .avmm_dprio_read(avmm_dprio_read), - .avmm_dprio_byteen(avmm_dprio_byteen), - .avmm_dprio_write(avmm_dprio_write), - .avmm_dprio_writedata(avmm_dprio_writedata), - - .avmm_atpgmode(avmm_atpgmode), - .avmm_mdio_dis(avmm_mdio_dis), - .avmm_scanen(avmm_scanen), - - // Outputs to fpll - .dprio_address(dprio_address), - .dprio_read(dprio_read), - .dprio_byteen(dprio_byteen), - .dprio_write(dprio_write), - .dprio_writedata(dprio_writedata), - - .atpgmode(dprio_atpgmode), - .mdio_dis(dprio_mdio_dis), - .scanen(dprio_scanen), - .ser_shift_load(dprio_ser_shift_load) - ); - - - fpll_dprio_init fpll_dprio_init_inst ( - .clk(clk), - .reset_n(~reset), - .locked(locked), - - //outputs - .dprio_address(init_dprio_address), - .dprio_read(init_dprio_read), - .dprio_byteen(init_dprio_byteen), - .dprio_write(init_dprio_write), - .dprio_writedata(init_dprio_writedata), - - .atpgmode(init_atpgmode), - .mdio_dis(init_mdio_dis), - .scanen(init_scanen), - .ser_shift_load(init_ser_shift_load), - .dprio_init_done(dprio_init_done)); - - //address luts, to be reconfigged by the Fitter - //FPLL_1 or 0 address lut - generic_lcell_comb lcell_fpll_0_1 ( - .dataa(1'b0), - .combout (fpll_1)); - defparam lcell_fpll_0_1.lut_mask = 64'hAAAAAAAAAAAAAAAA; - defparam lcell_fpll_0_1.dont_touch = "on"; - defparam lcell_fpll_0_1.family = device_family; - - - wire dprio_read_combout; - generic_lcell_comb lcell_dprio_read ( - .dataa(fpll_1), - .datab(dprio_read), - .datac(1'b0), - .datad(1'b0), - .datae(1'b0), - .dataf(1'b0), - .combout (dprio_read_combout)); - defparam lcell_dprio_read.lut_mask = 64'hCCCCCCCCCCCCCCCC; - defparam lcell_dprio_read.dont_touch = "on"; - defparam lcell_dprio_read.family = device_family; - - - - - - //assign reconfig_to_pll signals - assign reconfig_to_pll[0] = dprio_clk; - assign reconfig_to_pll[1] = ~dprio_init_reset; - assign reconfig_to_pll[2] = dprio_write; - assign reconfig_to_pll[3] = dprio_read_combout; - assign reconfig_to_pll[9:4] = dprio_address; - assign reconfig_to_pll[25:10] = dprio_writedata; - assign reconfig_to_pll[27:26] = dprio_byteen; - assign reconfig_to_pll[28] = dprio_ser_shift_load; - assign reconfig_to_pll[29] = dprio_mdio_dis; - assign reconfig_to_pll[30] = phase_en; - assign reconfig_to_pll[31] = up_dn; - assign reconfig_to_pll[36:32] = cnt_sel; - assign reconfig_to_pll[37] = dprio_scanen; - assign reconfig_to_pll[38] = dprio_atpgmode; - //assign reconfig_to_pll[40:37] = clken; - assign reconfig_to_pll[63:39] = 0; - - //assign reconfig_from_pll signals - assign dprio_readdata = reconfig_from_pll [15:0]; - assign locked_orig = reconfig_from_pll [16]; - assign phase_done = reconfig_from_pll [17]; - -endmodule diff --git a/sys/pll_hdmi.13.qip b/sys/pll_hdmi.13.qip deleted file mode 100644 index 76def89..0000000 --- a/sys/pll_hdmi.13.qip +++ /dev/null @@ -1,17 +0,0 @@ -set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll" -set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1" -set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim" -set_global_assignment -library "pll_hdmi" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi.cmp"] -set_global_assignment -name SYNTHESIS_ONLY_QIP ON - -set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"] -set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"] - -set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" -set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" -set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" -set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" - -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim" diff --git a/sys/pll_hdmi.qip b/sys/pll_hdmi.qip deleted file mode 100644 index be34aeb..0000000 --- a/sys/pll_hdmi.qip +++ /dev/null @@ -1,483 +0,0 @@ -set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll" -set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_VERSION "17.0" -set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim" -set_global_assignment -library "pll_hdmi" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi.cmp"] -set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" -set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" -set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_QSYS_MODE "UNKNOWN" -set_global_assignment -name SYNTHESIS_ONLY_QIP ON -set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_NAME "cGxsX2hkbWk=" -set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA==" -set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_VERSION "MTcuMA==" -set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_NAME "cGxsX2hkbWlfMDAwMg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_VERSION "MTcuMA==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZyYWN0aW9uYWxfY291dA==::MzI=::cGxsX2ZyYWN0aW9uYWxfY291dA==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::cGxsX2RzbV9vdXRfc2Vs" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::MQ==::TnVtYmVyIE9mIENsb2Nrcw==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::MQ==::bnVtYmVyX29mX2Nsb2Nrcw==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MTQ4LjU=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MzkwODQyMDE1Mw==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::Mw==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::NjUuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MjcuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MTQ4LjUwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::dHJ1ZQ==::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::Q3ljbG9uZSBW::UExMIFRZUEU=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::UmVjb25maWd1cmFibGU=::UExMIFNVQlRZUEU=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfaGlfZGl2::NA==::bV9jbnRfaGlfZGl2" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfbG9fZGl2::NA==::bV9jbnRfbG9fZGl2" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfaGlfZGl2::MjU2::bl9jbnRfaGlfZGl2" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfbG9fZGl2::MjU2::bl9jbnRfbG9fZGl2" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfYnlwYXNzX2Vu::ZmFsc2U=::bV9jbnRfYnlwYXNzX2Vu" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfYnlwYXNzX2Vu::dHJ1ZQ==::bl9jbnRfYnlwYXNzX2Vu" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfb2RkX2Rpdl9kdXR5X2Vu::ZmFsc2U=::bV9jbnRfb2RkX2Rpdl9kdXR5X2Vu" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfb2RkX2Rpdl9kdXR5X2Vu::ZmFsc2U=::bl9jbnRfb2RkX2Rpdl9kdXR5X2Vu" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MA==::Mg==::Y19jbnRfaGlfZGl2MA==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MA==::MQ==::Y19jbnRfbG9fZGl2MA==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDA=::MQ==::Y19jbnRfcHJzdDA=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qw::MA==::Y19jbnRfcGhfbXV4X3Byc3Qw" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMA==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMA==::ZmFsc2U=::Y19jbnRfYnlwYXNzX2VuMA==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMA==::dHJ1ZQ==::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMA==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MQ==::MQ==::Y19jbnRfaGlfZGl2MQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MQ==::MQ==::Y19jbnRfbG9fZGl2MQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE=::MQ==::Y19jbnRfcHJzdDE=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qx::MA==::Y19jbnRfcGhfbXV4X3Byc3Qx" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMQ==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Mg==::MQ==::Y19jbnRfaGlfZGl2Mg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Mg==::MQ==::Y19jbnRfbG9fZGl2Mg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDI=::MQ==::Y19jbnRfcHJzdDI=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qy::MA==::Y19jbnRfcGhfbXV4X3Byc3Qy" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMg==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMg==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMg==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Mw==::MQ==::Y19jbnRfaGlfZGl2Mw==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Mw==::MQ==::Y19jbnRfbG9fZGl2Mw==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDM=::MQ==::Y19jbnRfcHJzdDM=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qz::MA==::Y19jbnRfcGhfbXV4X3Byc3Qz" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMw==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMw==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMw==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMw==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMw==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMw==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2NA==::MQ==::Y19jbnRfaGlfZGl2NA==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2NA==::MQ==::Y19jbnRfbG9fZGl2NA==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDQ=::MQ==::Y19jbnRfcHJzdDQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q0::MA==::Y19jbnRfcGhfbXV4X3Byc3Q0" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNA==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNA==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNA==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNA==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNA==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2NQ==::MQ==::Y19jbnRfaGlfZGl2NQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2NQ==::MQ==::Y19jbnRfbG9fZGl2NQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDU=::MQ==::Y19jbnRfcHJzdDU=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q1::MA==::Y19jbnRfcGhfbXV4X3Byc3Q1" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNQ==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Ng==::MQ==::Y19jbnRfaGlfZGl2Ng==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Ng==::MQ==::Y19jbnRfbG9fZGl2Ng==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDY=::MQ==::Y19jbnRfcHJzdDY=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q2::MA==::Y19jbnRfcGhfbXV4X3Byc3Q2" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNg==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNg==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNg==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Nw==::MQ==::Y19jbnRfaGlfZGl2Nw==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Nw==::MQ==::Y19jbnRfbG9fZGl2Nw==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDc=::MQ==::Y19jbnRfcHJzdDc=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q3::MA==::Y19jbnRfcGhfbXV4X3Byc3Q3" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNw==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNw==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNw==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNw==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNw==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNw==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2OA==::MQ==::Y19jbnRfaGlfZGl2OA==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2OA==::MQ==::Y19jbnRfbG9fZGl2OA==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDg=::MQ==::Y19jbnRfcHJzdDg=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q4::MA==::Y19jbnRfcGhfbXV4X3Byc3Q4" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjOA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjOA==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuOA==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuOA==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOA==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOA==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2OQ==::MQ==::Y19jbnRfaGlfZGl2OQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2OQ==::MQ==::Y19jbnRfbG9fZGl2OQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDk=::MQ==::Y19jbnRfcHJzdDk=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q5::MA==::Y19jbnRfcGhfbXV4X3Byc3Q5" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjOQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjOQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuOQ==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuOQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTA=::MQ==::Y19jbnRfaGlfZGl2MTA=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTA=::MQ==::Y19jbnRfbG9fZGl2MTA=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEw::MQ==::Y19jbnRfcHJzdDEw" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMA==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMA==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTA=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTA=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTA=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTA=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTA=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTA=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTE=::MQ==::Y19jbnRfaGlfZGl2MTE=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTE=::MQ==::Y19jbnRfbG9fZGl2MTE=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEx::MQ==::Y19jbnRfcHJzdDEx" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMQ==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTE=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTE=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTE=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTE=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTE=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTE=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTI=::MQ==::Y19jbnRfaGlfZGl2MTI=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTI=::MQ==::Y19jbnRfbG9fZGl2MTI=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEy::MQ==::Y19jbnRfcHJzdDEy" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMg==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTI=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTI=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTI=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTI=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTI=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTI=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTM=::MQ==::Y19jbnRfaGlfZGl2MTM=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTM=::MQ==::Y19jbnRfbG9fZGl2MTM=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEz::MQ==::Y19jbnRfcHJzdDEz" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMw==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMw==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTM=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTM=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTM=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTM=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTM=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTM=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTQ=::MQ==::Y19jbnRfaGlfZGl2MTQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTQ=::MQ==::Y19jbnRfbG9fZGl2MTQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE0::MQ==::Y19jbnRfcHJzdDE0" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNA==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNA==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTQ=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTQ=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTQ=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTU=::MQ==::Y19jbnRfaGlfZGl2MTU=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTU=::MQ==::Y19jbnRfbG9fZGl2MTU=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE1::MQ==::Y19jbnRfcHJzdDE1" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNQ==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTU=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTU=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTU=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTU=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTU=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTU=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTY=::MQ==::Y19jbnRfaGlfZGl2MTY=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTY=::MQ==::Y19jbnRfbG9fZGl2MTY=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE2::MQ==::Y19jbnRfcHJzdDE2" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNg==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNg==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTY=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTY=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTY=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTY=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTY=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTY=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTc=::MQ==::Y19jbnRfaGlfZGl2MTc=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTc=::MQ==::Y19jbnRfbG9fZGl2MTc=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE3::MQ==::Y19jbnRfcHJzdDE3" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNw==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNw==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTc=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTc=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTc=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTc=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTc=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTc=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3Zjb19kaXY=::Mg==::cGxsX3Zjb19kaXY=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2NwX2N1cnJlbnQ=::MjA=::cGxsX2NwX2N1cnJlbnQ=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2J3Y3RybA==::NDAwMA==::cGxsX2J3Y3RybA==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX291dHB1dF9jbGtfZnJlcXVlbmN5::NDQ1LjQ5OTk5OSBNSHo=::cGxsX291dHB1dF9jbGtfZnJlcXVlbmN5" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZyYWN0aW9uYWxfZGl2aXNpb24=::MzkwODQyMDE1Mw==::cGxsX2ZyYWN0aW9uYWxfZGl2aXNpb24=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bWltaWNfZmJjbGtfdHlwZQ==::bm9uZQ==::bWltaWNfZmJjbGtfdHlwZQ==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZiY2xrX211eF8x::Z2xi::cGxsX2ZiY2xrX211eF8x" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZiY2xrX211eF8y::bV9jbnQ=::cGxsX2ZiY2xrX211eF8y" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX21fY250X2luX3NyYw==::cGhfbXV4X2Nsaw==::cGxsX21fY250X2luX3NyYw==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3NsZl9yc3Q=::dHJ1ZQ==::cGxsX3NsZl9yc3Q=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NCw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSwyLDEsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwyLDIwLDQwMDAsNDQ1LjQ5OTk5OSBNSHosMzkwODQyMDE1Myxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw==" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw=" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw=" - -set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"] -set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"] -set_global_assignment -library "pll_hdmi" -name QIP_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.qip"] - -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "17.0" -set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim" diff --git a/sys/pll_hdmi.v b/sys/pll_hdmi.v deleted file mode 100644 index 0cefd25..0000000 --- a/sys/pll_hdmi.v +++ /dev/null @@ -1,256 +0,0 @@ -// megafunction wizard: %Altera PLL v17.0% -// GENERATION: XML -// pll_hdmi.v - -// Generated using ACDS version 17.0 598 - -`timescale 1 ps / 1 ps -module pll_hdmi ( - input wire refclk, // refclk.clk - input wire rst, // reset.reset - output wire outclk_0, // outclk0.clk - input wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll - output wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll - ); - - pll_hdmi_0002 pll_hdmi_inst ( - .refclk (refclk), // refclk.clk - .rst (rst), // reset.reset - .outclk_0 (outclk_0), // outclk0.clk - .reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll - .reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll - .locked () // (terminated) - ); - -endmodule -// Retrieval info: -// -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// IPFS_FILES : pll_hdmi.vo -// RELATED_FILES: pll_hdmi.v, pll_hdmi_0002.v diff --git a/sys/pll_hdmi/pll_hdmi_0002.qip b/sys/pll_hdmi/pll_hdmi_0002.qip deleted file mode 100644 index 3cb7073..0000000 --- a/sys/pll_hdmi/pll_hdmi_0002.qip +++ /dev/null @@ -1,2 +0,0 @@ -set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" -set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" diff --git a/sys/pll_hdmi/pll_hdmi_0002.v b/sys/pll_hdmi/pll_hdmi_0002.v deleted file mode 100644 index 9347c76..0000000 --- a/sys/pll_hdmi/pll_hdmi_0002.v +++ /dev/null @@ -1,241 +0,0 @@ -`timescale 1ns/10ps -module pll_hdmi_0002( - - // interface 'refclk' - input wire refclk, - - // interface 'reset' - input wire rst, - - // interface 'outclk0' - output wire outclk_0, - - // interface 'locked' - output wire locked, - - // interface 'reconfig_to_pll' - input wire [63:0] reconfig_to_pll, - - // interface 'reconfig_from_pll' - output wire [63:0] reconfig_from_pll -); - - altera_pll #( - .fractional_vco_multiplier("true"), - .reference_clock_frequency("50.0 MHz"), - .pll_fractional_cout(32), - .pll_dsm_out_sel("1st_order"), - .operation_mode("direct"), - .number_of_clocks(1), - .output_clock_frequency0("148.500000 MHz"), - .phase_shift0("0 ps"), - .duty_cycle0(50), - .output_clock_frequency1("0 MHz"), - .phase_shift1("0 ps"), - .duty_cycle1(50), - .output_clock_frequency2("0 MHz"), - .phase_shift2("0 ps"), - .duty_cycle2(50), - .output_clock_frequency3("0 MHz"), - .phase_shift3("0 ps"), - .duty_cycle3(50), - .output_clock_frequency4("0 MHz"), - .phase_shift4("0 ps"), - .duty_cycle4(50), - .output_clock_frequency5("0 MHz"), - .phase_shift5("0 ps"), - .duty_cycle5(50), - .output_clock_frequency6("0 MHz"), - .phase_shift6("0 ps"), - .duty_cycle6(50), - .output_clock_frequency7("0 MHz"), - .phase_shift7("0 ps"), - .duty_cycle7(50), - .output_clock_frequency8("0 MHz"), - .phase_shift8("0 ps"), - .duty_cycle8(50), - .output_clock_frequency9("0 MHz"), - .phase_shift9("0 ps"), - .duty_cycle9(50), - .output_clock_frequency10("0 MHz"), - .phase_shift10("0 ps"), - .duty_cycle10(50), - .output_clock_frequency11("0 MHz"), - .phase_shift11("0 ps"), - .duty_cycle11(50), - .output_clock_frequency12("0 MHz"), - .phase_shift12("0 ps"), - .duty_cycle12(50), - .output_clock_frequency13("0 MHz"), - .phase_shift13("0 ps"), - .duty_cycle13(50), - .output_clock_frequency14("0 MHz"), - .phase_shift14("0 ps"), - .duty_cycle14(50), - .output_clock_frequency15("0 MHz"), - .phase_shift15("0 ps"), - .duty_cycle15(50), - .output_clock_frequency16("0 MHz"), - .phase_shift16("0 ps"), - .duty_cycle16(50), - .output_clock_frequency17("0 MHz"), - .phase_shift17("0 ps"), - .duty_cycle17(50), - .pll_type("Cyclone V"), - .pll_subtype("Reconfigurable"), - .m_cnt_hi_div(4), - .m_cnt_lo_div(4), - .n_cnt_hi_div(256), - .n_cnt_lo_div(256), - .m_cnt_bypass_en("false"), - .n_cnt_bypass_en("true"), - .m_cnt_odd_div_duty_en("false"), - .n_cnt_odd_div_duty_en("false"), - .c_cnt_hi_div0(2), - .c_cnt_lo_div0(1), - .c_cnt_prst0(1), - .c_cnt_ph_mux_prst0(0), - .c_cnt_in_src0("ph_mux_clk"), - .c_cnt_bypass_en0("false"), - .c_cnt_odd_div_duty_en0("true"), - .c_cnt_hi_div1(1), - .c_cnt_lo_div1(1), - .c_cnt_prst1(1), - .c_cnt_ph_mux_prst1(0), - .c_cnt_in_src1("ph_mux_clk"), - .c_cnt_bypass_en1("true"), - .c_cnt_odd_div_duty_en1("false"), - .c_cnt_hi_div2(1), - .c_cnt_lo_div2(1), - .c_cnt_prst2(1), - .c_cnt_ph_mux_prst2(0), - .c_cnt_in_src2("ph_mux_clk"), - .c_cnt_bypass_en2("true"), - .c_cnt_odd_div_duty_en2("false"), - .c_cnt_hi_div3(1), - .c_cnt_lo_div3(1), - .c_cnt_prst3(1), - .c_cnt_ph_mux_prst3(0), - .c_cnt_in_src3("ph_mux_clk"), - .c_cnt_bypass_en3("true"), - .c_cnt_odd_div_duty_en3("false"), - .c_cnt_hi_div4(1), - .c_cnt_lo_div4(1), - .c_cnt_prst4(1), - .c_cnt_ph_mux_prst4(0), - .c_cnt_in_src4("ph_mux_clk"), - .c_cnt_bypass_en4("true"), - .c_cnt_odd_div_duty_en4("false"), - .c_cnt_hi_div5(1), - .c_cnt_lo_div5(1), - .c_cnt_prst5(1), - .c_cnt_ph_mux_prst5(0), - .c_cnt_in_src5("ph_mux_clk"), - .c_cnt_bypass_en5("true"), - .c_cnt_odd_div_duty_en5("false"), - .c_cnt_hi_div6(1), - .c_cnt_lo_div6(1), - .c_cnt_prst6(1), - .c_cnt_ph_mux_prst6(0), - .c_cnt_in_src6("ph_mux_clk"), - .c_cnt_bypass_en6("true"), - .c_cnt_odd_div_duty_en6("false"), - .c_cnt_hi_div7(1), - .c_cnt_lo_div7(1), - .c_cnt_prst7(1), - .c_cnt_ph_mux_prst7(0), - .c_cnt_in_src7("ph_mux_clk"), - .c_cnt_bypass_en7("true"), - .c_cnt_odd_div_duty_en7("false"), - .c_cnt_hi_div8(1), - .c_cnt_lo_div8(1), - .c_cnt_prst8(1), - .c_cnt_ph_mux_prst8(0), - .c_cnt_in_src8("ph_mux_clk"), - .c_cnt_bypass_en8("true"), - .c_cnt_odd_div_duty_en8("false"), - .c_cnt_hi_div9(1), - .c_cnt_lo_div9(1), - .c_cnt_prst9(1), - .c_cnt_ph_mux_prst9(0), - .c_cnt_in_src9("ph_mux_clk"), - .c_cnt_bypass_en9("true"), - .c_cnt_odd_div_duty_en9("false"), - .c_cnt_hi_div10(1), - .c_cnt_lo_div10(1), - .c_cnt_prst10(1), - .c_cnt_ph_mux_prst10(0), - .c_cnt_in_src10("ph_mux_clk"), - .c_cnt_bypass_en10("true"), - .c_cnt_odd_div_duty_en10("false"), - .c_cnt_hi_div11(1), - .c_cnt_lo_div11(1), - .c_cnt_prst11(1), - .c_cnt_ph_mux_prst11(0), - .c_cnt_in_src11("ph_mux_clk"), - .c_cnt_bypass_en11("true"), - .c_cnt_odd_div_duty_en11("false"), - .c_cnt_hi_div12(1), - .c_cnt_lo_div12(1), - .c_cnt_prst12(1), - .c_cnt_ph_mux_prst12(0), - .c_cnt_in_src12("ph_mux_clk"), - .c_cnt_bypass_en12("true"), - .c_cnt_odd_div_duty_en12("false"), - .c_cnt_hi_div13(1), - .c_cnt_lo_div13(1), - .c_cnt_prst13(1), - .c_cnt_ph_mux_prst13(0), - .c_cnt_in_src13("ph_mux_clk"), - .c_cnt_bypass_en13("true"), - .c_cnt_odd_div_duty_en13("false"), - .c_cnt_hi_div14(1), - .c_cnt_lo_div14(1), - .c_cnt_prst14(1), - .c_cnt_ph_mux_prst14(0), - .c_cnt_in_src14("ph_mux_clk"), - .c_cnt_bypass_en14("true"), - .c_cnt_odd_div_duty_en14("false"), - .c_cnt_hi_div15(1), - .c_cnt_lo_div15(1), - .c_cnt_prst15(1), - .c_cnt_ph_mux_prst15(0), - .c_cnt_in_src15("ph_mux_clk"), - .c_cnt_bypass_en15("true"), - .c_cnt_odd_div_duty_en15("false"), - .c_cnt_hi_div16(1), - .c_cnt_lo_div16(1), - .c_cnt_prst16(1), - .c_cnt_ph_mux_prst16(0), - .c_cnt_in_src16("ph_mux_clk"), - .c_cnt_bypass_en16("true"), - .c_cnt_odd_div_duty_en16("false"), - .c_cnt_hi_div17(1), - .c_cnt_lo_div17(1), - .c_cnt_prst17(1), - .c_cnt_ph_mux_prst17(0), - .c_cnt_in_src17("ph_mux_clk"), - .c_cnt_bypass_en17("true"), - .c_cnt_odd_div_duty_en17("false"), - .pll_vco_div(2), - .pll_cp_current(20), - .pll_bwctrl(4000), - .pll_output_clk_frequency("445.499999 MHz"), - .pll_fractional_division("3908420153"), - .mimic_fbclk_type("none"), - .pll_fbclk_mux_1("glb"), - .pll_fbclk_mux_2("m_cnt"), - .pll_m_cnt_in_src("ph_mux_clk"), - .pll_slf_rst("true") - ) altera_pll_i ( - .rst (rst), - .outclk ({outclk_0}), - .locked (locked), - .reconfig_to_pll (reconfig_to_pll), - .fboutclk ( ), - .fbclk (1'b0), - .refclk (refclk), - .reconfig_from_pll (reconfig_from_pll) - ); -endmodule - diff --git a/sys/pll_hdmi_adj.vhd b/sys/pll_hdmi_adj.vhd deleted file mode 100644 index 67287cb..0000000 --- a/sys/pll_hdmi_adj.vhd +++ /dev/null @@ -1,433 +0,0 @@ --------------------------------------------------------------------------------- --- HDMI PLL Adjust --------------------------------------------------------------------------------- - --- Changes the HDMI PLL frequency according to the scaler suggestions. --------------------------------------------- --- LLTUNE : --- 0 : Input Display Enable --- 1 : Input Vsync --- 2 : Input Interlaced mode --- 3 : Input Interlaced field --- 4 : Output Image frame --- 5 : --- 6 : Input clock --- 7 : Output clock - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -ENTITY pll_hdmi_adj IS - PORT ( - -- Scaler - llena : IN std_logic; -- 0=Disabled 1=Enabled - lltune : IN unsigned(15 DOWNTO 0); -- Outputs from scaler - - locked : OUT std_logic; - - -- Signals from reconfig commands - i_waitrequest : OUT std_logic; - i_write : IN std_logic; - i_address : IN unsigned(5 DOWNTO 0); - i_writedata : IN unsigned(31 DOWNTO 0); - - -- Outputs to PLL_HDMI_CFG - o_waitrequest : IN std_logic; - o_write : OUT std_logic; - o_address : OUT unsigned(5 DOWNTO 0); - o_writedata : OUT unsigned(31 DOWNTO 0); - - ------------------------------------ - clk : IN std_logic; - reset_na : IN std_logic - ); - -BEGIN - - -END ENTITY pll_hdmi_adj; - ---############################################################################## - -ARCHITECTURE rtl OF pll_hdmi_adj IS - - SIGNAL i_clk,i_de,i_de2,i_vss,i_vss2,i_vss_delay,i_ce : std_logic; - SIGNAL i_linecpt,i_line : natural RANGE 0 TO 2**12-1; - SIGNAL i_delay : natural RANGE 0 TO 2**14-1; - - SIGNAL pwrite : std_logic; - SIGNAL paddress : unsigned(5 DOWNTO 0); - SIGNAL pdata : unsigned(31 DOWNTO 0); - TYPE enum_state IS (sIDLE,sW1,sW2,sW3,sW4,sW5,sW6); - SIGNAL state : enum_state; - SIGNAL tune_freq,tune_phase : unsigned(5 DOWNTO 0); - SIGNAL lltune_sync,lltune_sync2,lltune_sync3 : unsigned(15 DOWNTO 0); - SIGNAL mfrac,mfrac_mem,mfrac_ref,diff : unsigned(40 DOWNTO 0); - SIGNAL mul : unsigned(15 DOWNTO 0); - SIGNAL sign,sign_pre : std_logic; - SIGNAL expand : boolean; - SIGNAL up,modo,phm,dir : std_logic; - SIGNAL cpt : natural RANGE 0 TO 3; - SIGNAL col : natural RANGE 0 TO 15; - - SIGNAL icpt,ocpt,o2cpt,ssh,ofsize,ifsize : natural RANGE 0 TO 2**24-1; - SIGNAL ivss,ivss2,itog : std_logic; - SIGNAL ovss,ovss2,otog : std_logic; - SIGNAL sync,pulse,los,lop : std_logic; - SIGNAL osize,offset,osizep,offsetp : signed(23 DOWNTO 0); - SIGNAL logcpt : natural RANGE 0 TO 31; - SIGNAL udiff : integer RANGE -2**23 TO 2**23-1 :=0; - -BEGIN - - ---------------------------------------------------------------------------- - -- 4 lines delay to input - i_vss<=lltune(0); - i_de <=lltune(1); - i_ce <=lltune(5); - i_clk<=lltune(6); - - Delay:PROCESS(i_clk) IS - BEGIN - IF rising_edge(i_clk) THEN - IF i_ce='1' THEN - -- Measure input line time. - i_de2<=i_de; - - IF i_de='1' AND i_de2='0' THEN - i_linecpt<=0; - IF i_vss='1' THEN - i_line<=i_linecpt; - END IF; - ELSE - i_linecpt<=i_linecpt+1; - END IF; - - -- Delay 4 lines - i_vss2<=i_vss; - IF i_vss/=i_vss2 THEN - i_delay<=0; - ELSIF i_delay=i_line * 4 THEN - i_vss_delay<=i_vss; - ELSE - i_delay<=i_delay+1; - END IF; - END IF; - END IF; - END PROCESS Delay; - - ---------------------------------------------------------------------------- - -- Sample image sizes - Sampler:PROCESS(clk,reset_na) IS - BEGIN - IF reset_na='0' THEN ---pragma synthesis_off - otog<='0'; - itog<='0'; - ivss<='0'; - ivss2<='0'; - ovss<='0'; - ovss2<='0'; ---pragma synthesis_on - - ELSIF rising_edge(clk) THEN - -- Clock domain crossing - - ivss<=i_vss_delay; -- - ivss2<=ivss; - - ovss<=lltune(4); -- - ovss2<=ovss; - - otog<=otog XOR (ovss AND NOT ovss2); - - -- Measure output frame time - IF ovss='1' AND ovss2='0' AND otog='1' THEN - ocpt<=0; - osizep<=to_signed(ocpt,24); - ELSE - ocpt<=ocpt+1; - END IF; - IF ovss='0' AND ovss2='1' AND otog='0' THEN - o2cpt<=0; - ELSE - o2cpt<=o2cpt+1; - END IF; - - -- Measure output image time - IF ovss='0' AND ovss2='1' AND otog='0' THEN - ofsize<=ocpt; - END IF; - - itog<=itog XOR (ivss AND NOT ivss2); - - -- Measure input frame time - IF ivss='1' AND ivss2='0' AND itog='1' THEN - icpt<=0; - osize<=osizep; - udiff<=integer(to_integer(osizep)) - integer(icpt); - sync<='1'; - ELSE - icpt<=icpt+1; - sync<='0'; - END IF; - - -- Measure input image time - IF ivss='0' AND ivss2='1' AND itog='0' THEN - ifsize<=icpt; - END IF; - - expand<=(ofsize>=ifsize); - -- IN | ######### | EXPAND = 1 - -- OUT | ############# | - - -- IN | ######### | EXPAND = 0 - -- OUT | ###### | - - IF expand THEN - IF ivss='1' AND ivss2='0' AND itog='1' THEN - offset<=to_signed(ocpt,24); - END IF; - ELSE - IF ivss='0' AND ivss2='1' AND itog='0' THEN - offset<=to_signed(o2cpt,24); - END IF; - END IF; - - -------------------------------------------- - pulse<='0'; - IF sync='1' THEN - logcpt<=0; - ssh<=to_integer(osize); - los<='0'; - lop<='0'; - - ELSIF logcpt<24 THEN - -- Frequency difference - IF udiff>0 AND ssh=osize/2 AND ssh<(osize-offset) AND lop='0' THEN - tune_phase<='1' & to_unsigned(logcpt,5); - lop<='1'; - END IF; - ssh<=ssh/2; - logcpt<=logcpt+1; - - ELSIF logcpt=24 THEN - pulse<='1'; - ssh<=ssh/2; - logcpt<=logcpt+1; - END IF; - - END IF; - END PROCESS Sampler; - - ---------------------------------------------------------------------------- - -- 000010 : Start reg "Write either 0 or 1 to start fractional PLL reconf. - -- 000100 : M counter - -- 000111 : M counter Fractional Value K - - Comb:PROCESS(i_write,i_address, - i_writedata,pwrite,paddress,pdata) IS - BEGIN - IF i_write='1' THEN - o_write <=i_write; - o_address <=i_address; - o_writedata <=i_writedata; - ELSE - o_write <=pwrite; - o_address <=paddress; - o_writedata<=pdata; - END IF; - END PROCESS Comb; - - i_waitrequest<=o_waitrequest WHEN state=sIDLE ELSE '0'; - - ---------------------------------------------------------------------------- - Schmurtz:PROCESS(clk,reset_na) IS - VARIABLE off_v,ofp_v : natural RANGE 0 TO 63; - VARIABLE diff_v : unsigned(40 DOWNTO 0); - VARIABLE mulco : unsigned(15 DOWNTO 0); - VARIABLE up_v,sign_v : std_logic; - BEGIN - IF reset_na='0' THEN - modo<='0'; - state<=sIDLE; - ELSIF rising_edge(clk) THEN - ------------------------------------------------------ - -- Snoop accesses to PLL reconfiguration - IF i_address="000100" AND i_write='1' THEN - mfrac (40 DOWNTO 32)<=('0' & i_writedata(15 DOWNTO 8)) + - ('0' & i_writedata(7 DOWNTO 0)); - mfrac_ref(40 DOWNTO 32)<=('0' & i_writedata(15 DOWNTO 8)) + - ('0' & i_writedata(7 DOWNTO 0)); - mfrac_mem(40 DOWNTO 32)<=('0' & i_writedata(15 DOWNTO 8)) + - ('0' & i_writedata(7 DOWNTO 0)); - mul<=i_writedata(15 DOWNTO 0); - modo<='1'; - END IF; - - IF i_address="000111" AND i_write='1' THEN - mfrac (31 DOWNTO 0)<=i_writedata; - mfrac_ref(31 DOWNTO 0)<=i_writedata; - mfrac_mem(31 DOWNTO 0)<=i_writedata; - modo<='1'; - END IF; - - ------------------------------------------------------ - -- Tuning - off_v:=to_integer('0' & tune_freq(4 DOWNTO 0)); - ofp_v:=to_integer('0' & tune_phase(4 DOWNTO 0)); - --IF off_v<8 THEN off_v:=8; END IF; - --IF ofp_v<7 THEN ofp_v:=7; END IF; - IF off_v<4 THEN off_v:=4; END IF; - IF ofp_v<4 THEN ofp_v:=4; END IF; - - IF off_v>=18 AND ofp_v>=18 THEN - locked<=llena; - ELSE - locked<='0'; - END IF; - - up_v:='0'; - IF pulse='1' THEN - cpt<=(cpt+1) MOD 4; - IF llena='0' THEN - -- Recover original freq when disabling low lag mode - cpt<=0; - col<=0; - IF modo='1' THEN - mfrac<=mfrac_mem; - mfrac_ref<=mfrac_mem; - up<='1'; - modo<='0'; - END IF; - - ELSIF phm='0' AND cpt=0 THEN - -- Frequency adjust - sign_v:=tune_freq(5); - IF col<10 THEN col<=col+1; END IF; - IF off_v>=16 AND col>=10 THEN - phm<='1'; - col<=0; - ELSE - off_v:=off_v+1; - IF off_v>17 THEN - off_v:=off_v + 3; - END IF; - up_v:='1'; - up<='1'; - END IF; - - ELSIF cpt=0 THEN - -- Phase adjust - sign_v:=NOT tune_phase(5); - col<=col+1; - IF col>=10 THEN - phm<='0'; - up_v:='1'; - off_v:=31; - col<=0; - ELSE - off_v:=ofp_v + 1; - IF ofp_v>7 THEN - off_v:=off_v + 1; - END IF; - IF ofp_v>14 THEN - off_v:=off_v + 2; - END IF; - IF ofp_v>17 THEN - off_v:=off_v + 3; - END IF; - up_v:='1'; - END IF; - up<='1'; - END IF; - END IF; - - diff_v:=shift_right(mfrac_ref,off_v); - IF sign_v='0' THEN - diff_v:=mfrac_ref + diff_v; - ELSE - diff_v:=mfrac_ref - diff_v; - END IF; - - IF up_v='1' THEN - mfrac<=diff_v; - END IF; - - IF up_v='1' AND phm='0' THEN - mfrac_ref<=diff_v; - END IF; - - ------------------------------------------------------ - -- Update PLL registers - mulco:=mfrac(40 DOWNTO 33) & (mfrac(40 DOWNTO 33) + ('0' & mfrac(32))); - - CASE state IS - WHEN sIDLE => - pwrite<='0'; - IF up='1' THEN - up<='0'; - IF mulco/=mul THEN - state<=sW1; - ELSE - state<=sW3; - END IF; - END IF; - - WHEN sW1 => -- Change M multiplier - mul<=mulco; - pdata<=x"0000" & mulco; - paddress<="000100"; - pwrite<='1'; - state<=sW2; - - WHEN sW2 => - IF pwrite='1' AND o_waitrequest='0' THEN - state<=sW3; - pwrite<='0'; - END IF; - - WHEN sW3 => -- Change M fractional value - pdata<=mfrac(31 DOWNTO 0); - paddress<="000111"; - pwrite<='1'; - state<=sW4; - - WHEN sW4 => - IF pwrite='1' AND o_waitrequest='0' THEN - state<=sW5; - pwrite<='0'; - END IF; - - WHEN sW5 => - pdata<=x"0000_0001"; - paddress<="000010"; - pwrite<='1'; - state<=sW6; - - WHEN sW6 => - IF pwrite='1' AND o_waitrequest='0' THEN - pwrite<='0'; - state<=sIDLE; - END IF; - END CASE; - - END IF; - END PROCESS Schmurtz; - - ---------------------------------------------------------------------------- - -END ARCHITECTURE rtl; - diff --git a/sys/pll_q13.qip b/sys/pll_q13.qip deleted file mode 100644 index 78e7e40..0000000 --- a/sys/pll_q13.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ] -set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ] -set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.13.qip ] -set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ] diff --git a/sys/pll_q17.qip b/sys/pll_q17.qip deleted file mode 100644 index 85cc84b..0000000 --- a/sys/pll_q17.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name QIP_FILE rtl/pll.qip -set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ] -set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.qip ] -set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ] diff --git a/sys/scandoubler.v b/sys/scandoubler.v deleted file mode 100644 index 81e7c3f..0000000 --- a/sys/scandoubler.v +++ /dev/null @@ -1,211 +0,0 @@ -// -// scandoubler.v -// -// Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017-2021 Alexey Melnikov -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -// TODO: Delay vsync one line - -module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) -( - // system interface - input clk_vid, - input hq2x, - - // shifter video interface - input ce_pix, - input hs_in, - input vs_in, - input hb_in, - input vb_in, - input [DWIDTH:0] r_in, - input [DWIDTH:0] g_in, - input [DWIDTH:0] b_in, - - // output interface - output ce_pix_out, - output reg hs_out, - output vs_out, - output hb_out, - output vb_out, - output [DWIDTH:0] r_out, - output [DWIDTH:0] g_out, - output [DWIDTH:0] b_out -); - -localparam DWIDTH = HALF_DEPTH ? 3 : 7; - -reg [7:0] pix_len = 0; -wire [7:0] pl = pix_len + 1'b1; - -reg [7:0] pix_in_cnt = 0; -wire [7:0] pc_in = pix_in_cnt + 1'b1; -reg [7:0] pixsz, pixsz2, pixsz4 = 0; - -reg ce_x4i, ce_x1i; -always @(posedge clk_vid) begin - reg old_ce, valid, hs; - - if(~&pix_len) pix_len <= pl; - if(~&pix_in_cnt) pix_in_cnt <= pc_in; - - ce_x4i <= 0; - ce_x1i <= 0; - - // use such odd comparison to place ce_x4 evenly if master clock isn't multiple of 4. - if((pc_in == pixsz4) || (pc_in == pixsz2) || (pc_in == (pixsz2+pixsz4))) ce_x4i <= 1; - - old_ce <= ce_pix; - if(~old_ce & ce_pix) begin - if(valid & ~hb_in & ~vb_in) begin - pixsz <= pl; - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - end - pix_len <= 0; - valid <= 1; - end - - hs <= hs_in; - if((~hs & hs_in) || (pc_in >= pixsz)) begin - ce_x4i <= 1; - ce_x1i <= 1; - pix_in_cnt <= 0; - end - - if(hb_in | vb_in) valid <= 0; -end - -reg req_line_reset; -reg [DWIDTH:0] r_d, g_d, b_d; -always @(posedge clk_vid) begin - if(ce_x1i) begin - req_line_reset <= hb_in; - r_d <= r_in; - g_d <= g_in; - b_d <= b_in; - end -end - -Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x -( - .clk(clk_vid), - - .ce_in(ce_x4i), - .inputpixel({b_d,g_d,r_d}), - .disable_hq2x(~hq2x), - .reset_frame(vb_in), - .reset_line(req_line_reset), - - .ce_out(ce_x4o), - .read_y(sd_line), - .hblank(hbo[0]&hbo[8]), - .outpixel({b_out,g_out,r_out}) -); - -reg [7:0] pix_out_cnt = 0; -wire [7:0] pc_out = pix_out_cnt + 1'b1; - -reg ce_x4o, ce_x2o; -always @(posedge clk_vid) begin - reg hs; - - if(~&pix_out_cnt) pix_out_cnt <= pc_out; - - ce_x4o <= 0; - ce_x2o <= 0; - - // use such odd comparison to place ce_x4 evenly if master clock isn't multiple of 4. - if((pc_out == pixsz4) || (pc_out == pixsz2) || (pc_out == (pixsz2+pixsz4))) ce_x4o <= 1; - if( pc_out == pixsz2) ce_x2o <= 1; - - hs <= hs_out; - if((~hs & hs_out) || (pc_out >= pixsz)) begin - ce_x2o <= 1; - ce_x4o <= 1; - pix_out_cnt <= 0; - end -end - -reg [1:0] sd_line; -reg [3:0] vbo; -reg [3:0] vso; -reg [8:0] hbo; -always @(posedge clk_vid) begin - - reg [31:0] hcnt; - reg [30:0] sd_hcnt; - reg [30:0] hs_start, hs_end; - reg [30:0] hde_start, hde_end; - - reg hs, hb; - - if(ce_x4o) begin - hbo[8:1] <= hbo[7:0]; - end - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 1'd1; - if(sd_hcnt == hde_start) begin - sd_hcnt <= 0; - vbo[3:1] <= vbo[2:0]; - end - - if(sd_hcnt == hs_end) begin - sd_line <= sd_line + 1'd1; - if(&vbo[3:2]) sd_line <= 1; - vso[3:1] <= vso[2:0]; - end - - if(sd_hcnt == hde_start)hbo[0] <= 0; - if(sd_hcnt == hde_end) hbo[0] <= 1; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_end) hs_out <= 0; - if(sd_hcnt == hs_start) hs_out <= 1; - - hs <= hs_in; - hb <= hb_in; - - hcnt <= hcnt + 1'd1; - if(hb && !hb_in) begin - hde_start <= hcnt[31:1]; - hbo[0] <= 0; - hcnt <= 0; - sd_hcnt <= 0; - vbo <= {vbo[2:0],vb_in}; - end - - if(!hb && hb_in) hde_end <= hcnt[31:1]; - - // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - hs_end <= hcnt[31:1]; - vso[0] <= vs_in; - end - - // save position of rising edge - if(!hs && hs_in) hs_start <= hcnt[31:1]; -end - -assign vs_out = vso[3]; -assign ce_pix_out = hq2x ? ce_x4o : ce_x2o; - -//Compensate picture shift after HQ2x -assign vb_out = vbo[3]; -assign hb_out = hbo[6]; - -endmodule diff --git a/sys/scanlines.v b/sys/scanlines.v deleted file mode 100644 index 43f890f..0000000 --- a/sys/scanlines.v +++ /dev/null @@ -1,68 +0,0 @@ -module scanlines #(parameter v2=0) -( - input clk, - - input [1:0] scanlines, - input [23:0] din, - input hs_in,vs_in, - input de_in,ce_in, - - output reg [23:0] dout, - output reg hs_out,vs_out, - output reg de_out,ce_out -); - -reg [1:0] scanline; -always @(posedge clk) begin - reg old_hs, old_vs; - - old_hs <= hs_in; - old_vs <= vs_in; - - if(old_hs && ~hs_in) begin - if(v2) begin - scanline <= scanline + 1'd1; - if (scanline == scanlines) scanline <= 0; - end - else scanline <= scanline ^ scanlines; - end - if(old_vs && ~vs_in) scanline <= 0; -end - -wire [7:0] r,g,b; -assign {r,g,b} = din; - -reg [23:0] d; -always @(*) begin - case(scanline) - 1: // reduce 25% = 1/2 + 1/4 - d = {{1'b0, r[7:1]} + {2'b00, r[7:2]}, - {1'b0, g[7:1]} + {2'b00, g[7:2]}, - {1'b0, b[7:1]} + {2'b00, b[7:2]}}; - - 2: // reduce 50% = 1/2 - d = {{1'b0, r[7:1]}, - {1'b0, g[7:1]}, - {1'b0, b[7:1]}}; - - 3: // reduce 75% = 1/4 - d = {{2'b00, r[7:2]}, - {2'b00, g[7:2]}, - {2'b00, b[7:2]}}; - - default: d = {r,g,b}; - endcase -end - -always @(posedge clk) begin - reg [23:0] dout1, dout2; - reg de1,de2,vs1,vs2,hs1,hs2,ce1,ce2; - - dout <= dout2; dout2 <= dout1; dout1 <= d; - vs_out <= vs2; vs2 <= vs1; vs1 <= vs_in; - hs_out <= hs2; hs2 <= hs1; hs1 <= hs_in; - de_out <= de2; de2 <= de1; de1 <= de_in; - ce_out <= ce2; ce2 <= ce1; ce1 <= ce_in; -end - -endmodule diff --git a/sys/sd_card.sv b/sys/sd_card.sv deleted file mode 100644 index 610c271..0000000 --- a/sys/sd_card.sv +++ /dev/null @@ -1,463 +0,0 @@ -// -// sd_card.v -// -// Copyright (c) 2014 Till Harbaum -// Copyright (c) 2015-2018 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the Lesser GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// http://elm-chan.org/docs/mmc/mmc_e.html -// -///////////////////////////////////////////////////////////////////////// - -// -// Made module syncrhronous. Total code refactoring. (Sorgelig) -// clk_spi must be at least 2 x sck for proper work. - -module sd_card #(parameter WIDE = 0, OCTAL=0) -( - input clk_sys, - input reset, - - input sdhc, - input img_mounted, - input [63:0] img_size, - - output reg [31:0] sd_lba, - output reg sd_rd, - output reg sd_wr, - input sd_ack, - - input [AW:0] sd_buff_addr, - input [DW:0] sd_buff_dout, - output [DW:0] sd_buff_din, - input sd_buff_wr, - - // SPI interface - input clk_spi, - - input ss, - input sck, - input [SW:0] mosi, - output reg [SW:0] miso -); - -localparam AW = WIDE ? 7 : 8; -localparam DW = WIDE ? 15 : 7; -localparam SZ = OCTAL ? 8 : 1; -localparam SW = SZ-1; - -wire [7:0] DATA_TOKEN_CMD25 = 8'hfc; -wire [7:0] STOP_TRAN = 8'hfd; -wire [7:0] DATA_TOKEN = 8'hfe; -wire [7:0] WRITE_DATA_RESPONSE = 8'h05; - -// number of bytes to wait after a command before sending the reply -localparam NCR = 5+3; // 5 bytes are required (command length) - -localparam RD_STATE_IDLE = 0; -localparam RD_STATE_START = 1; -localparam RD_STATE_WAIT_IO = 2; -localparam RD_STATE_SEND_TOKEN = 3; -localparam RD_STATE_SEND_DATA = 4; -localparam RD_STATE_WAIT_M = 5; - -localparam WR_STATE_IDLE = 0; -localparam WR_STATE_EXP_DTOKEN = 1; -localparam WR_STATE_RECV_DATA = 2; -localparam WR_STATE_RECV_CRC0 = 3; -localparam WR_STATE_RECV_CRC1 = 4; -localparam WR_STATE_SEND_DRESP = 5; -localparam WR_STATE_BUSY = 6; - -localparam PREF_STATE_IDLE = 0; -localparam PREF_STATE_RD = 1; -localparam PREF_STATE_FINISH = 2; - -altsyncram sdbuf -( - .clock0 (clk_sys), - .address_a ({sd_buf,sd_buff_addr}), - .data_a (sd_buff_dout), - .wren_a (sd_ack & sd_buff_wr), - .q_a (sd_buff_din), - - .clock1 (clk_spi), - .address_b ({spi_buf,buffer_ptr}), - .data_b (buffer_din), - .wren_b (buffer_wr), - .q_b (buffer_dout), - - .aclr0(1'b0), - .aclr1(1'b0), - .addressstall_a(1'b0), - .addressstall_b(1'b0), - .byteena_a(1'b1), - .byteena_b(1'b1), - .clocken0(1'b1), - .clocken1(1'b1), - .clocken2(1'b1), - .clocken3(1'b1), - .eccstatus(), - .rden_a(1'b1), - .rden_b(1'b1) -); -defparam - sdbuf.numwords_a = 1<<(AW+3), - sdbuf.widthad_a = AW+3, - sdbuf.width_a = DW+1, - sdbuf.numwords_b = 2048, - sdbuf.widthad_b = 11, - sdbuf.width_b = 8, - sdbuf.address_reg_b = "CLOCK1", - sdbuf.clock_enable_input_a = "BYPASS", - sdbuf.clock_enable_input_b = "BYPASS", - sdbuf.clock_enable_output_a = "BYPASS", - sdbuf.clock_enable_output_b = "BYPASS", - sdbuf.indata_reg_b = "CLOCK1", - sdbuf.intended_device_family = "Cyclone V", - sdbuf.lpm_type = "altsyncram", - sdbuf.operation_mode = "BIDIR_DUAL_PORT", - sdbuf.outdata_aclr_a = "NONE", - sdbuf.outdata_aclr_b = "NONE", - sdbuf.outdata_reg_a = "UNREGISTERED", - sdbuf.outdata_reg_b = "UNREGISTERED", - sdbuf.power_up_uninitialized = "FALSE", - sdbuf.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", - sdbuf.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", - sdbuf.width_byteena_a = 1, - sdbuf.width_byteena_b = 1, - sdbuf.wrcontrol_wraddress_reg_b = "CLOCK1"; - -reg [26:0] csd_size; -reg csd_sdhc; -always @(posedge clk_sys) begin - if (img_mounted) begin - csd_sdhc <= sdhc; - if (sdhc) begin - csd_size[0] <= 0; - csd_size[22:1] <= img_size[40:19]; // in 512K units - csd_size[26:23] <= 0; - end - else begin - csd_size[2:0] <= 7; // C_SIZE_MULT - csd_size[14:3] <= 12'b101101101101; - csd_size[26:15] <= img_size[29:18]; // in 256K units ((2**(C_SIZE_MULT+2))*512) - end - end -end - -wire [127:0] CSD = {1'b0,csd_sdhc,6'h00,8'h0e,8'h00,8'h32,8'h5b,8'h59,6'h00,csd_size,7'h7f,8'h80,8'h0a,8'h40,8'h40,8'hf1}; -wire [127:0] CID = {8'hcd,8'hc7,8'h00,8'h93,8'h6f,8'h2f,8'h73,8'h00,8'h00,8'h44,8'h32,8'h38,8'h34,8'h00,8'h00,8'h3e}; - -reg [8:0] buffer_ptr; -reg [7:0] buffer_din; -wire [7:0] buffer_dout; -reg buffer_wr; - -reg [1:0] sd_buf, spi_buf; - -reg [6:0] sbuf; -reg [2:0] bit_cnt; - -wire last_bit = &bit_cnt || OCTAL; -wire [7:0] ibuf = OCTAL ? mosi : {sbuf,mosi[0]}; - -always @(posedge clk_spi) begin - reg [2:0] read_state; - reg [2:0] write_state; - reg [1:0] pref_state; - reg [5:0] cmd; - reg cmd55; - reg [39:0] reply; - reg [3:0] byte_cnt; - reg old_sck; - reg [2:0] ack; - reg [2:0] wait_m_cnt; - reg [31:0] arg; - - ack[1:0] <= {ack[0],sd_ack}; - if(ack[1] == ack[0]) ack[2] <= ack[1]; - - if(~ack[2] & ack[1]) {sd_rd,sd_wr} <= 0; - if( ack[2] & ~ack[1]) begin - sd_buf <= sd_buf + 1'd1; - sd_lba <= sd_lba + 1; - end - - buffer_wr <= 0; - - if(reset) begin - bit_cnt <= 0; - byte_cnt <= '1; - miso <= '1; - cmd <= 0; - sd_wr <= 0; - sd_rd <= 0; - read_state <= RD_STATE_IDLE; - write_state <= WR_STATE_IDLE; - pref_state <= PREF_STATE_IDLE; - end - else begin - - if(buffer_wr) begin - if(~&buffer_ptr) buffer_ptr <= buffer_ptr + 1'd1; - else begin - spi_buf <= spi_buf + 1'd1; - sd_wr <= 1; - end - end - - case(pref_state) - PREF_STATE_IDLE: - if(((sd_buf - spi_buf) <= 1) && (read_state != RD_STATE_IDLE) && (cmd == 17 || cmd == 18)) begin - sd_rd <= 1; - pref_state <= PREF_STATE_RD; - end - - PREF_STATE_RD: - if(read_state == RD_STATE_IDLE) begin - pref_state <= PREF_STATE_IDLE; - end - else if(ack[2] & ~ack[1]) begin - pref_state <= (cmd == 18) ? PREF_STATE_IDLE : PREF_STATE_FINISH; - end - - PREF_STATE_FINISH: - if(read_state == RD_STATE_IDLE) begin - pref_state <= PREF_STATE_IDLE; - end - endcase - - old_sck <= sck; - if(ss) begin - bit_cnt <= 0; - byte_cnt <= '1; - miso <= '1; - end - else if(old_sck & ~sck) begin - miso <= '1; // default: send 1's (busy/wait) - if(byte_cnt >= NCR) {miso,reply} <= {reply, {SZ{1'b1}}}; - - // ---------- read state machine processing ------------- - case(read_state) - RD_STATE_IDLE: ; - - RD_STATE_START: begin - if(byte_cnt == NCR && last_bit) read_state <= (cmd == 9 || cmd == 10) ? RD_STATE_SEND_TOKEN : RD_STATE_WAIT_IO; - end - - // waiting for io controller to return data - RD_STATE_WAIT_IO: begin - if(sd_buf != spi_buf && last_bit) read_state <= RD_STATE_SEND_TOKEN; - end - - // send data token - RD_STATE_SEND_TOKEN: begin - miso <= DATA_TOKEN[~bit_cnt -:SZ]; - if(last_bit) begin - read_state <= RD_STATE_SEND_DATA; // next: send data - buffer_ptr <= 0; - end - end - - // send data - RD_STATE_SEND_DATA: begin - - miso <= (cmd == 9) ? CSD[{buffer_ptr[3:0],~bit_cnt} -:SZ] : (cmd == 10) ? CID[{buffer_ptr[3:0],~bit_cnt} -:SZ] : buffer_dout[~bit_cnt -:SZ]; - - if(last_bit) begin - - // sent 512 sector data bytes? - if(cmd == 17 && &buffer_ptr) read_state <= RD_STATE_IDLE; - else if(cmd == 18 && &buffer_ptr) begin - read_state <= RD_STATE_WAIT_M; - wait_m_cnt <= 0; - end - - // sent 16 cid/csd data bytes? - else if((cmd == 9 || cmd == 10) && &buffer_ptr[3:0]) read_state <= RD_STATE_IDLE; - - // not done yet -> trigger read of next data byte - else buffer_ptr <= buffer_ptr + 1'd1; - end - end - - RD_STATE_WAIT_M: begin - if(last_bit) begin - wait_m_cnt <= wait_m_cnt + 1'd1; - if(&wait_m_cnt) begin - spi_buf <= spi_buf + 1'd1; - read_state <= RD_STATE_WAIT_IO; - end - end - end - endcase - - // ------------------ write support ---------------------- - // send write data response - if(write_state == WR_STATE_SEND_DRESP) miso <= WRITE_DATA_RESPONSE[~bit_cnt -:SZ]; - - // busy after write until the io controller sends ack - if(write_state == WR_STATE_BUSY) miso <= 0; - end - else if(~old_sck & sck) begin - - sbuf[6:0] <= {sbuf[5:0],mosi[0]}; - bit_cnt <= bit_cnt + SZ[2:0]; - - if(last_bit) begin - // finished reading one byte - // byte counter runs against 15 byte boundary - if(~&byte_cnt) byte_cnt <= byte_cnt + 1'd1; - - // byte_cnt > 6 -> complete command received - // first byte of valid command is 01xxxxxx - // don't accept new commands once a write or read command has been accepted - if(byte_cnt > 5 && - ((write_state == WR_STATE_IDLE && read_state == RD_STATE_IDLE && ibuf[7:6] == 1) || - (read_state != RD_STATE_IDLE && ibuf == 8'h4c))) begin - byte_cnt <= 0; - cmd <= ibuf[5:0]; - cmd55 <= (cmd == 55); // set cmd55 flag if previous command was 55 - if(ibuf[5:0] == 12) read_state <= RD_STATE_IDLE; - end - - // parse additional command bytes - if(byte_cnt == 0) arg[31:24] <= ibuf; - if(byte_cnt == 1) arg[23:16] <= ibuf; - if(byte_cnt == 2) arg[15:8] <= ibuf; - if(byte_cnt == 3) arg[7:0] <= ibuf; - - // last byte (crc) received, evaluate - if(byte_cnt == 4) begin - - // default: - reply <= 40'h04FFFFFFFF; // illegal command - - case(cmd) - // CMD0: GO_IDLE_STATE - 0: reply[39:32] <= 1; // ok, busy - - // CMD1: SEND_OP_COND - 1: reply[39:32] <= 0; - - // CMD8: SEND_IF_COND (V2 only) - 8: reply <= 40'h01000001AA; // ok, busy - - // CMD9: SEND_CSD - 9, - // CMD10: SEND_CID - 10: begin - reply[39:32] <= 0; - read_state <= RD_STATE_START; - end - - // CMD12: STOP_TRANSMISSION - 12: reply[39:32] <= 0; - - // CMD13: SEND_STATUS - 13: reply[39:24] <= 16'h0000; - - // CMD16: SET_BLOCKLEN - 16: reply[39:32] <= (arg == 512) ? 8'h00 : 8'h40; // we only support a block size of 512 - - // CMD17: READ_SINGLE_BLOCK - 17, - // CMD18: READ_MULTIPLE - 18: begin - reply[39:32] <= 0; - read_state <= RD_STATE_START; - spi_buf <= 0; - sd_buf <= 0; - sd_lba <= csd_sdhc ? arg : {9'd0, arg[31:9]}; - end - - // ACMD23: SET_WR_BLK_ERASE_COUNT - 23: reply[39:32] <= 0; - - // CMD24: WRITE_BLOCK - 24, - // CMD25: WRITE_MULTIPLE - 25: begin - reply[39:32] <= 0; - write_state <= WR_STATE_EXP_DTOKEN; // expect data token - spi_buf <= 0; - sd_buf <= 0; - sd_lba <= csd_sdhc ? arg : {9'd0, arg[31:9]}; - end - - // ACMD41: APP_SEND_OP_COND - 41: if(cmd55) reply[39:32] <= 0; // ok, not busy - - // CMD55: APP_COND - 55: reply[39:32] <= 1; // ok, busy - - // CMD58: READ_OCR - 58: reply <= { 8'h00, 1'b1, csd_sdhc, 30'd0 }; // bit 30 = 1 -> high capacity card - - // CMD59: CRC_ON_OFF - 59: reply[39:32] <= 0; - endcase - end - - // ---------- handle write ----------- - case(write_state) - // do nothing in idle state - WR_STATE_IDLE: ; - - // waiting for data token - WR_STATE_EXP_DTOKEN: begin - buffer_ptr <= 0; - if(cmd == 24) begin - if(ibuf == DATA_TOKEN) write_state <= WR_STATE_RECV_DATA; - end - else begin - if(ibuf == DATA_TOKEN_CMD25) write_state <= WR_STATE_RECV_DATA; - if(ibuf == STOP_TRAN) write_state <= WR_STATE_IDLE; - end - end - - // transfer 512 bytes - WR_STATE_RECV_DATA: begin - // push one byte into local buffer - buffer_wr <= 1; - buffer_din <= ibuf; - - // all bytes written? - if(&buffer_ptr) write_state <= WR_STATE_RECV_CRC0; - end - - // transfer 1st crc byte - WR_STATE_RECV_CRC0: - write_state <= WR_STATE_RECV_CRC1; - - // transfer 2nd crc byte - WR_STATE_RECV_CRC1: - write_state <= WR_STATE_SEND_DRESP; - - // send data response - WR_STATE_SEND_DRESP: - write_state <= WR_STATE_BUSY; - - // wait for io controller to accept data - WR_STATE_BUSY: - if(spi_buf == sd_buf) write_state <= (cmd == 25) ? WR_STATE_EXP_DTOKEN : WR_STATE_IDLE; - endcase - end - end - end -end - -endmodule diff --git a/sys/shadowmask.sv b/sys/shadowmask.sv deleted file mode 100644 index 572679c..0000000 --- a/sys/shadowmask.sv +++ /dev/null @@ -1,136 +0,0 @@ -module shadowmask -( - input clk, - input clk_sys, - - input cmd_wr, - input [15:0] cmd_in, - - input [23:0] din, - input hs_in,vs_in, - input de_in, - input brd_in, - input enable, - - output reg [23:0] dout, - output reg hs_out,vs_out, - output reg de_out -); - - -reg [4:0] hmax; -reg [4:0] vmax; -reg [7:0] mask_idx; -reg mask_2x; -reg mask_rotate; -reg mask_enable; -reg [10:0] mask_lut[256]; - -always @(posedge clk) begin - reg [4:0] hcount; - reg [4:0] vcount; - reg [3:0] hindex; - reg [3:0] vindex; - reg [4:0] hmax2; - reg [4:0] vmax2; - reg [11:0] pcnt,pde; - reg old_hs, old_vs, old_brd; - reg next_v; - - old_hs <= hs_in; - old_vs <= vs_in; - old_brd<= brd_in; - - // hcount and vcount counts pixel rows and columns - // hindex and vindex half the value of the counters for double size patterns - // hindex2, vindex2 swap the h and v counters for drawing rotated masks - hindex <= mask_2x ? hcount[4:1] : hcount[3:0]; - vindex <= mask_2x ? vcount[4:1] : vcount[3:0]; - mask_idx <= mask_rotate ? {hindex,vindex} : {vindex,hindex}; - - // hmax and vmax store these sizes - // hmax2 and vmax2 swap the values to handle rotation - hmax2 <= ((mask_rotate ? vmax : hmax) << mask_2x) | mask_2x; - vmax2 <= ((mask_rotate ? hmax : vmax) << mask_2x) | mask_2x; - - pcnt <= pcnt+1'd1; - if(old_brd && ~brd_in) pde <= pcnt-4'd3; - - hcount <= hcount+1'b1; - if(hcount == hmax2 || pde == pcnt) hcount <= 0; - - if(~old_brd && brd_in) next_v <= 1; - if(old_vs && ~vs_in) vcount <= 0; - if(old_hs && ~hs_in) begin - vcount <= vcount + next_v; - next_v <= 0; - pcnt <= 0; - if (vcount == vmax2) vcount <= 0; - end -end - -reg [4:0] r_mul, g_mul, b_mul; // 1.4 fixed point multipliers -always @(posedge clk) begin - reg [10:0] lut; - - lut <= mask_lut[mask_idx]; - - r_mul <= 5'b10000; g_mul <= 5'b10000; b_mul <= 5'b10000; // default 100% to all channels - if (mask_enable) begin - r_mul <= lut[10] ? {1'b1,lut[7:4]} : {1'b0,lut[3:0]}; - g_mul <= lut[9] ? {1'b1,lut[7:4]} : {1'b0,lut[3:0]}; - b_mul <= lut[8] ? {1'b1,lut[7:4]} : {1'b0,lut[3:0]}; - end -end - -always @(posedge clk) begin - reg [11:0] vid; - reg [7:0] r1, g1, b1; - reg [7:0] r2, g2, b2; - reg [7:0] r3_x, g3_x, b3_x; // 6.25% + 12.5% - reg [8:0] r3_y, g3_y, b3_y; // 25% + 50% + 100% - reg [8:0] r4, g4, b4; - - // C1 - data input - {r1,g1,b1} <= din; - vid <= {vid[8:0],vs_in, hs_in, de_in}; - - // C2 - relax timings - {r2,g2,b2} <= {r1,g1,b1}; - - // C3 - perform multiplications - r3_x <= ({4{r_mul[0]}} & r2[7:4]) + ({8{r_mul[1]}} & r2[7:3]); - r3_y <= ({6{r_mul[2]}} & r2[7:2]) + ({7{r_mul[3]}} & r2[7:1]) + ({9{r_mul[4]}} & r2[7:0]); - g3_x <= ({4{g_mul[0]}} & g2[7:4]) + ({8{g_mul[1]}} & g2[7:3]); - g3_y <= ({6{g_mul[2]}} & g2[7:2]) + ({7{g_mul[3]}} & g2[7:1]) + ({9{g_mul[4]}} & g2[7:0]); - b3_x <= ({4{b_mul[0]}} & b2[7:4]) + ({8{b_mul[1]}} & b2[7:3]); - b3_y <= ({6{b_mul[2]}} & b2[7:2]) + ({7{b_mul[3]}} & b2[7:1]) + ({9{b_mul[4]}} & b2[7:0]); - - // C4 - combine results - r4 <= r3_x + r3_y; - g4 <= g3_x + g3_y; - b4 <= b3_x + b3_y; - - // C5 - clamp and output - dout <= {{8{r4[8]}} | r4[7:0], {8{g4[8]}} | g4[7:0], {8{b4[8]}} | b4[7:0]}; - {vs_out,hs_out,de_out} <= vid[11:9]; -end - -// clock in mask commands -always @(posedge clk_sys) begin - reg m_enable; - reg [7:0] idx; - - if (cmd_wr) begin - case(cmd_in[15:13]) - 3'b000: begin {m_enable, mask_rotate, mask_2x} <= cmd_in[3:1]; idx <= 0; end - 3'b001: vmax <= cmd_in[3:0]; - 3'b010: hmax <= cmd_in[3:0]; - 3'b011: begin mask_lut[idx] <= cmd_in[10:0]; idx <= idx + 1'd1; end - endcase - end - - mask_enable <= m_enable & enable; -end - -endmodule diff --git a/sys/sigma_delta_dac.v b/sys/sigma_delta_dac.v deleted file mode 100644 index d0d6be0..0000000 --- a/sys/sigma_delta_dac.v +++ /dev/null @@ -1,33 +0,0 @@ -// -// PWM DAC -// -// MSBI is the highest bit number. NOT amount of bits! -// -module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1) -( - output reg DACout, //Average Output feeding analog lowpass - input [MSBI:0] DACin, //DAC input (excess 2**MSBI) - input CLK, - input RESET -); - -reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder -reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder -reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder -reg [MSBI+2:0] DeltaB; //B input of Delta Adder - -always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); -always @(*) DeltaAdder = DACin + DeltaB; -always @(*) SigmaAdder = DeltaAdder + SigmaLatch; - -always @(posedge CLK or posedge RESET) begin - if(RESET) begin - SigmaLatch <= 1'b1 << (MSBI+1); - DACout <= INV; - end else begin - SigmaLatch <= SigmaAdder; - DACout <= SigmaLatch[MSBI+2] ^ INV; - end -end - -endmodule diff --git a/sys/spdif.v b/sys/spdif.v deleted file mode 100644 index eee2b08..0000000 --- a/sys/spdif.v +++ /dev/null @@ -1,320 +0,0 @@ -//----------------------------------------------------------------- -// SPDIF Transmitter -// V0.1 -// Ultra-Embedded.com -// Copyright 2012 -// -// Email: admin@ultra-embedded.com -// -// License: GPL -// If you would like a version with a more permissive license for -// use in closed source commercial applications please contact me -// for details. -//----------------------------------------------------------------- -// -// This file is open source HDL; you can redistribute it and/or -// modify it under the terms of the GNU General Public License as -// published by the Free Software Foundation; either version 2 of -// the License, or (at your option) any later version. -// -// This file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public -// License along with this file; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 -// USA -//----------------------------------------------------------------- -// altera message_off 10762 -// altera message_off 10240 - -module spdif -( - input clk_i, - input rst_i, - - // SPDIF bit output enable - // Single cycle pulse synchronous to clk_i which drives - // the output bit rate. - // For 44.1KHz, 44100×32×2×2 = 5,644,800Hz - // For 48KHz, 48000×32×2×2 = 6,144,000Hz - input bit_out_en_i, - - // Output - output spdif_o, - - // Audio interface (16-bit x 2 = RL) - input [31:0] sample_i, - output reg sample_req_o -); - -//----------------------------------------------------------------- -// Registers -//----------------------------------------------------------------- -reg [15:0] audio_sample_q; -reg [8:0] subframe_count_q; - -reg load_subframe_q; -reg [7:0] preamble_q; -wire [31:0] subframe_w; - -reg [5:0] bit_count_q; -reg bit_toggle_q; - -reg spdif_out_q; - -reg [5:0] parity_count_q; - -reg channel_status_bit_q; - -//----------------------------------------------------------------- -// Subframe Counter -//----------------------------------------------------------------- -always @ (posedge rst_i or posedge clk_i ) -begin - if (rst_i == 1'b1) - subframe_count_q <= 9'd0; - else if (load_subframe_q) - begin - // 192 frames (384 subframes) in an audio block - if (subframe_count_q == 9'd383) - subframe_count_q <= 9'd0; - else - subframe_count_q <= subframe_count_q + 9'd1; - end -end - -//----------------------------------------------------------------- -// Sample capture -//----------------------------------------------------------------- -reg [15:0] sample_buf_q; - -always @ (posedge rst_i or posedge clk_i ) -begin - if (rst_i == 1'b1) - begin - audio_sample_q <= 16'h0000; - sample_buf_q <= 16'h0000; - sample_req_o <= 1'b0; - end - else if (load_subframe_q) - begin - // Start of frame (first subframe)? - if (subframe_count_q[0] == 1'b0) - begin - // Use left sample - audio_sample_q <= sample_i[15:0]; - - // Store right sample - sample_buf_q <= sample_i[31:16]; - - // Request next sample - sample_req_o <= 1'b1; - end - else - begin - // Use right sample - audio_sample_q <= sample_buf_q; - - sample_req_o <= 1'b0; - end - end - else - sample_req_o <= 1'b0; -end - -// Timeslots 3 - 0 = Preamble -assign subframe_w[3:0] = 4'b0000; - -// Timeslots 7 - 4 = 24-bit audio LSB -assign subframe_w[7:4] = 4'b0000; - -// Timeslots 11 - 8 = 20-bit audio LSB -assign subframe_w[11:8] = 4'b0000; - -// Timeslots 27 - 12 = 16-bit audio -assign subframe_w[27:12] = audio_sample_q; - -// Timeslots 28 = Validity -assign subframe_w[28] = 1'b0; // Valid - -// Timeslots 29 = User bit -assign subframe_w[29] = 1'b0; - -// Timeslots 30 = Channel status bit -assign subframe_w[30] = channel_status_bit_q ; //was constant 1'b0 enabling copy-bit; - -// Timeslots 31 = Even Parity bit (31:4) -assign subframe_w[31] = 1'b0; - -//----------------------------------------------------------------- -// Preamble and Channel status bit -//----------------------------------------------------------------- -localparam PREAMBLE_Z = 8'b00010111; // "B" channel A data at start of block -localparam PREAMBLE_Y = 8'b00100111; // "W" channel B data -localparam PREAMBLE_X = 8'b01000111; // "M" channel A data not at start of block - -reg [7:0] preamble_r; -reg channel_status_bit_r; - -always @ * -begin - // Start of audio block? - // Z(B) - Left channel - if (subframe_count_q == 9'd0) - preamble_r = PREAMBLE_Z; // Z(B) - // Right Channel? - else if (subframe_count_q[0] == 1'b1) - preamble_r = PREAMBLE_Y; // Y(W) - // Left Channel (but not start of block)? - else - preamble_r = PREAMBLE_X; // X(M) - - if (subframe_count_q[8:1] == 8'd2) // frame 2 => subframes 4 and 5 => 0 = copy inhibited, 1 = copy permitted - channel_status_bit_r = 1'b1; - else if (subframe_count_q[8:1] == 8'd15) // frame 15 => 0 = no indication, 1 = original media - channel_status_bit_r = 1'b1; - else if (subframe_count_q[8:1] == 8'd25) // frame 24 to 27 => sample frequency, 0100 = 48kHz, 0000 = 44kHz (l2r) - channel_status_bit_r = 1'b1; - else - channel_status_bit_r = 1'b0; // everything else defaults to 0 -end - -always @ (posedge rst_i or posedge clk_i ) -begin - if (rst_i == 1'b1) - begin - preamble_q <= 8'h00; - channel_status_bit_q <= 1'b0; - end - else if (load_subframe_q) - begin - preamble_q <= preamble_r; - channel_status_bit_q <= channel_status_bit_r; - end -end - -//----------------------------------------------------------------- -// Parity Counter -//----------------------------------------------------------------- -always @ (posedge rst_i or posedge clk_i ) -begin - if (rst_i == 1'b1) - begin - parity_count_q <= 6'd0; - end - // Time to output a bit? - else if (bit_out_en_i) - begin - // Preamble bits? - if (bit_count_q < 6'd8) - begin - parity_count_q <= 6'd0; - end - // Normal timeslots - else if (bit_count_q < 6'd62) - begin - // On first pass through this timeslot, count number of high bits - if (bit_count_q[0] == 0 && subframe_w[bit_count_q / 2] == 1'b1) - parity_count_q <= parity_count_q + 6'd1; - end - end -end - -//----------------------------------------------------------------- -// Bit Counter -//----------------------------------------------------------------- -always @ (posedge rst_i or posedge clk_i) -begin - if (rst_i == 1'b1) - begin - bit_count_q <= 6'b0; - load_subframe_q <= 1'b1; - end - // Time to output a bit? - else if (bit_out_en_i) - begin - // 32 timeslots (x2 for double frequency) - if (bit_count_q == 6'd63) - begin - bit_count_q <= 6'd0; - load_subframe_q <= 1'b1; - end - else - begin - bit_count_q <= bit_count_q + 6'd1; - load_subframe_q <= 1'b0; - end - end - else - load_subframe_q <= 1'b0; -end - -//----------------------------------------------------------------- -// Bit half toggle -//----------------------------------------------------------------- -always @ (posedge rst_i or posedge clk_i) -if (rst_i == 1'b1) - bit_toggle_q <= 1'b0; -// Time to output a bit? -else if (bit_out_en_i) - bit_toggle_q <= ~bit_toggle_q; - -//----------------------------------------------------------------- -// Output bit (BMC encoded) -//----------------------------------------------------------------- -reg bit_r; - -always @ * -begin - bit_r = spdif_out_q; - - // Time to output a bit? - if (bit_out_en_i) - begin - // Preamble bits? - if (bit_count_q < 6'd8) - begin - bit_r = preamble_q[bit_count_q[2:0]]; - end - // Normal timeslots - else if (bit_count_q < 6'd62) - begin - if (subframe_w[bit_count_q / 2] == 1'b0) - begin - if (bit_toggle_q == 1'b0) - bit_r = ~spdif_out_q; - else - bit_r = spdif_out_q; - end - else - bit_r = ~spdif_out_q; - end - // Parity timeslot - else - begin - // Even number of high bits, make odd - if (parity_count_q[0] == 1'b0) - begin - if (bit_toggle_q == 1'b0) - bit_r = ~spdif_out_q; - else - bit_r = spdif_out_q; - end - else - bit_r = ~spdif_out_q; - end - end -end - -always @ (posedge rst_i or posedge clk_i ) -if (rst_i == 1'b1) - spdif_out_q <= 1'b0; -else - spdif_out_q <= bit_r; - -assign spdif_o = spdif_out_q; - -endmodule diff --git a/sys/sys.qip b/sys/sys.qip deleted file mode 100644 index ced8e8b..0000000 --- a/sys/sys.qip +++ /dev/null @@ -1,34 +0,0 @@ -set_global_assignment -name QIP_FILE [join [list $::quartus(qip_path) pll_q [regexp -inline {[0-9]+} $quartus(version)] .qip] {}] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sys_top.v ] -set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sys_top.sdc ] -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) ascal.vhd ] -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) pll_hdmi_adj.vhd ] -set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) math.sv ] -set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hq2x.sv ] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v ] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scanlines.v ] -set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) shadowmask.sv ] -set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_cleaner.sv ] -set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) gamma_corr.sv ] -set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_mixer.sv ] -set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_freak.sv ] -set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_freezer.sv ] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) arcade_video.v ] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v ] -set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vga_out.sv ] -set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) yc_out.sv ] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2c.v ] -set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) alsa.sv ] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2s.v ] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) spdif.v ] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) audio_out.v ] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) iir_filter.v ] -set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ltc2308.sv ] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sigma_delta_dac.v ] -set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) mt32pi.sv ] -set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) mcp23009.sv ] -set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) f2sdram_safe_terminator.sv ] -set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr_svc.sv ] -set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ] -set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sd_card.sv ] -set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hps_io.sv ] diff --git a/sys/sys.tcl b/sys/sys.tcl deleted file mode 100644 index 93b6247..0000000 --- a/sys/sys.tcl +++ /dev/null @@ -1,220 +0,0 @@ -set_global_assignment -name FAMILY "Cyclone V" -set_global_assignment -name DEVICE 5CSEBA6U23I7 -set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 - -#============================================================ -# ADC -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO -set_location_assignment PIN_U9 -to ADC_CONVST -set_location_assignment PIN_V10 -to ADC_SCK -set_location_assignment PIN_AC4 -to ADC_SDI -set_location_assignment PIN_AD4 -to ADC_SDO - -#============================================================ -# I2C LEDS/BUTTONS -#============================================================ -set_location_assignment PIN_U14 -to IO_SCL -set_location_assignment PIN_AG9 -to IO_SDA -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IO_S* -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to IO_S* -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to IO_S* - -#============================================================ -# USER PORT -#============================================================ -set_location_assignment PIN_AF17 -to USER_IO[6] -set_location_assignment PIN_AF15 -to USER_IO[5] -set_location_assignment PIN_AG16 -to USER_IO[4] -set_location_assignment PIN_AH11 -to USER_IO[3] -set_location_assignment PIN_AH12 -to USER_IO[2] -set_location_assignment PIN_AH9 -to USER_IO[1] -set_location_assignment PIN_AG11 -to USER_IO[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USER_IO[*] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to USER_IO[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to USER_IO[*] - -#============================================================ -# SDIO_CD or SPDIF_OUT -#============================================================ -set_location_assignment PIN_AH7 -to SDCD_SPDIF -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCD_SPDIF -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCD_SPDIF -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDCD_SPDIF - -#============================================================ -# SDRAM -#============================================================ -set_location_assignment PIN_Y11 -to SDRAM_A[0] -set_location_assignment PIN_AA26 -to SDRAM_A[1] -set_location_assignment PIN_AA13 -to SDRAM_A[2] -set_location_assignment PIN_AA11 -to SDRAM_A[3] -set_location_assignment PIN_W11 -to SDRAM_A[4] -set_location_assignment PIN_Y19 -to SDRAM_A[5] -set_location_assignment PIN_AB23 -to SDRAM_A[6] -set_location_assignment PIN_AC23 -to SDRAM_A[7] -set_location_assignment PIN_AC22 -to SDRAM_A[8] -set_location_assignment PIN_C12 -to SDRAM_A[9] -set_location_assignment PIN_AB26 -to SDRAM_A[10] -set_location_assignment PIN_AD17 -to SDRAM_A[11] -set_location_assignment PIN_D12 -to SDRAM_A[12] -set_location_assignment PIN_Y17 -to SDRAM_BA[0] -set_location_assignment PIN_AB25 -to SDRAM_BA[1] -set_location_assignment PIN_E8 -to SDRAM_DQ[0] -set_location_assignment PIN_V12 -to SDRAM_DQ[1] -set_location_assignment PIN_D11 -to SDRAM_DQ[2] -set_location_assignment PIN_W12 -to SDRAM_DQ[3] -set_location_assignment PIN_AH13 -to SDRAM_DQ[4] -set_location_assignment PIN_D8 -to SDRAM_DQ[5] -set_location_assignment PIN_AH14 -to SDRAM_DQ[6] -set_location_assignment PIN_AF7 -to SDRAM_DQ[7] -set_location_assignment PIN_AE24 -to SDRAM_DQ[8] -set_location_assignment PIN_AD23 -to SDRAM_DQ[9] -set_location_assignment PIN_AE6 -to SDRAM_DQ[10] -set_location_assignment PIN_AE23 -to SDRAM_DQ[11] -set_location_assignment PIN_AG14 -to SDRAM_DQ[12] -set_location_assignment PIN_AD5 -to SDRAM_DQ[13] -set_location_assignment PIN_AF4 -to SDRAM_DQ[14] -set_location_assignment PIN_AH3 -to SDRAM_DQ[15] -set_location_assignment PIN_AG13 -to SDRAM_DQML -set_location_assignment PIN_AF13 -to SDRAM_DQMH -set_location_assignment PIN_AD20 -to SDRAM_CLK -set_location_assignment PIN_AG10 -to SDRAM_CKE -set_location_assignment PIN_AA19 -to SDRAM_nWE -set_location_assignment PIN_AA18 -to SDRAM_nCAS -set_location_assignment PIN_Y18 -to SDRAM_nCS -set_location_assignment PIN_W14 -to SDRAM_nRAS - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_* -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_* -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_* -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] -set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*] -set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_* - -#============================================================ -# SPI SD -#============================================================ -set_location_assignment PIN_AE15 -to SD_SPI_CS -set_location_assignment PIN_AH8 -to SD_SPI_MISO -set_location_assignment PIN_AG8 -to SD_SPI_CLK -set_location_assignment PIN_U13 -to SD_SPI_MOSI -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SD_SPI* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_SPI* -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_SPI* - - -#============================================================ -# CLOCK -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 -set_location_assignment PIN_V11 -to FPGA_CLK1_50 -set_location_assignment PIN_Y13 -to FPGA_CLK2_50 -set_location_assignment PIN_E11 -to FPGA_CLK3_50 - -#============================================================ -# HDMI -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_* -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_D[*] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_DE -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_HS -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_VS -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_CLK -set_location_assignment PIN_U10 -to HDMI_I2C_SCL -set_location_assignment PIN_AA4 -to HDMI_I2C_SDA -set_location_assignment PIN_T13 -to HDMI_I2S -set_location_assignment PIN_T11 -to HDMI_LRCLK -set_location_assignment PIN_U11 -to HDMI_MCLK -set_location_assignment PIN_T12 -to HDMI_SCLK -set_location_assignment PIN_AG5 -to HDMI_TX_CLK -set_location_assignment PIN_AD19 -to HDMI_TX_DE -set_location_assignment PIN_AD12 -to HDMI_TX_D[0] -set_location_assignment PIN_AE12 -to HDMI_TX_D[1] -set_location_assignment PIN_W8 -to HDMI_TX_D[2] -set_location_assignment PIN_Y8 -to HDMI_TX_D[3] -set_location_assignment PIN_AD11 -to HDMI_TX_D[4] -set_location_assignment PIN_AD10 -to HDMI_TX_D[5] -set_location_assignment PIN_AE11 -to HDMI_TX_D[6] -set_location_assignment PIN_Y5 -to HDMI_TX_D[7] -set_location_assignment PIN_AF10 -to HDMI_TX_D[8] -set_location_assignment PIN_Y4 -to HDMI_TX_D[9] -set_location_assignment PIN_AE9 -to HDMI_TX_D[10] -set_location_assignment PIN_AB4 -to HDMI_TX_D[11] -set_location_assignment PIN_AE7 -to HDMI_TX_D[12] -set_location_assignment PIN_AF6 -to HDMI_TX_D[13] -set_location_assignment PIN_AF8 -to HDMI_TX_D[14] -set_location_assignment PIN_AF5 -to HDMI_TX_D[15] -set_location_assignment PIN_AE4 -to HDMI_TX_D[16] -set_location_assignment PIN_AH2 -to HDMI_TX_D[17] -set_location_assignment PIN_AH4 -to HDMI_TX_D[18] -set_location_assignment PIN_AH5 -to HDMI_TX_D[19] -set_location_assignment PIN_AH6 -to HDMI_TX_D[20] -set_location_assignment PIN_AG6 -to HDMI_TX_D[21] -set_location_assignment PIN_AF9 -to HDMI_TX_D[22] -set_location_assignment PIN_AE8 -to HDMI_TX_D[23] -set_location_assignment PIN_T8 -to HDMI_TX_HS -set_location_assignment PIN_AF11 -to HDMI_TX_INT -set_location_assignment PIN_V13 -to HDMI_TX_VS - -#============================================================ -# KEY -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] -set_location_assignment PIN_AH17 -to KEY[0] -set_location_assignment PIN_AH16 -to KEY[1] - -#============================================================ -# LED -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] -set_location_assignment PIN_W15 -to LED[0] -set_location_assignment PIN_AA24 -to LED[1] -set_location_assignment PIN_V16 -to LED[2] -set_location_assignment PIN_V15 -to LED[3] -set_location_assignment PIN_AF26 -to LED[4] -set_location_assignment PIN_AE26 -to LED[5] -set_location_assignment PIN_Y16 -to LED[6] -set_location_assignment PIN_AA23 -to LED[7] - -#============================================================ -# SW -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] -set_location_assignment PIN_Y24 -to SW[0] -set_location_assignment PIN_W24 -to SW[1] -set_location_assignment PIN_W21 -to SW[2] -set_location_assignment PIN_W20 -to SW[3] - -set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALSPIMASTER_X52_Y72_N111 -entity sys_top -to spi -set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALUART_X52_Y67_N111 -entity sys_top -to uart -set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALI2C_X52_Y60_N111 -entity sys_top -to hdmi_i2c - -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl" - -set_global_assignment -name CDF_FILE jtag.cdf -set_global_assignment -name QIP_FILE sys/sys.qip - diff --git a/sys/sys_analog.tcl b/sys/sys_analog.tcl deleted file mode 100644 index 692043f..0000000 --- a/sys/sys_analog.tcl +++ /dev/null @@ -1,71 +0,0 @@ -#============================================================ -# SDIO -#============================================================ -set_location_assignment PIN_AF25 -to SDIO_DAT[0] -set_location_assignment PIN_AF23 -to SDIO_DAT[1] -set_location_assignment PIN_AD26 -to SDIO_DAT[2] -set_location_assignment PIN_AF28 -to SDIO_DAT[3] -set_location_assignment PIN_AF27 -to SDIO_CMD -set_location_assignment PIN_AH26 -to SDIO_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_* - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_* -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD - -#============================================================ -# VGA -#============================================================ -set_location_assignment PIN_AE17 -to VGA_R[0] -set_location_assignment PIN_AE20 -to VGA_R[1] -set_location_assignment PIN_AF20 -to VGA_R[2] -set_location_assignment PIN_AH18 -to VGA_R[3] -set_location_assignment PIN_AH19 -to VGA_R[4] -set_location_assignment PIN_AF21 -to VGA_R[5] - -set_location_assignment PIN_AE19 -to VGA_G[0] -set_location_assignment PIN_AG15 -to VGA_G[1] -set_location_assignment PIN_AF18 -to VGA_G[2] -set_location_assignment PIN_AG18 -to VGA_G[3] -set_location_assignment PIN_AG19 -to VGA_G[4] -set_location_assignment PIN_AG20 -to VGA_G[5] - -set_location_assignment PIN_AG21 -to VGA_B[0] -set_location_assignment PIN_AA20 -to VGA_B[1] -set_location_assignment PIN_AE22 -to VGA_B[2] -set_location_assignment PIN_AF22 -to VGA_B[3] -set_location_assignment PIN_AH23 -to VGA_B[4] -set_location_assignment PIN_AH21 -to VGA_B[5] - -set_location_assignment PIN_AH22 -to VGA_HS -set_location_assignment PIN_AG24 -to VGA_VS - -set_location_assignment PIN_AH27 -to VGA_EN -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_* -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_* - -#============================================================ -# AUDIO -#============================================================ -set_location_assignment PIN_AC24 -to AUDIO_L -set_location_assignment PIN_AE25 -to AUDIO_R -set_location_assignment PIN_AG26 -to AUDIO_SPDIF -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_* -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_* - -#============================================================ -# I/O #1 -#============================================================ -set_location_assignment PIN_Y15 -to LED_USER -set_location_assignment PIN_AA15 -to LED_HDD -set_location_assignment PIN_AG28 -to LED_POWER - -set_location_assignment PIN_AH24 -to BTN_USER -set_location_assignment PIN_AG25 -to BTN_OSD -set_location_assignment PIN_AG23 -to BTN_RESET - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_* -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_* diff --git a/sys/sys_dual_sdram.tcl b/sys/sys_dual_sdram.tcl deleted file mode 100644 index cf90eab..0000000 --- a/sys/sys_dual_sdram.tcl +++ /dev/null @@ -1,51 +0,0 @@ -#============================================================ -# Secondary SDRAM -#============================================================ -set_location_assignment PIN_Y15 -to SDRAM2_DQ[0] -set_location_assignment PIN_AC24 -to SDRAM2_DQ[1] -set_location_assignment PIN_AA15 -to SDRAM2_DQ[2] -set_location_assignment PIN_AD26 -to SDRAM2_DQ[3] -set_location_assignment PIN_AG28 -to SDRAM2_DQ[4] -set_location_assignment PIN_AF28 -to SDRAM2_DQ[5] -set_location_assignment PIN_AE25 -to SDRAM2_DQ[6] -set_location_assignment PIN_AF27 -to SDRAM2_DQ[7] -set_location_assignment PIN_AG26 -to SDRAM2_DQ[14] -set_location_assignment PIN_AH27 -to SDRAM2_DQ[15] - -set_location_assignment PIN_AG25 -to SDRAM2_DQ[13] -set_location_assignment PIN_AH26 -to SDRAM2_DQ[12] -set_location_assignment PIN_AH24 -to SDRAM2_DQ[11] -set_location_assignment PIN_AF25 -to SDRAM2_DQ[10] -set_location_assignment PIN_AG23 -to SDRAM2_DQ[9] -set_location_assignment PIN_AF23 -to SDRAM2_DQ[8] -set_location_assignment PIN_AG24 -to SDRAM2_A[12] -set_location_assignment PIN_AH22 -to SDRAM2_CLK -set_location_assignment PIN_AH21 -to SDRAM2_A[9] -set_location_assignment PIN_AG21 -to SDRAM2_A[11] -set_location_assignment PIN_AH23 -to SDRAM2_A[7] -set_location_assignment PIN_AA20 -to SDRAM2_A[8] -set_location_assignment PIN_AF22 -to SDRAM2_A[5] -set_location_assignment PIN_AE22 -to SDRAM2_A[6] -set_location_assignment PIN_AG20 -to SDRAM2_nWE -set_location_assignment PIN_AF21 -to SDRAM2_A[4] - -set_location_assignment PIN_AG19 -to SDRAM2_nCAS -set_location_assignment PIN_AH19 -to SDRAM2_nRAS -set_location_assignment PIN_AG18 -to SDRAM2_nCS -set_location_assignment PIN_AH18 -to SDRAM2_BA[0] -set_location_assignment PIN_AF18 -to SDRAM2_BA[1] -set_location_assignment PIN_AF20 -to SDRAM2_A[10] -set_location_assignment PIN_AG15 -to SDRAM2_A[0] -set_location_assignment PIN_AE20 -to SDRAM2_A[1] -set_location_assignment PIN_AE19 -to SDRAM2_A[2] -set_location_assignment PIN_AE17 -to SDRAM2_A[3] - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM2_* -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM2_* -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM2_* -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM2_DQ[*] -set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM2_DQ[*] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDRAM2_DQ[*] -set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM2_* - -set_global_assignment -name VERILOG_MACRO "MISTER_DUAL_SDRAM=1" diff --git a/sys/sys_top.sdc b/sys/sys_top.sdc deleted file mode 100644 index ac21334..0000000 --- a/sys/sys_top.sdc +++ /dev/null @@ -1,77 +0,0 @@ -# Specify root clocks -create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50] -create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50] -create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50] -create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk] -create_clock -period "100.0 MHz" [get_pins -compatibility_mode spi|sclk_out] -name spi_sck -create_clock -period "10.0 MHz" [get_pins -compatibility_mode hdmi_i2c|out_clk] -name hdmi_sck - -derive_pll_clocks -derive_clock_uncertainty - -# Decouple different clock groups (to simplify routing) -set_clock_groups -exclusive \ - -group [get_clocks { *|pll|pll_inst|altera_pll_i|*[*].*|divclk}] \ - -group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|*[0].*|divclk}] \ - -group [get_clocks { pll_audio|pll_audio_inst|altera_pll_i|*[0].*|divclk}] \ - -group [get_clocks { spi_sck}] \ - -group [get_clocks { hdmi_sck}] \ - -group [get_clocks { *|h2f_user0_clk}] \ - -group [get_clocks { FPGA_CLK1_50 }] \ - -group [get_clocks { FPGA_CLK2_50 }] \ - -group [get_clocks { FPGA_CLK3_50 }] - -set_false_path -from [get_ports {KEY*}] -set_false_path -from [get_ports {BTN_*}] -set_false_path -to [get_ports {LED_*}] -set_false_path -to [get_ports {VGA_*}] -set_false_path -from [get_ports {VGA_EN}] -set_false_path -to [get_ports {AUDIO_SPDIF}] -set_false_path -to [get_ports {AUDIO_L}] -set_false_path -to [get_ports {AUDIO_R}] -set_false_path -from {get_ports {SW[*]}} -set_false_path -to {cfg[*]} -set_false_path -from {cfg[*]} -set_false_path -from {VSET[*]} -set_false_path -to {wcalc[*] hcalc[*]} -set_false_path -to {hdmi_width[*] hdmi_height[*]} -set_false_path -to {deb_* btn_en btn_up} - -set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2 -set_multicycle_path -to {*_osd|osd_vcnt*} -hold 1 - -set_false_path -to {*_osd|v_cnt*} -set_false_path -to {*_osd|v_osd_start*} -set_false_path -to {*_osd|v_info_start*} -set_false_path -to {*_osd|h_osd_start*} -set_false_path -from {*_osd|v_osd_start*} -set_false_path -from {*_osd|v_info_start*} -set_false_path -from {*_osd|h_osd_start*} -set_false_path -from {*_osd|rot*} -set_false_path -from {*_osd|dsp_width*} -set_false_path -to {*_osd|half} - -set_false_path -to {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]} -set_false_path -from {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]} -set_false_path -to {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] LFB_HMIN[*] LFB_HMAX[*] LFB_VMIN[*] LFB_VMAX[*]} -set_false_path -from {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] LFB_HMIN[*] LFB_HMAX[*] LFB_VMIN[*] LFB_VMAX[*]} -set_false_path -to {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]} -set_false_path -from {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]} -set_false_path -from {aflt_* acx* acy* areset* arc*} -set_false_path -from {arx* ary*} -set_false_path -from {vs_line*} -set_false_path -from {ColorBurst_Range* PhaseInc* pal_en cvbs yc_en} - -set_false_path -from {ascal|o_ihsize*} -set_false_path -from {ascal|o_ivsize*} -set_false_path -from {ascal|o_format*} -set_false_path -from {ascal|o_hdown} -set_false_path -from {ascal|o_vdown} -set_false_path -from {ascal|o_hmin* ascal|o_hmax* ascal|o_vmin* ascal|o_vmax* ascal|o_vrrmax* ascal|o_vrr} -set_false_path -from {ascal|o_hdisp* ascal|o_vdisp*} -set_false_path -from {ascal|o_htotal* ascal|o_vtotal*} -set_false_path -from {ascal|o_hsstart* ascal|o_vsstart* ascal|o_hsend* ascal|o_vsend*} -set_false_path -from {ascal|o_hsize* ascal|o_vsize*} - -set_false_path -from {mcp23009|flg_*} -set_false_path -to {sysmem|fpga_interfaces|clocks_resets*} diff --git a/sys/sys_top.v b/sys/sys_top.v deleted file mode 100644 index 65129eb..0000000 --- a/sys/sys_top.v +++ /dev/null @@ -1,1903 +0,0 @@ -//============================================================================ -// -// MiSTer hardware abstraction module -// (c)2017-2020 Alexey Melnikov -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -// -//============================================================================ - -module sys_top -( - /////////// CLOCK ////////// - input FPGA_CLK1_50, - input FPGA_CLK2_50, - input FPGA_CLK3_50, - - //////////// HDMI ////////// - output HDMI_I2C_SCL, - inout HDMI_I2C_SDA, - - output HDMI_MCLK, - output HDMI_SCLK, - output HDMI_LRCLK, - output HDMI_I2S, - - output HDMI_TX_CLK, - output HDMI_TX_DE, - output [23:0] HDMI_TX_D, - output HDMI_TX_HS, - output HDMI_TX_VS, - - input HDMI_TX_INT, - - //////////// SDR /////////// - output [12:0] SDRAM_A, - inout [15:0] SDRAM_DQ, - output SDRAM_DQML, - output SDRAM_DQMH, - output SDRAM_nWE, - output SDRAM_nCAS, - output SDRAM_nRAS, - output SDRAM_nCS, - output [1:0] SDRAM_BA, - output SDRAM_CLK, - output SDRAM_CKE, - -`ifdef MISTER_DUAL_SDRAM - ////////// SDR #2 ////////// - output [12:0] SDRAM2_A, - inout [15:0] SDRAM2_DQ, - output SDRAM2_nWE, - output SDRAM2_nCAS, - output SDRAM2_nRAS, - output SDRAM2_nCS, - output [1:0] SDRAM2_BA, - output SDRAM2_CLK, - -`else - //////////// VGA /////////// - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - inout VGA_HS, - output VGA_VS, - input VGA_EN, // active low - - /////////// AUDIO ////////// - output AUDIO_L, - output AUDIO_R, - output AUDIO_SPDIF, - - //////////// SDIO /////////// - inout [3:0] SDIO_DAT, - inout SDIO_CMD, - output SDIO_CLK, - - //////////// I/O /////////// - output LED_USER, - output LED_HDD, - output LED_POWER, - input BTN_USER, - input BTN_OSD, - input BTN_RESET, -`endif - - ////////// I/O ALT ///////// - output SD_SPI_CS, - input SD_SPI_MISO, - output SD_SPI_CLK, - output SD_SPI_MOSI, - - inout SDCD_SPDIF, - output IO_SCL, - inout IO_SDA, - - ////////// ADC ////////////// - output ADC_SCK, - input ADC_SDO, - output ADC_SDI, - output ADC_CONVST, - - ////////// MB KEY /////////// - input [1:0] KEY, - - ////////// MB SWITCH //////// - input [3:0] SW, - - ////////// MB LED /////////// - output [7:0] LED, - - ///////// USER IO /////////// - inout [6:0] USER_IO -); - -////////////////////// Secondary SD /////////////////////////////////// -wire SD_CS, SD_CLK, SD_MOSI, SD_MISO, SD_CD; - -`ifndef MISTER_DUAL_SDRAM - assign SD_CD = mcp_en ? mcp_sdcd : SDCD_SPDIF; - assign SD_MISO = SD_CD | (mcp_en ? SD_SPI_MISO : (VGA_EN | SDIO_DAT[0])); - assign SD_SPI_CS = mcp_en ? (mcp_sdcd ? 1'bZ : SD_CS) : (sog & ~cs1 & ~VGA_EN) ? 1'b1 : 1'bZ; - assign SD_SPI_CLK = (~mcp_en | mcp_sdcd) ? 1'bZ : SD_CLK; - assign SD_SPI_MOSI = (~mcp_en | mcp_sdcd) ? 1'bZ : SD_MOSI; - assign {SDIO_CLK,SDIO_CMD,SDIO_DAT} = av_dis ? 6'bZZZZZZ : (mcp_en | (SDCD_SPDIF & ~SW[2])) ? {vga_g,vga_r,vga_b} : {SD_CLK,SD_MOSI,SD_CS,3'bZZZ}; -`else - assign SD_CD = mcp_sdcd; - assign SD_MISO = mcp_sdcd | SD_SPI_MISO; - assign SD_SPI_CS = mcp_sdcd ? 1'bZ : SD_CS; - assign SD_SPI_CLK = mcp_sdcd ? 1'bZ : SD_CLK; - assign SD_SPI_MOSI = mcp_sdcd ? 1'bZ : SD_MOSI; -`endif - -////////////////////// LEDs/Buttons /////////////////////////////////// - -reg [7:0] led_overtake = 0; -reg [7:0] led_state = 0; - -wire led_p = led_power[1] ? ~led_power[0] : 1'b0; -wire led_d = led_disk[1] ? ~led_disk[0] : ~(led_disk[0] | gp_out[29]); -wire led_u = ~led_user; -wire led_locked; - -//LEDs on de10-nano board -assign LED = (led_overtake & led_state) | (~led_overtake & {1'b0,led_locked,1'b0, ~led_p, 1'b0, ~led_d, 1'b0, ~led_u}); - -wire [2:0] mcp_btn; -wire mcp_sdcd; -wire mcp_en; -wire mcp_mode; -mcp23009 mcp23009 -( - .clk(FPGA_CLK2_50), - - .btn(mcp_btn), - .led({led_p, led_d, led_u}), - .flg_sd_cd(mcp_sdcd), - .flg_present(mcp_en), - .flg_mode(mcp_mode), - - .scl(IO_SCL), - .sda(IO_SDA) -); - -wire io_dig = mcp_en ? mcp_mode : SW[3]; - -`ifndef MISTER_DUAL_SDRAM - wire av_dis = io_dig | VGA_EN; - assign LED_POWER = av_dis ? 1'bZ : mcp_en ? de1 : led_p ? 1'bZ : 1'b0; - assign LED_HDD = av_dis ? 1'bZ : mcp_en ? (sog & ~cs1) : led_d ? 1'bZ : 1'b0; - //assign LED_USER = av_dis ? 1'bZ : mcp_en ? ~vga_tx_clk : led_u ? 1'bZ : 1'b0; - assign LED_USER = VGA_TX_CLK; - wire BTN_DIS = VGA_EN; -`else - wire BTN_RESET = SDRAM2_DQ[9]; - wire BTN_OSD = SDRAM2_DQ[13]; - wire BTN_USER = SDRAM2_DQ[11]; - wire BTN_DIS = SDRAM2_DQ[15]; -`endif - -reg BTN_EN = 0; -reg [25:0] btn_timeout = 0; -initial btn_timeout = 0; -always @(posedge FPGA_CLK2_50) begin - reg btn_up = 0; - reg btn_en = 0; - - btn_up <= BTN_RESET & BTN_OSD & BTN_USER; - if(~reset & btn_up & ~&btn_timeout) btn_timeout <= btn_timeout + 1'd1; - btn_en <= ~BTN_DIS; - BTN_EN <= &btn_timeout & btn_en; -end - -wire btn_r = (mcp_en | SW[3]) ? mcp_btn[1] : (BTN_EN & ~BTN_RESET); -wire btn_o = (mcp_en | SW[3]) ? mcp_btn[2] : (BTN_EN & ~BTN_OSD ); -wire btn_u = (mcp_en | SW[3]) ? mcp_btn[0] : (BTN_EN & ~BTN_USER ); - -reg btn_user, btn_osd; -always @(posedge FPGA_CLK2_50) begin - integer div; - reg [7:0] deb_user; - reg [7:0] deb_osd; - - div <= div + 1'b1; - if(div > 100000) div <= 0; - - if(!div) begin - deb_user <= {deb_user[6:0], btn_u | ~KEY[1]}; - if(&deb_user) btn_user <= 1; - if(!deb_user) btn_user <= 0; - - deb_osd <= {deb_osd[6:0], btn_o | ~KEY[0]}; - if(&deb_osd) btn_osd <= 1; - if(!deb_osd) btn_osd <= 0; - end -end - -///////////////////////// HPS I/O ///////////////////////////////////// - -// gp_in[31] = 0 - quick flag that FPGA is initialized (HPS reads 1 when FPGA is not in user mode) -// used to avoid lockups while JTAG loading -wire [31:0] gp_in = {1'b0, btn_user | btn[1], btn_osd | btn[0], io_dig, 8'd0, io_ver, io_ack, io_wide, io_dout | io_dout_sys}; -wire [31:0] gp_out; - -wire [1:0] io_ver = 1; // 0 - obsolete. 1 - optimized HPS I/O. 2,3 - reserved for future. -wire io_wait; -wire io_wide; -wire [15:0] io_dout; -wire [15:0] io_din = gp_outr[15:0]; -wire io_clk = gp_outr[17]; -wire io_ss0 = gp_outr[18]; -wire io_ss1 = gp_outr[19]; -wire io_ss2 = gp_outr[20]; - -`ifndef MISTER_DEBUG_NOHDMI - wire io_osd_hdmi = io_ss1 & ~io_ss0; -`endif - -wire io_fpga = ~io_ss1 & io_ss0; -wire io_uio = ~io_ss1 & io_ss2; - -reg io_ack; -reg rack; -wire io_strobe = ~rack & io_clk; - -always @(posedge clk_sys) begin - if(~(io_wait | vs_wait) | io_strobe) begin - rack <= io_clk; - io_ack <= rack; - end -end - -reg [31:0] gp_outr; -always @(posedge clk_sys) begin - reg [31:0] gp_outd; - gp_outr <= gp_outd; - gp_outd <= gp_out; -end - -`ifdef MISTER_DUAL_SDRAM - wire [7:0] core_type = 'hA8; // generic core, dual SDRAM. -`else - wire [7:0] core_type = 'hA4; // generic core. -`endif - -// HPS will not communicate to core if magic is different -wire [31:0] core_magic = {24'h5CA623, core_type}; - -cyclonev_hps_interface_mpu_general_purpose h2f_gp -( - .gp_in({~gp_out[31] ? core_magic : gp_in}), - .gp_out(gp_out) -); - - -reg [15:0] cfg; -reg cfg_set = 0; - -`ifdef MISTER_DEBUG_NOHDMI - wire vga_fb = 0; - wire direct_video = 1; -`else - wire vga_fb = cfg[12] | vga_force_scaler; - wire direct_video = cfg[10]; -`endif - -wire audio_96k = cfg[6]; -wire csync_en = cfg[3]; -wire io_osd_vga = io_ss1 & ~io_ss2; -`ifndef MISTER_DUAL_SDRAM - wire ypbpr_en = cfg[5]; - wire sog = cfg[9]; - `ifdef MISTER_DEBUG_NOHDMI - wire vga_scaler = 0; - `else - wire vga_scaler = cfg[2] | vga_force_scaler; - `endif -`endif - -reg cfg_custom_t = 0; -reg [5:0] cfg_custom_p1; -reg [31:0] cfg_custom_p2; - -reg [4:0] vol_att; -initial vol_att = 5'b11111; - -reg [11:0] coef_addr; -reg [9:0] coef_data; -reg coef_wr = 0; - -wire[12:0] ARX, ARY; -reg [11:0] VSET = 0, HSET = 0; -reg FREESCALE = 0; -reg [2:0] scaler_flt; -reg lowlat = 0; -reg cfg_done = 0; - -reg vs_wait = 0; -reg [11:0] vs_line = 0; - -reg scaler_out = 0; -reg vrr_mode = 0; - -reg [31:0] aflt_rate = 7056000; -reg [39:0] acx = 4258969; -reg [7:0] acx0 = 3; -reg [7:0] acx1 = 3; -reg [7:0] acx2 = 1; -reg [23:0] acy0 = -24'd6216759; -reg [23:0] acy1 = 24'd6143386; -reg [23:0] acy2 = -24'd2023767; -reg areset = 0; -reg [12:0] arc1x = 0; -reg [12:0] arc1y = 0; -reg [12:0] arc2x = 0; -reg [12:0] arc2y = 0; -reg [15:0] io_dout_sys; - -always@(posedge clk_sys) begin - reg [7:0] cmd; - reg has_cmd; - reg [7:0] cnt = 0; - reg vs_d0,vs_d1,vs_d2; - reg [4:0] acx_att; - reg [7:0] fb_crc; - - coef_wr <= 0; - -`ifndef MISTER_DEBUG_NOHDMI - shadowmask_wr <= 0; -`endif - - if(~io_uio) begin - has_cmd <= 0; - cmd <= 0; - areset <= 0; - acx_att <= 0; - acx <= acx >> acx_att; - io_dout_sys <= 0; - end - else - if(io_strobe) begin - io_dout_sys <= 0; - if(!has_cmd) begin - has_cmd <= 1; - cmd <= io_din[7:0]; - cnt <= 0; - if(io_din[7:0] == 'h30) vs_wait <= 1; - if(io_din[7:0] == 'h39) begin - aflt_rate <= 7056000; - acx <= 4258969; - acx0 <= 3; - acx1 <= 3; - acx2 <= 1; - acy0 <= -24'd6216759; - acy1 <= 24'd6143386; - acy2 <= -24'd2023767; - areset <= 1; - end - if(io_din[7:0] == 'h20) io_dout_sys <= 'b11; -`ifndef MISTER_DEBUG_NOHDMI - if(io_din[7:0] == 'h40) io_dout_sys <= fb_crc; -`endif - end - else begin - cnt <= cnt + 1'd1; - if(cmd == 1) begin - cfg <= io_din; - cfg_set <= 1; - scaler_out <= 1; - end - if(cmd == 'h20) begin - cfg_set <= 0; - if(cnt<8) begin - case(cnt[2:0]) - 0: {HDMI_PR,vrr_mode,WIDTH} <= {io_din[15:14], io_din[11:0]}; - 1: HFP <= io_din[11:0]; - 2: HS <= {io_din[15], io_din[11:0]}; - 3: HBP <= io_din[11:0]; - 4: HEIGHT <= io_din[11:0]; - 5: VFP <= io_din[11:0]; - 6: VS <= {io_din[15],io_din[11:0]}; - 7: VBP <= io_din[11:0]; - endcase -`ifndef MISTER_DEBUG_NOHDMI - if(cnt == 1) begin - cfg_custom_p1 <= 0; - cfg_custom_p2 <= 0; - cfg_custom_t <= ~cfg_custom_t; - end - end - else begin - if(cnt[1:0]==0) cfg_custom_p1 <= io_din[5:0]; - if(cnt[1:0]==1) cfg_custom_p2[15:0] <= io_din; - if(cnt[1:0]==2) begin - cfg_custom_p2[31:16] <= io_din; - cfg_custom_t <= ~cfg_custom_t; - cnt[2:0] <= 3'b100; - end - if(cnt == 8) {lowlat,cfg_done} <= {io_din[15],1'b1}; -`endif - end - end - if(cmd == 'h2F) begin - case(cnt[3:0]) - 0: {LFB_EN,LFB_FLT,LFB_FMT} <= {io_din[15], io_din[14], io_din[5:0]}; - 1: LFB_BASE[15:0] <= io_din[15:0]; - 2: LFB_BASE[31:16] <= io_din[15:0]; - 3: LFB_WIDTH <= io_din[11:0]; - 4: LFB_HEIGHT <= io_din[11:0]; - 5: LFB_HMIN <= io_din[11:0]; - 6: LFB_HMAX <= io_din[11:0]; - 7: LFB_VMIN <= io_din[11:0]; - 8: LFB_VMAX <= io_din[11:0]; - 9: LFB_STRIDE <= io_din[13:0]; - endcase - end - if(cmd == 'h25) {led_overtake, led_state} <= io_din; - if(cmd == 'h26) vol_att <= io_din[4:0]; - if(cmd == 'h27) VSET <= io_din[11:0]; - if(cmd == 'h2A) begin - if(cnt[0]) {coef_wr,coef_data} <= {1'b1,io_din[9:0]}; - else coef_addr <= io_din[11:0]; - end - if(cmd == 'h2B) scaler_flt <= io_din[2:0]; - if(cmd == 'h37) {FREESCALE,HSET} <= {io_din[15],io_din[11:0]}; - if(cmd == 'h38) vs_line <= io_din[11:0]; - if(cmd == 'h39) begin - case(cnt[3:0]) - 0: acx_att <= io_din[4:0]; - 1: aflt_rate[15:0] <= io_din; - 2: aflt_rate[31:16] <= io_din; - 3: acx[15:0] <= io_din; - 4: acx[31:16] <= io_din; - 5: acx[39:32] <= io_din[7:0]; - 6: acx0 <= io_din[7:0]; - 7: acx1 <= io_din[7:0]; - 8: acx2 <= io_din[7:0]; - 9: acy0[15:0] <= io_din; - 10: acy0[23:16] <= io_din[7:0]; - 11: acy1[15:0] <= io_din; - 12: acy1[23:16] <= io_din[7:0]; - 13: acy2[15:0] <= io_din; - 14: acy2[23:16] <= io_din[7:0]; - endcase - end - if(cmd == 'h3A) begin - case(cnt[3:0]) - 0: arc1x <= io_din[12:0]; - 1: arc1y <= io_din[12:0]; - 2: arc2x <= io_din[12:0]; - 3: arc2y <= io_din[12:0]; - endcase - end -`ifndef MISTER_DEBUG_NOHDMI - if(cmd == 'h3E) {shadowmask_wr,shadowmask_data} <= {1'b1, io_din}; - if(cmd == 'h40) begin - case(cnt[3:0]) - 0: io_dout_sys <= {arxy, arx}; - 1: io_dout_sys <= {arxy, ary}; - 2: io_dout_sys <= {LFB_EN, FB_EN, FB_FMT}; - 3: io_dout_sys <= FB_WIDTH; - 4: io_dout_sys <= FB_HEIGHT; - 5: io_dout_sys <= FB_BASE[15:0]; - 6: io_dout_sys <= FB_BASE[31:16]; - 7: io_dout_sys <= FB_STRIDE; - endcase - end -`endif -`ifndef MISTER_DISABLE_YC - if(cmd == 'h41) begin - case(cnt[3:0]) - 0: {pal_en,cvbs,yc_en} <= io_din[2:0]; - 1: PhaseInc[15:0] <= io_din; - 2: PhaseInc[31:16] <= io_din; - 3: PhaseInc[39:32] <= io_din[7:0]; - 4: ColorBurst_Range[15:0] <= io_din; - 5: ColorBurst_Range[16] <= io_din[0]; - endcase - end -`endif - end - end - -`ifndef MISTER_DEBUG_NOHDMI - fb_crc <= {LFB_EN, FB_EN, FB_FMT} - ^ FB_WIDTH[7:0] ^ FB_WIDTH[11:8] - ^ FB_HEIGHT[7:0] ^ FB_HEIGHT[11:8] - ^ arx[7:0] ^ arx[11:8] ^ arxy - ^ ary[7:0] ^ ary[11:8]; -`endif - - vs_d0 <= HDMI_TX_VS; - if(vs_d0 == HDMI_TX_VS) vs_d1 <= vs_d0; - - vs_d2 <= vs_d1; - if(~vs_d2 & vs_d1) vs_wait <= 0; -end - -cyclonev_hps_interface_peripheral_uart uart -( - .ri(0), - .dsr(uart_dsr), - .dcd(uart_dsr), - .dtr(uart_dtr), - - .cts(uart_cts), - .rts(uart_rts), - .rxd(uart_rxd), - .txd(uart_txd) -); - -wire [63:0] f2h_irq = {video_sync,HDMI_TX_VS}; -cyclonev_hps_interface_interrupts interrupts -( - .irq(f2h_irq) -); - -/////////////////////////// RESET /////////////////////////////////// - -reg reset_req = 0; -always @(posedge FPGA_CLK2_50) begin - reg [1:0] resetd, resetd2; - reg old_reset; - - //latch the reset - old_reset <= reset; - if(~old_reset & reset) reset_req <= 1; - - //special combination to set/clear the reset - //preventing of accidental reset control - if(resetd==1) reset_req <= 1; - if(resetd==2 && resetd2==0) reset_req <= 0; - - resetd <= gp_out[31:30]; - resetd2 <= resetd; -end - -//////////////////// SYSTEM MEMORY & SCALER ///////////////////////// - -wire reset; -wire clk_100m; - -sysmem_lite sysmem -( - //Reset/Clock - .reset_core_req(reset_req), - .reset_out(reset), - .clock(clk_100m), - - //DE10-nano has no reset signal on GPIO, so core has to emulate cold reset button. - .reset_hps_cold_req(btn_r), - - //64-bit DDR3 RAM access - .ram1_clk(ram_clk), - .ram1_address(ram_address), - .ram1_burstcount(ram_burstcount), - .ram1_waitrequest(ram_waitrequest), - .ram1_readdata(ram_readdata), - .ram1_readdatavalid(ram_readdatavalid), - .ram1_read(ram_read), - .ram1_writedata(ram_writedata), - .ram1_byteenable(ram_byteenable), - .ram1_write(ram_write), - - //64-bit DDR3 RAM access - .ram2_clk(clk_audio), - .ram2_address(ram2_address), - .ram2_burstcount(ram2_burstcount), - .ram2_waitrequest(ram2_waitrequest), - .ram2_readdata(ram2_readdata), - .ram2_readdatavalid(ram2_readdatavalid), - .ram2_read(ram2_read), - .ram2_writedata(ram2_writedata), - .ram2_byteenable(ram2_byteenable), - .ram2_write(ram2_write), - - //128-bit DDR3 RAM access - // HDMI frame buffer - .vbuf_clk(clk_100m), - .vbuf_address(vbuf_address), - .vbuf_burstcount(vbuf_burstcount), - .vbuf_waitrequest(vbuf_waitrequest), - .vbuf_writedata(vbuf_writedata), - .vbuf_byteenable(vbuf_byteenable), - .vbuf_write(vbuf_write), - .vbuf_readdata(vbuf_readdata), - .vbuf_readdatavalid(vbuf_readdatavalid), - .vbuf_read(vbuf_read) -); - -wire [28:0] ram2_address; -wire [7:0] ram2_burstcount; -wire [7:0] ram2_byteenable; -wire ram2_waitrequest; -wire [63:0] ram2_readdata; -wire [63:0] ram2_writedata; -wire ram2_readdatavalid; -wire ram2_read; -wire ram2_write; -wire [7:0] ram2_bcnt; - -ddr_svc ddr_svc -( - .clk(clk_audio), - - .ram_waitrequest(ram2_waitrequest), - .ram_burstcnt(ram2_burstcount), - .ram_addr(ram2_address), - .ram_readdata(ram2_readdata), - .ram_read_ready(ram2_readdatavalid), - .ram_read(ram2_read), - .ram_writedata(ram2_writedata), - .ram_byteenable(ram2_byteenable), - .ram_write(ram2_write), - .ram_bcnt(ram2_bcnt), - -`ifndef MISTER_DISABLE_ALSA - .ch0_addr(alsa_address), - .ch0_burst(1), - .ch0_data(alsa_readdata), - .ch0_req(alsa_req), - .ch0_ready(alsa_ready), -`endif - - .ch1_addr(pal_addr), - .ch1_burst(128), - .ch1_data(pal_data), - .ch1_req(pal_req), - .ch1_ready(pal_wr) -); - -wire clk_pal = clk_audio; - - -wire [27:0] vbuf_address; -wire [7:0] vbuf_burstcount; -wire vbuf_waitrequest; -wire [127:0] vbuf_readdata; -wire vbuf_readdatavalid; -wire vbuf_read; -wire [127:0] vbuf_writedata; -wire [15:0] vbuf_byteenable; -wire vbuf_write; - -wire [23:0] hdmi_data; -wire hdmi_vs, hdmi_hs, hdmi_de, hdmi_vbl, hdmi_brd; -wire freeze; - -`ifndef MISTER_DEBUG_NOHDMI - wire clk_hdmi = hdmi_clk_out; - - ascal - #( - .RAMBASE(32'h20000000), - `ifdef MISTER_SMALL_VBUF - .RAMSIZE(32'h00200000), - `else - .RAMSIZE(32'h00800000), - `endif - `ifndef MISTER_FB - .PALETTE2("false"), - `else - `ifndef MISTER_FB_PALETTE - .PALETTE2("false"), - `endif - `endif - `ifdef MISTER_DISABLE_ADAPTIVE - .ADAPTIVE("false"), - `endif - `ifdef MISTER_DOWNSCALE_NN - .DOWNSCALE_NN("true"), - `endif - .FRAC(8), - .N_DW(128), - .N_AW(28) - ) - ascal - ( - .reset_na (~reset_req), - .run (1), - .freeze (freeze), - - .i_clk (clk_ihdmi), - .i_ce (ce_hpix), - .i_r (hr_out), - .i_g (hg_out), - .i_b (hb_out), - .i_hs (hhs_fix), - .i_vs (hvs_fix), - .i_fl (f1), - .i_de (hde_emu), - .iauto (1), - .himin (0), - .himax (0), - .vimin (0), - .vimax (0), - - .o_clk (clk_hdmi), - .o_ce (scaler_out), - .o_r (hdmi_data[23:16]), - .o_g (hdmi_data[15:8]), - .o_b (hdmi_data[7:0]), - .o_hs (hdmi_hs), - .o_vs (hdmi_vs), - .o_de (hdmi_de), - .o_vbl (hdmi_vbl), - .o_brd (hdmi_brd), - .o_lltune (lltune), - .htotal (WIDTH + HFP + HBP + HS[11:0]), - .hsstart (WIDTH + HFP), - .hsend (WIDTH + HFP + HS[11:0]), - .hdisp (WIDTH), - .hmin (hmin), - .hmax (hmax), - .vtotal (HEIGHT + VFP + VBP + VS[11:0]), - .vsstart (HEIGHT + VFP), - .vsend (HEIGHT + VFP + VS[11:0]), - .vdisp (HEIGHT), - .vmin (vmin), - .vmax (vmax), - .vrr (vrr_mode), - .vrrmax (HEIGHT + VBP + VS[11:0] + 12'd1), - - .mode ({~lowlat,LFB_EN ? LFB_FLT : |scaler_flt,2'b00}), - .poly_clk (clk_sys), - .poly_a (coef_addr), - .poly_dw (coef_data), - .poly_wr (coef_wr), - - .pal1_clk (clk_pal), - .pal1_dw (pal_d), - .pal1_a (pal_a), - .pal1_wr (pal_wr), - - `ifdef MISTER_FB - `ifdef MISTER_FB_PALETTE - .pal2_clk (fb_pal_clk), - .pal2_dw (fb_pal_d), - .pal2_dr (fb_pal_q), - .pal2_a (fb_pal_a), - .pal2_wr (fb_pal_wr), - .pal_n (fb_en), - `endif - `endif - - .o_fb_ena (FB_EN), - .o_fb_hsize (FB_WIDTH), - .o_fb_vsize (FB_HEIGHT), - .o_fb_format (FB_FMT), - .o_fb_base (FB_BASE), - .o_fb_stride (FB_STRIDE), - - .avl_clk (clk_100m), - .avl_waitrequest (vbuf_waitrequest), - .avl_readdata (vbuf_readdata), - .avl_readdatavalid(vbuf_readdatavalid), - .avl_burstcount (vbuf_burstcount), - .avl_writedata (vbuf_writedata), - .avl_address (vbuf_address), - .avl_write (vbuf_write), - .avl_read (vbuf_read), - .avl_byteenable (vbuf_byteenable) - ); -`endif - -reg LFB_EN = 0; -reg LFB_FLT = 0; -reg [5:0] LFB_FMT = 0; -reg [11:0] LFB_WIDTH = 0; -reg [11:0] LFB_HEIGHT = 0; -reg [11:0] LFB_HMIN = 0; -reg [11:0] LFB_HMAX = 0; -reg [11:0] LFB_VMIN = 0; -reg [11:0] LFB_VMAX = 0; -reg [31:0] LFB_BASE = 0; -reg [13:0] LFB_STRIDE = 0; - -reg FB_EN = 0; -reg [5:0] FB_FMT = 0; -reg [11:0] FB_WIDTH = 0; -reg [11:0] FB_HEIGHT = 0; -reg [31:0] FB_BASE = 0; -reg [13:0] FB_STRIDE = 0; - -always @(posedge clk_sys) begin - FB_EN <= LFB_EN | fb_en; - if(LFB_EN) begin - FB_FMT <= LFB_FMT; - FB_WIDTH <= LFB_WIDTH; - FB_HEIGHT <= LFB_HEIGHT; - FB_BASE <= LFB_BASE; - FB_STRIDE <= LFB_STRIDE; - end - else begin - FB_FMT <= fb_fmt; - FB_WIDTH <= fb_width; - FB_HEIGHT <= fb_height; - FB_BASE <= fb_base; - FB_STRIDE <= fb_stride; - end -end - -`ifdef MISTER_FB - reg fb_vbl; - always @(posedge clk_vid) fb_vbl <= hdmi_vbl; -`endif - -reg ar_md_start; -wire ar_md_busy; -reg [11:0] ar_md_mul1, ar_md_mul2, ar_md_div; -wire [11:0] ar_md_res; - -sys_umuldiv #(12,12,12) ar_muldiv -( - .clk(clk_vid), - .start(ar_md_start), - .busy(ar_md_busy), - - .mul1(ar_md_mul1), - .mul2(ar_md_mul2), - .div(ar_md_div), - .result(ar_md_res) -); - -reg [11:0] hmin; -reg [11:0] hmax; -reg [11:0] vmin; -reg [11:0] vmax; -reg [11:0] hdmi_height; -reg [11:0] hdmi_width; - -reg [11:0] arx; -reg [11:0] ary; -reg arxy; - -always @(posedge clk_vid) begin - reg [11:0] hmini,hmaxi,vmini,vmaxi; - reg [11:0] wcalc,videow; - reg [11:0] hcalc,videoh; - reg [2:0] state; - - hdmi_height <= (VSET && (VSET < HEIGHT)) ? VSET : HEIGHT; - hdmi_width <= (HSET && (HSET < WIDTH)) ? HSET << HDMI_PR : WIDTH << HDMI_PR; - - if(!ARY) begin - if(ARX == 1) begin - arx <= arc1x[11:0]; - ary <= arc1y[11:0]; - arxy <= arc1x[12] | arc1y[12]; - end - else if(ARX == 2) begin - arx <= arc2x[11:0]; - ary <= arc2y[11:0]; - arxy <= arc2x[12] | arc2y[12]; - end - else begin - arx <= 0; - ary <= 0; - arxy <= 0; - end - end - else begin - arx <= ARX[11:0]; - ary <= ARY[11:0]; - arxy <= ARX[12] | ARY[12]; - end - - ar_md_start <= 0; - state <= state + 1'd1; - case(state) - 0: if(LFB_EN) begin - hmini <= LFB_HMIN; - vmini <= LFB_VMIN; - hmaxi <= LFB_HMAX; - vmaxi <= LFB_VMAX; - state <= 0; - end - else if(FREESCALE || !arx || !ary) begin - wcalc <= hdmi_width; - hcalc <= hdmi_height; - state <= 6; - end - else if(arxy) begin - wcalc <= arx; - hcalc <= ary; - state <= 6; - end - - 1: begin - ar_md_mul1 <= hdmi_height; - ar_md_mul2 <= arx; - ar_md_div <= ary; - ar_md_start<= 1; - end - 2: begin - wcalc <= ar_md_res; - if(ar_md_start | ar_md_busy) state <= 2; - end - - 3: begin - ar_md_mul1 <= hdmi_width; - ar_md_mul2 <= ary; - ar_md_div <= arx; - ar_md_start<= 1; - end - 4: begin - hcalc <= ar_md_res; - if(ar_md_start | ar_md_busy) state <= 4; - end - - 6: begin - videow <= (wcalc > hdmi_width) ? (hdmi_width >> HDMI_PR) : (wcalc[11:0] >> HDMI_PR); - videoh <= (hcalc > hdmi_height) ? hdmi_height : hcalc[11:0]; - end - - 7: begin - hmini <= ((WIDTH - videow)>>1); - hmaxi <= ((WIDTH - videow)>>1) + videow - 1'd1; - vmini <= ((HEIGHT - videoh)>>1); - vmaxi <= ((HEIGHT - videoh)>>1) + videoh - 1'd1; - end - endcase - - hmin <= hmini; - hmax <= hmaxi; - vmin <= vmini; - vmax <= vmaxi; -end - -`ifndef MISTER_DEBUG_NOHDMI - wire [15:0] lltune; - pll_hdmi_adj pll_hdmi_adj - ( - .clk(FPGA_CLK1_50), - .reset_na(~reset_req), - - .llena(lowlat), - .lltune({16{cfg_done}} & lltune), - .locked(led_locked), - .i_waitrequest(adj_waitrequest), - .i_write(adj_write), - .i_address(adj_address), - .i_writedata(adj_data), - .o_waitrequest(cfg_waitrequest), - .o_write(cfg_write), - .o_address(cfg_address), - .o_writedata(cfg_data) - ); -`else - assign led_locked = 0; -`endif - -wire [63:0] pal_data; -wire [47:0] pal_d = {pal_data[55:32], pal_data[23:0]}; -wire [6:0] pal_a = ram2_bcnt[6:0]; -wire pal_wr; - -reg [28:0] pal_addr; -reg pal_req = 0; -always @(posedge clk_pal) begin - reg old_vs1, old_vs2; - - pal_addr <= LFB_BASE[31:3] - 29'd512; - - old_vs1 <= hdmi_vs; - old_vs2 <= old_vs1; - - if(~old_vs2 & old_vs1 & ~FB_FMT[2] & FB_FMT[1] & FB_FMT[0] & FB_EN) pal_req <= ~pal_req; -end - - -///////////////////////// HDMI output ///////////////////////////////// -`ifndef MISTER_DEBUG_NOHDMI - wire hdmi_clk_out; - pll_hdmi pll_hdmi - ( - .refclk(FPGA_CLK1_50), - .rst(reset_req), - .reconfig_to_pll(reconfig_to_pll), - .reconfig_from_pll(reconfig_from_pll), - .outclk_0(hdmi_clk_out) - ); -`endif - -//1920x1080@60 PCLK=148.5MHz CEA -reg [11:0] WIDTH = 1920; -reg [11:0] HFP = 88; -reg [12:0] HS = 48; -reg [11:0] HBP = 148; -reg [11:0] HEIGHT = 1080; -reg [11:0] VFP = 4; -reg [12:0] VS = 5; -reg [11:0] VBP = 36; -reg HDMI_PR = 0; - -wire [63:0] reconfig_to_pll; -wire [63:0] reconfig_from_pll; -wire cfg_waitrequest,adj_waitrequest; -wire cfg_write; -wire [5:0] cfg_address; -wire [31:0] cfg_data; -reg adj_write; -reg [5:0] adj_address; -reg [31:0] adj_data; - -`ifndef MISTER_DEBUG_NOHDMI - pll_cfg_hdmi pll_cfg_hdmi - ( - .mgmt_clk(FPGA_CLK1_50), - .mgmt_reset(reset_req), - .mgmt_waitrequest(cfg_waitrequest), - .mgmt_write(cfg_write), - .mgmt_address(cfg_address), - .mgmt_writedata(cfg_data), - .reconfig_to_pll(reconfig_to_pll), - .reconfig_from_pll(reconfig_from_pll) - ); - - reg cfg_got = 0; - always @(posedge clk_sys) begin - reg vsd, vsd2; - if(~cfg_ready || ~cfg_set) cfg_got <= cfg_set; - else begin - vsd <= HDMI_TX_VS; - vsd2 <= vsd; - if(~vsd2 & vsd) cfg_got <= cfg_set; - end - end - - reg cfg_ready = 0; - always @(posedge FPGA_CLK1_50) begin - reg gotd = 0, gotd2 = 0; - reg custd = 0, custd2 = 0; - reg old_wait = 0; - - gotd <= cfg_got; - gotd2 <= gotd; - - adj_write <= 0; - - custd <= cfg_custom_t; - custd2 <= custd; - if(custd2 != custd & ~gotd) begin - adj_address <= cfg_custom_p1; - adj_data <= cfg_custom_p2; - adj_write <= 1; - end - - if(~gotd2 & gotd) begin - adj_address <= 2; - adj_data <= 0; - adj_write <= 1; - end - - old_wait <= adj_waitrequest; - if(old_wait & ~adj_waitrequest & gotd) cfg_ready <= 1; - end -`else - wire cfg_ready = 1; -`endif - -assign HDMI_I2C_SCL = hdmi_scl_en ? 1'b0 : 1'bZ; -assign HDMI_I2C_SDA = hdmi_sda_en ? 1'b0 : 1'bZ; - -wire hdmi_scl_en, hdmi_sda_en; -cyclonev_hps_interface_peripheral_i2c hdmi_i2c -( - .out_clk(hdmi_scl_en), - .scl(HDMI_I2C_SCL), - .out_data(hdmi_sda_en), - .sda(HDMI_I2C_SDA) -); - -`ifndef MISTER_DEBUG_NOHDMI - `ifdef MISTER_FB - reg dis_output; - always @(posedge clk_hdmi) begin - reg dis; - dis <= fb_force_blank & ~LFB_EN; - dis_output <= dis; - end - `else - wire dis_output = 0; - `endif - - wire [23:0] hdmi_data_mask; - wire hdmi_de_mask, hdmi_vs_mask, hdmi_hs_mask; - - reg [15:0] shadowmask_data; - reg shadowmask_wr = 0; - - shadowmask HDMI_shadowmask - ( - .clk(clk_hdmi), - .clk_sys(clk_sys), - - .cmd_wr(shadowmask_wr), - .cmd_in(shadowmask_data), - - .din(dis_output ? 24'd0 : hdmi_data), - .hs_in(hdmi_hs), - .vs_in(hdmi_vs), - .de_in(hdmi_de), - .brd_in(hdmi_brd), - .enable(~LFB_EN), - - .dout(hdmi_data_mask), - .hs_out(hdmi_hs_mask), - .vs_out(hdmi_vs_mask), - .de_out(hdmi_de_mask) - ); - - wire [23:0] hdmi_data_osd; - wire hdmi_de_osd, hdmi_vs_osd, hdmi_hs_osd; - - osd hdmi_osd - ( - .clk_sys(clk_sys), - - .io_osd(io_osd_hdmi), - .io_strobe(io_strobe), - .io_din(io_din), - - .clk_video(clk_hdmi), - .din(hdmi_data_mask), - .hs_in(hdmi_hs_mask), - .vs_in(hdmi_vs_mask), - .de_in(hdmi_de_mask), - - .dout(hdmi_data_osd), - .hs_out(hdmi_hs_osd), - .vs_out(hdmi_vs_osd), - .de_out(hdmi_de_osd) - ); - - wire hdmi_cs_osd; - csync csync_hdmi(clk_hdmi, hdmi_hs_osd, hdmi_vs_osd, hdmi_cs_osd); -`endif - -reg [23:0] dv_data; -reg dv_hs, dv_vs, dv_de; -wire [23:0] dv_data_osd; -wire dv_hs_osd, dv_vs_osd, dv_cs_osd; - -always @(posedge clk_vid) begin - reg [23:0] dv_d1, dv_d2; - reg dv_de1, dv_de2, dv_hs1, dv_hs2, dv_vs1, dv_vs2; - reg [12:0] vsz, vcnt, vcnt_l, vcnt_ll; - reg old_hs, old_vs; - reg vde; - reg [3:0] hss; - - if(ce_pix) begin - hss <= (hss << 1) | dv_hs_osd; - - old_hs <= dv_hs_osd; - if(~old_hs && dv_hs_osd) begin - old_vs <= dv_vs_osd; - if(~&vcnt) vcnt <= vcnt + 1'd1; - if(~old_vs & dv_vs_osd) begin - if (vcnt != vcnt_ll || vcnt < vcnt_l) vsz <= vcnt; - vcnt_l <= vcnt; - vcnt_ll <= vcnt_l; - end - if(old_vs & ~dv_vs_osd) vcnt <= 0; - - if(vcnt == 1) vde <= 1; - if(vcnt == vsz - 3) vde <= 0; - end - - dv_de1 <= !{hss,dv_hs_osd} && vde; - end - - dv_d1 <= dv_data_osd; - dv_hs1 <= csync_en ? dv_cs_osd : dv_hs_osd; - dv_vs1 <= dv_vs_osd; - - dv_d2 <= dv_d1; - dv_de2 <= dv_de1; - dv_hs2 <= dv_hs1; - dv_vs2 <= dv_vs1; - - dv_data<= dv_d2; - dv_de <= dv_de2; - dv_hs <= dv_hs2; - dv_vs <= dv_vs2; -end - -`ifndef MISTER_DISABLE_YC - assign {dv_data_osd, dv_hs_osd, dv_vs_osd, dv_cs_osd } = ~yc_en ? {vga_data_osd, vga_hs_osd, vga_vs_osd, vga_cs_osd } : {yc_o, yc_hs, yc_vs, yc_cs }; -`else - assign {dv_data_osd, dv_hs_osd, dv_vs_osd, dv_cs_osd } = {vga_data_osd, vga_hs_osd, vga_vs_osd, vga_cs_osd }; -`endif - -wire hdmi_tx_clk; -`ifndef MISTER_DEBUG_NOHDMI - cyclonev_clkselect hdmi_clk_sw - ( - .clkselect({1'b1, ~vga_fb & direct_video}), - .inclk({clk_vid, hdmi_clk_out, 2'b00}), - .outclk(hdmi_tx_clk) - ); -`else - assign hdmi_tx_clk = clk_vid; -`endif - -altddio_out -#( - .extend_oe_disable("OFF"), - .intended_device_family("Cyclone V"), - .invert_output("OFF"), - .lpm_hint("UNUSED"), - .lpm_type("altddio_out"), - .oe_reg("UNREGISTERED"), - .power_up_high("OFF"), - .width(1) -) -hdmiclk_ddr -( - .datain_h(1'b0), - .datain_l(1'b1), - .outclock(hdmi_tx_clk), - .dataout(HDMI_TX_CLK), - .aclr(1'b0), - .aset(1'b0), - .oe(1'b1), - .outclocken(1'b1), - .sclr(1'b0), - .sset(1'b0) -); - -reg hdmi_out_hs; -reg hdmi_out_vs; -reg hdmi_out_de; -reg [23:0] hdmi_out_d; - -always @(posedge hdmi_tx_clk) begin - reg [23:0] hdmi_dv_data; - reg hdmi_dv_hs, hdmi_dv_vs, hdmi_dv_de; - - reg hs,vs,de; - reg [23:0] d; - - hdmi_dv_data <= dv_data; - hdmi_dv_hs <= dv_hs; - hdmi_dv_vs <= dv_vs; - hdmi_dv_de <= dv_de; - -`ifndef MISTER_DEBUG_NOHDMI - hs <= (~vga_fb & direct_video) ? hdmi_dv_hs : (direct_video & csync_en) ? hdmi_cs_osd : hdmi_hs_osd; - vs <= (~vga_fb & direct_video) ? hdmi_dv_vs : hdmi_vs_osd; - de <= (~vga_fb & direct_video) ? hdmi_dv_de : hdmi_de_osd; - d <= (~vga_fb & direct_video) ? hdmi_dv_data : hdmi_data_osd; -`else - hs <= hdmi_dv_hs; - vs <= hdmi_dv_vs; - de <= hdmi_dv_de; - d <= hdmi_dv_data; -`endif - - hdmi_out_hs <= hs; - hdmi_out_vs <= vs; - hdmi_out_de <= de; - hdmi_out_d <= d; -end - -assign HDMI_TX_HS = hdmi_out_hs; -assign HDMI_TX_VS = hdmi_out_vs; -assign HDMI_TX_DE = hdmi_out_de; -assign HDMI_TX_D = hdmi_out_d; - -///////////////////////// VGA output ////////////////////////////////// - -`ifndef MISTER_DUAL_SDRAM - wire vga_tx_clk; - `ifndef MISTER_DEBUG_NOHDMI - cyclonev_clkselect vga_clk_sw - ( - .clkselect({1'b1, ~vga_fb & ~vga_scaler}), - .inclk({clk_vid, hdmi_clk_out, 2'b00}), - .outclk(vga_tx_clk) - ); - `else - assign vga_tx_clk = clk_vid; - `endif - - wire VGA_TX_CLK; - altddio_out - #( - .extend_oe_disable("OFF"), - .intended_device_family("Cyclone V"), - .invert_output("OFF"), - .lpm_hint("UNUSED"), - .lpm_type("altddio_out"), - .oe_reg("UNREGISTERED"), - .power_up_high("OFF"), - .width(1) - ) - vgaclk_ddr - ( - .datain_h(1'b0), - .datain_l(1'b1), - .outclock(vga_tx_clk), - .dataout(VGA_TX_CLK), - .aclr(~mcp_en & ~av_dis), - .aset(1'b0), - .oe(~av_dis & (mcp_en | ~led_u)), - .outclocken(1'b1), - .sclr(1'b0), - .sset(1'b0) - ); -`endif - -wire [23:0] vga_data_sl; -wire vga_de_sl, vga_ce_sl, vga_vs_sl, vga_hs_sl; -scanlines #(0) VGA_scanlines -( - .clk(clk_vid), - - .scanlines(scanlines), - .din(de_emu ? {r_out, g_out, b_out} : 24'd0), - .hs_in(hs_fix), - .vs_in(vs_fix), - .de_in(de_emu), - .ce_in(ce_pix), - - .dout(vga_data_sl), - .hs_out(vga_hs_sl), - .vs_out(vga_vs_sl), - .de_out(vga_de_sl), - .ce_out(vga_ce_sl) -); - -wire [23:0] vga_data_osd; -wire vga_vs_osd, vga_hs_osd, vga_de_osd; -osd vga_osd -( - .clk_sys(clk_sys), - - .io_osd(io_osd_vga), - .io_strobe(io_strobe), - .io_din(io_din), - .osd_status(osd_status), - - .clk_video(clk_vid), - .din(vga_data_sl), - .hs_in(vga_hs_sl), - .vs_in(vga_vs_sl), - .de_in(vga_de_sl), - - .dout(vga_data_osd), - .hs_out(vga_hs_osd), - .vs_out(vga_vs_osd), - .de_out(vga_de_osd) -); - -wire vga_cs_osd; -csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd); - -`ifndef MISTER_DISABLE_YC - reg pal_en; - reg yc_en; - reg cvbs; - reg [16:0] ColorBurst_Range; - reg [39:0] PhaseInc; - wire [23:0] yc_o; - wire yc_hs, yc_vs, yc_cs, yc_de; - - yc_out yc_out - ( - .clk(clk_vid), - .PAL_EN(pal_en), - .CVBS(cvbs), - .PHASE_INC(PhaseInc), - .COLORBURST_RANGE(ColorBurst_Range), - .hsync(vga_hs_osd), - .vsync(vga_vs_osd), - .csync(vga_cs_osd), - .de(vga_de_osd), - .dout(yc_o), - .din(vga_data_osd), - .hsync_o(yc_hs), - .vsync_o(yc_vs), - .csync_o(yc_cs), - .de_o(yc_de) - ); -`endif - -`ifndef MISTER_DUAL_SDRAM - wire VGA_DISABLE; - wire [23:0] vgas_o; - wire vgas_hs, vgas_vs, vgas_cs, vgas_de; - `ifndef MISTER_DEBUG_NOHDMI - vga_out vga_scaler_out - ( - .clk(clk_hdmi), - .ypbpr_en(ypbpr_en), - .hsync(hdmi_hs_osd), - .vsync(hdmi_vs_osd), - .csync(hdmi_cs_osd), - .de(hdmi_de_osd), - .dout(vgas_o), - .din({24{hdmi_de_osd}} & hdmi_data_osd), - .hsync_o(vgas_hs), - .vsync_o(vgas_vs), - .csync_o(vgas_cs), - .de_o(vgas_de) - ); - `else - assign {vgas_o, vgas_hs, vgas_vs, vgas_cs, vgas_de} = 0; - `endif - - wire [23:0] vga_o, vga_o_t; - wire vga_hs, vga_vs, vga_cs, vga_de, vga_hs_t, vga_vs_t, vga_cs_t, vga_de_t; - vga_out vga_out - ( - .clk(clk_vid), - .ypbpr_en(ypbpr_en), - .hsync(vga_hs_osd), - .vsync(vga_vs_osd), - .csync(vga_cs_osd), - .de(vga_de_osd), - .dout(vga_o_t), - .din(vga_data_osd), - .hsync_o(vga_hs_t), - .vsync_o(vga_vs_t), - .csync_o(vga_cs_t), - .de_o(vga_de_t) - ); - - `ifndef MISTER_DISABLE_YC - assign {vga_o, vga_hs, vga_vs, vga_cs, vga_de } = ~yc_en ? {vga_o_t, vga_hs_t, vga_vs_t, vga_cs_t, vga_de_t } : {yc_o, yc_hs, yc_vs, yc_cs, yc_de }; - `else - assign {vga_o, vga_hs, vga_vs, vga_cs, vga_de } = {vga_o_t, vga_hs_t, vga_vs_t, vga_cs_t, vga_de_t } ; - `endif - - wire vgas_en = vga_fb | vga_scaler; - - wire cs1 = vgas_en ? vgas_cs : vga_cs; - wire de1 = vgas_en ? vgas_de : vga_de; - - assign VGA_VS = av_dis ? 1'bZ : ((vgas_en ? (~vgas_vs ^ VS[12]) : VGA_DISABLE ? 1'd1 : ~vga_vs) | csync_en); - assign VGA_HS = av_dis ? 1'bZ : (vgas_en ? ((csync_en ? ~vgas_cs : ~vgas_hs) ^ HS[12]) : VGA_DISABLE ? 1'd1 : (csync_en ? ~vga_cs : ~vga_hs)); - assign VGA_R = av_dis ? 6'bZZZZZZ : vgas_en ? vgas_o[23:18] : VGA_DISABLE ? 6'd0 : vga_o[23:18]; - assign VGA_G = av_dis ? 6'bZZZZZZ : vgas_en ? vgas_o[15:10] : VGA_DISABLE ? 6'd0 : vga_o[15:10]; - assign VGA_B = av_dis ? 6'bZZZZZZ : vgas_en ? vgas_o[7:2] : VGA_DISABLE ? 6'd0 : vga_o[7:2] ; - - wire [1:0] vga_r = vgas_en ? vgas_o[17:16] : VGA_DISABLE ? 2'd0 : vga_o[17:16]; - wire [1:0] vga_g = vgas_en ? vgas_o[9:8] : VGA_DISABLE ? 2'd0 : vga_o[9:8]; - wire [1:0] vga_b = vgas_en ? vgas_o[1:0] : VGA_DISABLE ? 2'd0 : vga_o[1:0]; -`endif - -reg video_sync = 0; -always @(posedge clk_vid) begin - reg [11:0] line_cnt = 0; - reg [11:0] sync_line = 0; - reg [1:0] hs_cnt = 0; - reg old_hs; - - old_hs <= hs_fix; - if(~old_hs & hs_fix) begin - - video_sync <= (sync_line == line_cnt); - - line_cnt <= line_cnt + 1'd1; - if(~hs_cnt[1]) begin - hs_cnt <= hs_cnt + 1'd1; - if(hs_cnt[0]) begin - sync_line <= (line_cnt - vs_line); - line_cnt <= 0; - end - end - end - - if(de_emu) hs_cnt <= 0; -end - -///////////////////////// Audio output //////////////////////////////// - -assign SDCD_SPDIF = (mcp_en & ~spdif) ? 1'b0 : 1'bZ; - -`ifndef MISTER_DUAL_SDRAM - wire analog_l, analog_r; - - assign AUDIO_SPDIF = av_dis ? 1'bZ : (SW[0] | mcp_en) ? HDMI_LRCLK : spdif; - assign AUDIO_R = av_dis ? 1'bZ : (SW[0] | mcp_en) ? HDMI_I2S : analog_r; - assign AUDIO_L = av_dis ? 1'bZ : (SW[0] | mcp_en) ? HDMI_SCLK : analog_l; -`endif - -assign HDMI_MCLK = clk_audio; -wire clk_audio; - -pll_audio pll_audio -( - .refclk(FPGA_CLK3_50), - .rst(0), - .outclk_0(clk_audio) -); - -wire spdif; -audio_out audio_out -( - .reset(reset | areset), - .clk(clk_audio), - - .att(vol_att), - .mix(audio_mix), - .sample_rate(audio_96k), - - .flt_rate(aflt_rate), - .cx(acx), - .cx0(acx0), - .cx1(acx1), - .cx2(acx2), - .cy0(acy0), - .cy1(acy1), - .cy2(acy2), - - .is_signed(audio_s), - .core_l(audio_l), - .core_r(audio_r), - -`ifndef MISTER_DISABLE_ALSA - .alsa_l(alsa_l), - .alsa_r(alsa_r), -`endif - - .i2s_bclk(HDMI_SCLK), - .i2s_lrclk(HDMI_LRCLK), - .i2s_data(HDMI_I2S), -`ifndef MISTER_DUAL_SDRAM - .dac_l(analog_l), - .dac_r(analog_r), -`endif - .spdif(spdif) -); - - -`ifndef MISTER_DISABLE_ALSA - wire aspi_sck,aspi_mosi,aspi_ss,aspi_miso; - cyclonev_hps_interface_peripheral_spi_master spi - ( - .sclk_out(aspi_sck), - .txd(aspi_mosi), // mosi - .rxd(aspi_miso), // miso - - .ss_0_n(aspi_ss), - .ss_in_n(1) - ); - - wire [28:0] alsa_address; - wire [63:0] alsa_readdata; - wire alsa_ready; - wire alsa_req; - wire alsa_late; - - wire [15:0] alsa_l, alsa_r; - - alsa alsa - ( - .reset(reset), - .clk(clk_audio), - - .ram_address(alsa_address), - .ram_data(alsa_readdata), - .ram_req(alsa_req), - .ram_ready(alsa_ready), - - .spi_ss(aspi_ss), - .spi_sck(aspi_sck), - .spi_mosi(aspi_mosi), - .spi_miso(aspi_miso), - - .pcm_l(alsa_l), - .pcm_r(alsa_r) - ); -`endif - -//////////////// User I/O (USB 3.0 connector) ///////////////////////// - -assign USER_IO[0] = !user_out[0] ? 1'b0 : 1'bZ; -assign USER_IO[1] = !user_out[1] ? 1'b0 : 1'bZ; -assign USER_IO[2] = !(SW[1] ? HDMI_I2S : user_out[2]) ? 1'b0 : 1'bZ; -assign USER_IO[3] = !user_out[3] ? 1'b0 : 1'bZ; -assign USER_IO[4] = !(SW[1] ? HDMI_SCLK : user_out[4]) ? 1'b0 : 1'bZ; -assign USER_IO[5] = !(SW[1] ? HDMI_LRCLK : user_out[5]) ? 1'b0 : 1'bZ; -assign USER_IO[6] = !user_out[6] ? 1'b0 : 1'bZ; - -assign user_in[0] = USER_IO[0]; -assign user_in[1] = USER_IO[1]; -assign user_in[2] = SW[1] | USER_IO[2]; -assign user_in[3] = USER_IO[3]; -assign user_in[4] = SW[1] | USER_IO[4]; -assign user_in[5] = SW[1] | USER_IO[5]; -assign user_in[6] = USER_IO[6]; - - -/////////////////// User module connection //////////////////////////// - -wire clk_sys; -wire [15:0] audio_l, audio_r; -wire audio_s; -wire [1:0] audio_mix; -wire [1:0] scanlines; -wire [7:0] r_out, g_out, b_out, hr_out, hg_out, hb_out; -wire vs_fix, hs_fix, de_emu, vs_emu, hs_emu, f1; -wire hvs_fix, hhs_fix, hde_emu; -wire clk_vid, ce_pix, clk_ihdmi, ce_hpix; -wire vga_force_scaler; - -wire ram_clk; -wire [28:0] ram_address; -wire [7:0] ram_burstcount; -wire ram_waitrequest; -wire [63:0] ram_readdata; -wire ram_readdatavalid; -wire ram_read; -wire [63:0] ram_writedata; -wire [7:0] ram_byteenable; -wire ram_write; - -wire led_user; -wire [1:0] led_power; -wire [1:0] led_disk; -wire [1:0] btn; - -sync_fix sync_v(clk_vid, vs_emu, vs_fix); -sync_fix sync_h(clk_vid, hs_emu, hs_fix); - -wire [6:0] user_out, user_in; - -assign clk_ihdmi= clk_vid; -assign ce_hpix = vga_ce_sl; -assign hr_out = vga_data_sl[23:16]; -assign hg_out = vga_data_sl[15:8]; -assign hb_out = vga_data_sl[7:0]; -assign hhs_fix = vga_hs_sl; -assign hvs_fix = vga_vs_sl; -assign hde_emu = vga_de_sl; - -wire uart_dtr; -wire uart_dsr; -wire uart_cts; -wire uart_rts; -wire uart_rxd; -wire uart_txd; - -wire osd_status; - -wire fb_en; -wire [4:0] fb_fmt; -wire [11:0] fb_width; -wire [11:0] fb_height; -wire [31:0] fb_base; -wire [13:0] fb_stride; - - -`ifdef MISTER_FB - `ifdef MISTER_FB_PALETTE - wire fb_pal_clk; - wire [7:0] fb_pal_a; - wire [23:0] fb_pal_d; - wire [23:0] fb_pal_q; - wire fb_pal_wr; - `endif - wire fb_force_blank; -`else - assign fb_en = 0; - assign fb_fmt = 0; - assign fb_width = 0; - assign fb_height = 0; - assign fb_base = 0; - assign fb_stride = 0; -`endif - -reg [1:0] sl_r; -wire [1:0] sl = sl_r; -always @(posedge clk_sys) sl_r <= FB_EN ? 2'b00 : scanlines; - -emu emu -( - .CLK_50M(FPGA_CLK2_50), - .RESET(reset), - .HPS_BUS({fb_en, sl, f1, HDMI_TX_VS, - clk_100m, clk_ihdmi, - ce_hpix, hde_emu, hhs_fix, hvs_fix, - io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}), - - .VGA_R(r_out), - .VGA_G(g_out), - .VGA_B(b_out), - .VGA_HS(hs_emu), - .VGA_VS(vs_emu), - .VGA_DE(de_emu), - .VGA_F1(f1), - .VGA_SCALER(vga_force_scaler), - -`ifndef MISTER_DUAL_SDRAM - .VGA_DISABLE(VGA_DISABLE), -`endif - - .HDMI_WIDTH(direct_video ? 12'd0 : hdmi_width), - .HDMI_HEIGHT(direct_video ? 12'd0 : hdmi_height), - .HDMI_FREEZE(freeze), - - .CLK_VIDEO(clk_vid), - .CE_PIXEL(ce_pix), - .VGA_SL(scanlines), - .VIDEO_ARX(ARX), - .VIDEO_ARY(ARY), - -`ifdef MISTER_FB - .FB_EN(fb_en), - .FB_FORMAT(fb_fmt), - .FB_WIDTH(fb_width), - .FB_HEIGHT(fb_height), - .FB_BASE(fb_base), - .FB_STRIDE(fb_stride), - .FB_VBL(fb_vbl), - .FB_LL(lowlat), - .FB_FORCE_BLANK(fb_force_blank), - -`ifdef MISTER_FB_PALETTE - .FB_PAL_CLK (fb_pal_clk), - .FB_PAL_ADDR(fb_pal_a), - .FB_PAL_DOUT(fb_pal_d), - .FB_PAL_DIN (fb_pal_q), - .FB_PAL_WR (fb_pal_wr), -`endif - -`endif - - .LED_USER(led_user), - .LED_POWER(led_power), - .LED_DISK(led_disk), - - .CLK_AUDIO(clk_audio), - .AUDIO_L(audio_l), - .AUDIO_R(audio_r), - .AUDIO_S(audio_s), - .AUDIO_MIX(audio_mix), - - .ADC_BUS({ADC_SCK,ADC_SDO,ADC_SDI,ADC_CONVST}), - - .DDRAM_CLK(ram_clk), - .DDRAM_ADDR(ram_address), - .DDRAM_BURSTCNT(ram_burstcount), - .DDRAM_BUSY(ram_waitrequest), - .DDRAM_DOUT(ram_readdata), - .DDRAM_DOUT_READY(ram_readdatavalid), - .DDRAM_RD(ram_read), - .DDRAM_DIN(ram_writedata), - .DDRAM_BE(ram_byteenable), - .DDRAM_WE(ram_write), - - .SDRAM_DQ(SDRAM_DQ), - .SDRAM_A(SDRAM_A), - .SDRAM_DQML(SDRAM_DQML), - .SDRAM_DQMH(SDRAM_DQMH), - .SDRAM_BA(SDRAM_BA), - .SDRAM_nCS(SDRAM_nCS), - .SDRAM_nWE(SDRAM_nWE), - .SDRAM_nRAS(SDRAM_nRAS), - .SDRAM_nCAS(SDRAM_nCAS), - .SDRAM_CLK(SDRAM_CLK), - .SDRAM_CKE(SDRAM_CKE), - -`ifdef MISTER_DUAL_SDRAM - .SDRAM2_DQ(SDRAM2_DQ), - .SDRAM2_A(SDRAM2_A), - .SDRAM2_BA(SDRAM2_BA), - .SDRAM2_nCS(SDRAM2_nCS), - .SDRAM2_nWE(SDRAM2_nWE), - .SDRAM2_nRAS(SDRAM2_nRAS), - .SDRAM2_nCAS(SDRAM2_nCAS), - .SDRAM2_CLK(SDRAM2_CLK), - .SDRAM2_EN(io_dig), -`endif - - .BUTTONS(btn), - .OSD_STATUS(osd_status), - - .SD_SCK(SD_CLK), - .SD_MOSI(SD_MOSI), - .SD_MISO(SD_MISO), - .SD_CS(SD_CS), - .SD_CD(SD_CD), - - .UART_CTS(uart_rts), - .UART_RTS(uart_cts), - .UART_RXD(uart_txd), - .UART_TXD(uart_rxd), - .UART_DTR(uart_dsr), - .UART_DSR(uart_dtr), - - .USER_OUT(user_out), - .USER_IN(user_in) -); - -endmodule - -///////////////////////////////////////////////////////////////////// - -module sync_fix -( - input clk, - - input sync_in, - output sync_out -); - -assign sync_out = sync_in ^ pol; - -reg pol; -always @(posedge clk) begin - reg [31:0] cnt; - reg s1,s2; - - s1 <= sync_in; - s2 <= s1; - cnt <= s2 ? (cnt - 1) : (cnt + 1); - - if(~s2 & s1) begin - cnt <= 0; - pol <= cnt[31]; - end -end - -endmodule - -///////////////////////////////////////////////////////////////////// - -// CSync generation -// Shifts HSync left by 1 HSync period during VSync - -module csync -( - input clk, - input hsync, - input vsync, - - output csync -); - -assign csync = (csync_vs ^ csync_hs); - -reg csync_hs, csync_vs; -always @(posedge clk) begin - reg prev_hs; - reg [15:0] h_cnt, line_len, hs_len; - - // Count line/Hsync length - h_cnt <= h_cnt + 1'd1; - - prev_hs <= hsync; - if (prev_hs ^ hsync) begin - h_cnt <= 0; - if (hsync) begin - line_len <= h_cnt - hs_len; - csync_hs <= 0; - end - else hs_len <= h_cnt; - end - - if (~vsync) csync_hs <= hsync; - else if(h_cnt == line_len) csync_hs <= 1; - - csync_vs <= vsync; -end - -endmodule diff --git a/sys/sysmem.sv b/sys/sysmem.sv deleted file mode 100644 index 8c17e86..0000000 --- a/sys/sysmem.sv +++ /dev/null @@ -1,570 +0,0 @@ -`timescale 1 ps / 1 ps -module sysmem_lite -( - output clock, - output reset_out, - - input reset_hps_cold_req, - input reset_hps_warm_req, - input reset_core_req, - - input ram1_clk, - input [28:0] ram1_address, - input [7:0] ram1_burstcount, - output ram1_waitrequest, - output [63:0] ram1_readdata, - output ram1_readdatavalid, - input ram1_read, - input [63:0] ram1_writedata, - input [7:0] ram1_byteenable, - input ram1_write, - - input ram2_clk, - input [28:0] ram2_address, - input [7:0] ram2_burstcount, - output ram2_waitrequest, - output [63:0] ram2_readdata, - output ram2_readdatavalid, - input ram2_read, - input [63:0] ram2_writedata, - input [7:0] ram2_byteenable, - input ram2_write, - - input vbuf_clk, - input [27:0] vbuf_address, - input [7:0] vbuf_burstcount, - output vbuf_waitrequest, - output [127:0] vbuf_readdata, - output vbuf_readdatavalid, - input vbuf_read, - input [127:0] vbuf_writedata, - input [15:0] vbuf_byteenable, - input vbuf_write -); - -assign reset_out = ~init_reset_n | ~hps_h2f_reset_n | reset_core_req; - -//////////////////////////////////////////////////////// -//// f2sdram_safe_terminator_ram1 //// -//////////////////////////////////////////////////////// -wire [28:0] f2h_ram1_address; -wire [7:0] f2h_ram1_burstcount; -wire f2h_ram1_waitrequest; -wire [63:0] f2h_ram1_readdata; -wire f2h_ram1_readdatavalid; -wire f2h_ram1_read; -wire [63:0] f2h_ram1_writedata; -wire [7:0] f2h_ram1_byteenable; -wire f2h_ram1_write; - -(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ram1_reset_0 = 1'b1; -(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ram1_reset_1 = 1'b1; -always @(posedge ram1_clk) begin - ram1_reset_0 <= reset_out; - ram1_reset_1 <= ram1_reset_0; -end - -f2sdram_safe_terminator #(64, 8) f2sdram_safe_terminator_ram1 -( - .clk (ram1_clk), - .rst_req_sync (ram1_reset_1), - - .waitrequest_slave (ram1_waitrequest), - .burstcount_slave (ram1_burstcount), - .address_slave (ram1_address), - .readdata_slave (ram1_readdata), - .readdatavalid_slave (ram1_readdatavalid), - .read_slave (ram1_read), - .writedata_slave (ram1_writedata), - .byteenable_slave (ram1_byteenable), - .write_slave (ram1_write), - - .waitrequest_master (f2h_ram1_waitrequest), - .burstcount_master (f2h_ram1_burstcount), - .address_master (f2h_ram1_address), - .readdata_master (f2h_ram1_readdata), - .readdatavalid_master (f2h_ram1_readdatavalid), - .read_master (f2h_ram1_read), - .writedata_master (f2h_ram1_writedata), - .byteenable_master (f2h_ram1_byteenable), - .write_master (f2h_ram1_write) -); - -//////////////////////////////////////////////////////// -//// f2sdram_safe_terminator_ram2 //// -//////////////////////////////////////////////////////// -wire [28:0] f2h_ram2_address; -wire [7:0] f2h_ram2_burstcount; -wire f2h_ram2_waitrequest; -wire [63:0] f2h_ram2_readdata; -wire f2h_ram2_readdatavalid; -wire f2h_ram2_read; -wire [63:0] f2h_ram2_writedata; -wire [7:0] f2h_ram2_byteenable; -wire f2h_ram2_write; - -(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ram2_reset_0 = 1'b1; -(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ram2_reset_1 = 1'b1; -always @(posedge ram2_clk) begin - ram2_reset_0 <= reset_out; - ram2_reset_1 <= ram2_reset_0; -end - -f2sdram_safe_terminator #(64, 8) f2sdram_safe_terminator_ram2 -( - .clk (ram2_clk), - .rst_req_sync (ram2_reset_1), - - .waitrequest_slave (ram2_waitrequest), - .burstcount_slave (ram2_burstcount), - .address_slave (ram2_address), - .readdata_slave (ram2_readdata), - .readdatavalid_slave (ram2_readdatavalid), - .read_slave (ram2_read), - .writedata_slave (ram2_writedata), - .byteenable_slave (ram2_byteenable), - .write_slave (ram2_write), - - .waitrequest_master (f2h_ram2_waitrequest), - .burstcount_master (f2h_ram2_burstcount), - .address_master (f2h_ram2_address), - .readdata_master (f2h_ram2_readdata), - .readdatavalid_master (f2h_ram2_readdatavalid), - .read_master (f2h_ram2_read), - .writedata_master (f2h_ram2_writedata), - .byteenable_master (f2h_ram2_byteenable), - .write_master (f2h_ram2_write) -); - -//////////////////////////////////////////////////////// -//// f2sdram_safe_terminator_vbuf //// -//////////////////////////////////////////////////////// -wire [27:0] f2h_vbuf_address; -wire [7:0] f2h_vbuf_burstcount; -wire f2h_vbuf_waitrequest; -wire [127:0] f2h_vbuf_readdata; -wire f2h_vbuf_readdatavalid; -wire f2h_vbuf_read; -wire [127:0] f2h_vbuf_writedata; -wire [15:0] f2h_vbuf_byteenable; -wire f2h_vbuf_write; - -(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg vbuf_reset_0 = 1'b1; -(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg vbuf_reset_1 = 1'b1; -always @(posedge vbuf_clk) begin - vbuf_reset_0 <= reset_out; - vbuf_reset_1 <= vbuf_reset_0; -end - -f2sdram_safe_terminator #(128, 8) f2sdram_safe_terminator_vbuf -( - .clk (vbuf_clk), - .rst_req_sync (vbuf_reset_1), - - .waitrequest_slave (vbuf_waitrequest), - .burstcount_slave (vbuf_burstcount), - .address_slave (vbuf_address), - .readdata_slave (vbuf_readdata), - .readdatavalid_slave (vbuf_readdatavalid), - .read_slave (vbuf_read), - .writedata_slave (vbuf_writedata), - .byteenable_slave (vbuf_byteenable), - .write_slave (vbuf_write), - - .waitrequest_master (f2h_vbuf_waitrequest), - .burstcount_master (f2h_vbuf_burstcount), - .address_master (f2h_vbuf_address), - .readdata_master (f2h_vbuf_readdata), - .readdatavalid_master (f2h_vbuf_readdatavalid), - .read_master (f2h_vbuf_read), - .writedata_master (f2h_vbuf_writedata), - .byteenable_master (f2h_vbuf_byteenable), - .write_master (f2h_vbuf_write) -); - -//////////////////////////////////////////////////////// -//// HPS <> FPGA interfaces //// -//////////////////////////////////////////////////////// -sysmem_HPS_fpga_interfaces fpga_interfaces ( - .f2h_cold_rst_req_n (~reset_hps_cold_req), - .f2h_warm_rst_req_n (~reset_hps_warm_req), - .h2f_user0_clk (clock), - .h2f_rst_n (hps_h2f_reset_n), - .f2h_sdram0_clk (vbuf_clk), - .f2h_sdram0_ADDRESS (f2h_vbuf_address), - .f2h_sdram0_BURSTCOUNT (f2h_vbuf_burstcount), - .f2h_sdram0_WAITREQUEST (f2h_vbuf_waitrequest), - .f2h_sdram0_READDATA (f2h_vbuf_readdata), - .f2h_sdram0_READDATAVALID (f2h_vbuf_readdatavalid), - .f2h_sdram0_READ (f2h_vbuf_read), - .f2h_sdram0_WRITEDATA (f2h_vbuf_writedata), - .f2h_sdram0_BYTEENABLE (f2h_vbuf_byteenable), - .f2h_sdram0_WRITE (f2h_vbuf_write), - .f2h_sdram1_clk (ram1_clk), - .f2h_sdram1_ADDRESS (f2h_ram1_address), - .f2h_sdram1_BURSTCOUNT (f2h_ram1_burstcount), - .f2h_sdram1_WAITREQUEST (f2h_ram1_waitrequest), - .f2h_sdram1_READDATA (f2h_ram1_readdata), - .f2h_sdram1_READDATAVALID (f2h_ram1_readdatavalid), - .f2h_sdram1_READ (f2h_ram1_read), - .f2h_sdram1_WRITEDATA (f2h_ram1_writedata), - .f2h_sdram1_BYTEENABLE (f2h_ram1_byteenable), - .f2h_sdram1_WRITE (f2h_ram1_write), - .f2h_sdram2_clk (ram2_clk), - .f2h_sdram2_ADDRESS (f2h_ram2_address), - .f2h_sdram2_BURSTCOUNT (f2h_ram2_burstcount), - .f2h_sdram2_WAITREQUEST (f2h_ram2_waitrequest), - .f2h_sdram2_READDATA (f2h_ram2_readdata), - .f2h_sdram2_READDATAVALID (f2h_ram2_readdatavalid), - .f2h_sdram2_READ (f2h_ram2_read), - .f2h_sdram2_WRITEDATA (f2h_ram2_writedata), - .f2h_sdram2_BYTEENABLE (f2h_ram2_byteenable), - .f2h_sdram2_WRITE (f2h_ram2_write) -); - -wire hps_h2f_reset_n; - -reg init_reset_n = 0; -always @(posedge clock) begin - integer timeout = 0; - - if(timeout < 2000000) begin - init_reset_n <= 0; - timeout <= timeout + 1; - end - else init_reset_n <= 1; -end - -endmodule - - -module sysmem_HPS_fpga_interfaces -( - // h2f_reset - output wire [1 - 1 : 0 ] h2f_rst_n - - // f2h_cold_reset_req - ,input wire [1 - 1 : 0 ] f2h_cold_rst_req_n - - // f2h_warm_reset_req - ,input wire [1 - 1 : 0 ] f2h_warm_rst_req_n - - // h2f_user0_clock - ,output wire [1 - 1 : 0 ] h2f_user0_clk - - // f2h_sdram0_data - ,input wire [28 - 1 : 0 ] f2h_sdram0_ADDRESS - ,input wire [8 - 1 : 0 ] f2h_sdram0_BURSTCOUNT - ,output wire [1 - 1 : 0 ] f2h_sdram0_WAITREQUEST - ,output wire [128 - 1 : 0 ] f2h_sdram0_READDATA - ,output wire [1 - 1 : 0 ] f2h_sdram0_READDATAVALID - ,input wire [1 - 1 : 0 ] f2h_sdram0_READ - ,input wire [128 - 1 : 0 ] f2h_sdram0_WRITEDATA - ,input wire [16 - 1 : 0 ] f2h_sdram0_BYTEENABLE - ,input wire [1 - 1 : 0 ] f2h_sdram0_WRITE - - // f2h_sdram0_clock - ,input wire [1 - 1 : 0 ] f2h_sdram0_clk - - // f2h_sdram1_data - ,input wire [29 - 1 : 0 ] f2h_sdram1_ADDRESS - ,input wire [8 - 1 : 0 ] f2h_sdram1_BURSTCOUNT - ,output wire [1 - 1 : 0 ] f2h_sdram1_WAITREQUEST - ,output wire [64 - 1 : 0 ] f2h_sdram1_READDATA - ,output wire [1 - 1 : 0 ] f2h_sdram1_READDATAVALID - ,input wire [1 - 1 : 0 ] f2h_sdram1_READ - ,input wire [64 - 1 : 0 ] f2h_sdram1_WRITEDATA - ,input wire [8 - 1 : 0 ] f2h_sdram1_BYTEENABLE - ,input wire [1 - 1 : 0 ] f2h_sdram1_WRITE - - // f2h_sdram1_clock - ,input wire [1 - 1 : 0 ] f2h_sdram1_clk - - // f2h_sdram2_data - ,input wire [29 - 1 : 0 ] f2h_sdram2_ADDRESS - ,input wire [8 - 1 : 0 ] f2h_sdram2_BURSTCOUNT - ,output wire [1 - 1 : 0 ] f2h_sdram2_WAITREQUEST - ,output wire [64 - 1 : 0 ] f2h_sdram2_READDATA - ,output wire [1 - 1 : 0 ] f2h_sdram2_READDATAVALID - ,input wire [1 - 1 : 0 ] f2h_sdram2_READ - ,input wire [64 - 1 : 0 ] f2h_sdram2_WRITEDATA - ,input wire [8 - 1 : 0 ] f2h_sdram2_BYTEENABLE - ,input wire [1 - 1 : 0 ] f2h_sdram2_WRITE - - // f2h_sdram2_clock - ,input wire [1 - 1 : 0 ] f2h_sdram2_clk -); - - -wire [29 - 1 : 0] intermediate; -assign intermediate[0:0] = ~intermediate[1:1]; -assign intermediate[8:8] = intermediate[4:4]|intermediate[7:7]; -assign intermediate[2:2] = intermediate[9:9]; -assign intermediate[3:3] = intermediate[9:9]; -assign intermediate[5:5] = intermediate[9:9]; -assign intermediate[6:6] = intermediate[9:9]; -assign intermediate[10:10] = intermediate[9:9]; -assign intermediate[11:11] = ~intermediate[12:12]; -assign intermediate[17:17] = intermediate[14:14]|intermediate[16:16]; -assign intermediate[13:13] = intermediate[18:18]; -assign intermediate[15:15] = intermediate[18:18]; -assign intermediate[19:19] = intermediate[18:18]; -assign intermediate[20:20] = ~intermediate[21:21]; -assign intermediate[26:26] = intermediate[23:23]|intermediate[25:25]; -assign intermediate[22:22] = intermediate[27:27]; -assign intermediate[24:24] = intermediate[27:27]; -assign intermediate[28:28] = intermediate[27:27]; -assign f2h_sdram0_WAITREQUEST[0:0] = intermediate[0:0]; -assign f2h_sdram1_WAITREQUEST[0:0] = intermediate[11:11]; -assign f2h_sdram2_WAITREQUEST[0:0] = intermediate[20:20]; -assign intermediate[4:4] = f2h_sdram0_READ[0:0]; -assign intermediate[7:7] = f2h_sdram0_WRITE[0:0]; -assign intermediate[9:9] = f2h_sdram0_clk[0:0]; -assign intermediate[14:14] = f2h_sdram1_READ[0:0]; -assign intermediate[16:16] = f2h_sdram1_WRITE[0:0]; -assign intermediate[18:18] = f2h_sdram1_clk[0:0]; -assign intermediate[23:23] = f2h_sdram2_READ[0:0]; -assign intermediate[25:25] = f2h_sdram2_WRITE[0:0]; -assign intermediate[27:27] = f2h_sdram2_clk[0:0]; - -cyclonev_hps_interface_clocks_resets clocks_resets( - .f2h_warm_rst_req_n({ - f2h_warm_rst_req_n[0:0] // 0:0 - }) -,.f2h_pending_rst_ack({ - 1'b1 // 0:0 - }) -,.f2h_dbg_rst_req_n({ - 1'b1 // 0:0 - }) -,.h2f_rst_n({ - h2f_rst_n[0:0] // 0:0 - }) -,.f2h_cold_rst_req_n({ - f2h_cold_rst_req_n[0:0] // 0:0 - }) -,.h2f_user0_clk({ - h2f_user0_clk[0:0] // 0:0 - }) -); - - -cyclonev_hps_interface_dbg_apb debug_apb( - .DBG_APB_DISABLE({ - 1'b0 // 0:0 - }) -,.P_CLK_EN({ - 1'b0 // 0:0 - }) -); - - -cyclonev_hps_interface_tpiu_trace tpiu( - .traceclk_ctl({ - 1'b1 // 0:0 - }) -); - - -cyclonev_hps_interface_boot_from_fpga boot_from_fpga( - .boot_from_fpga_ready({ - 1'b0 // 0:0 - }) -,.boot_from_fpga_on_failure({ - 1'b0 // 0:0 - }) -,.bsel_en({ - 1'b0 // 0:0 - }) -,.csel_en({ - 1'b0 // 0:0 - }) -,.csel({ - 2'b01 // 1:0 - }) -,.bsel({ - 3'b001 // 2:0 - }) -); - - -cyclonev_hps_interface_fpga2hps fpga2hps( - .port_size_config({ - 2'b11 // 1:0 - }) -); - - -cyclonev_hps_interface_hps2fpga hps2fpga( - .port_size_config({ - 2'b11 // 1:0 - }) -); - - -cyclonev_hps_interface_fpga2sdram f2sdram( - .cfg_rfifo_cport_map({ - 16'b0010000100000000 // 15:0 - }) -,.cfg_wfifo_cport_map({ - 16'b0010000100000000 // 15:0 - }) -,.rd_ready_3({ - 1'b1 // 0:0 - }) -,.cmd_port_clk_2({ - intermediate[28:28] // 0:0 - }) -,.rd_ready_2({ - 1'b1 // 0:0 - }) -,.cmd_port_clk_1({ - intermediate[19:19] // 0:0 - }) -,.rd_ready_1({ - 1'b1 // 0:0 - }) -,.cmd_port_clk_0({ - intermediate[10:10] // 0:0 - }) -,.rd_ready_0({ - 1'b1 // 0:0 - }) -,.wrack_ready_2({ - 1'b1 // 0:0 - }) -,.wrack_ready_1({ - 1'b1 // 0:0 - }) -,.wrack_ready_0({ - 1'b1 // 0:0 - }) -,.cmd_ready_2({ - intermediate[21:21] // 0:0 - }) -,.cmd_ready_1({ - intermediate[12:12] // 0:0 - }) -,.cmd_ready_0({ - intermediate[1:1] // 0:0 - }) -,.cfg_port_width({ - 12'b000000010110 // 11:0 - }) -,.rd_valid_3({ - f2h_sdram2_READDATAVALID[0:0] // 0:0 - }) -,.rd_valid_2({ - f2h_sdram1_READDATAVALID[0:0] // 0:0 - }) -,.rd_valid_1({ - f2h_sdram0_READDATAVALID[0:0] // 0:0 - }) -,.rd_clk_3({ - intermediate[22:22] // 0:0 - }) -,.rd_data_3({ - f2h_sdram2_READDATA[63:0] // 63:0 - }) -,.rd_clk_2({ - intermediate[13:13] // 0:0 - }) -,.rd_data_2({ - f2h_sdram1_READDATA[63:0] // 63:0 - }) -,.rd_clk_1({ - intermediate[3:3] // 0:0 - }) -,.rd_data_1({ - f2h_sdram0_READDATA[127:64] // 63:0 - }) -,.rd_clk_0({ - intermediate[2:2] // 0:0 - }) -,.rd_data_0({ - f2h_sdram0_READDATA[63:0] // 63:0 - }) -,.cfg_axi_mm_select({ - 6'b000000 // 5:0 - }) -,.cmd_valid_2({ - intermediate[26:26] // 0:0 - }) -,.cmd_valid_1({ - intermediate[17:17] // 0:0 - }) -,.cmd_valid_0({ - intermediate[8:8] // 0:0 - }) -,.cfg_cport_rfifo_map({ - 18'b000000000011010000 // 17:0 - }) -,.wr_data_3({ - 2'b00 // 89:88 - ,f2h_sdram2_BYTEENABLE[7:0] // 87:80 - ,16'b0000000000000000 // 79:64 - ,f2h_sdram2_WRITEDATA[63:0] // 63:0 - }) -,.wr_data_2({ - 2'b00 // 89:88 - ,f2h_sdram1_BYTEENABLE[7:0] // 87:80 - ,16'b0000000000000000 // 79:64 - ,f2h_sdram1_WRITEDATA[63:0] // 63:0 - }) -,.wr_data_1({ - 2'b00 // 89:88 - ,f2h_sdram0_BYTEENABLE[15:8] // 87:80 - ,16'b0000000000000000 // 79:64 - ,f2h_sdram0_WRITEDATA[127:64] // 63:0 - }) -,.cfg_cport_type({ - 12'b000000111111 // 11:0 - }) -,.wr_data_0({ - 2'b00 // 89:88 - ,f2h_sdram0_BYTEENABLE[7:0] // 87:80 - ,16'b0000000000000000 // 79:64 - ,f2h_sdram0_WRITEDATA[63:0] // 63:0 - }) -,.cfg_cport_wfifo_map({ - 18'b000000000011010000 // 17:0 - }) -,.wr_clk_3({ - intermediate[24:24] // 0:0 - }) -,.wr_clk_2({ - intermediate[15:15] // 0:0 - }) -,.wr_clk_1({ - intermediate[6:6] // 0:0 - }) -,.wr_clk_0({ - intermediate[5:5] // 0:0 - }) -,.cmd_data_2({ - 18'b000000000000000000 // 59:42 - ,f2h_sdram2_BURSTCOUNT[7:0] // 41:34 - ,3'b000 // 33:31 - ,f2h_sdram2_ADDRESS[28:0] // 30:2 - ,intermediate[25:25] // 1:1 - ,intermediate[23:23] // 0:0 - }) -,.cmd_data_1({ - 18'b000000000000000000 // 59:42 - ,f2h_sdram1_BURSTCOUNT[7:0] // 41:34 - ,3'b000 // 33:31 - ,f2h_sdram1_ADDRESS[28:0] // 30:2 - ,intermediate[16:16] // 1:1 - ,intermediate[14:14] // 0:0 - }) -,.cmd_data_0({ - 18'b000000000000000000 // 59:42 - ,f2h_sdram0_BURSTCOUNT[7:0] // 41:34 - ,4'b0000 // 33:30 - ,f2h_sdram0_ADDRESS[27:0] // 29:2 - ,intermediate[7:7] // 1:1 - ,intermediate[4:4] // 0:0 - }) -); - -endmodule diff --git a/sys/vga_out.sv b/sys/vga_out.sv deleted file mode 100644 index 4160635..0000000 --- a/sys/vga_out.sv +++ /dev/null @@ -1,73 +0,0 @@ - -module vga_out -( - input clk, - input ypbpr_en, - - input hsync, - input vsync, - input csync, - input de, - - input [23:0] din, - output [23:0] dout, - - output reg hsync_o, - output reg vsync_o, - output reg csync_o, - output reg de_o -); - -wire [7:0] red = din[23:16]; -wire [7:0] green = din[15:8]; -wire [7:0] blue = din[7:0]; - -// http://marsee101.blog19.fc2.com/blog-entry-2311.html - - -// Y = 0.301*R + 0.586*G + 0.113*B (Y = 0.299*R + 0.587*G + 0.114*B) -// Pb = 128 - 0.168*R - 0.332*G + 0.500*B (Pb = -0.169*R - 0.331*G + 0.500*B) -// Pr = 128 + 0.500*R - 0.418*G - 0.082*B (Pr = 0.500*R - 0.419*G - 0.081*B) - -reg [7:0] y, pb, pr; -reg [23:0] rgb; -always @(posedge clk) begin - reg [18:0] y_1r, pb_1r, pr_1r; - reg [18:0] y_1g, pb_1g, pr_1g; - reg [18:0] y_1b, pb_1b, pr_1b; - reg [18:0] y_2, pb_2, pr_2; - reg [23:0] din1, din2; - reg hsync2, vsync2, csync2, de2; - reg hsync1, vsync1, csync1, de1; - - y_1r <= {red, 6'd0} + {red, 3'd0} + {red, 2'd0} + red; - pb_1r <= 19'd32768 - ({red, 5'd0} + {red, 3'd0} + {red, 1'd0}); - pr_1r <= 19'd32768 + {red, 7'd0}; - - y_1g <= {green, 7'd0} + {green, 4'd0} + {green, 2'd0} + {green, 1'd0}; - pb_1g <= {green, 6'd0} + {green, 4'd0} + {green, 2'd0} + green; - pr_1g <= {green, 6'd0} + {green, 5'd0} + {green, 3'd0} + {green, 1'd0}; - - y_1b <= {blue, 4'd0} + {blue, 3'd0} + {blue, 2'd0} + blue; - pb_1b <= {blue, 7'd0}; - pr_1b <= {blue, 4'd0} + {blue, 2'd0} + blue; - - y_2 <= y_1r + y_1g + y_1b; - pb_2 <= pb_1r - pb_1g + pb_1b; - pr_2 <= pr_1r - pr_1g - pr_1b; - - y <= y_2[18] ? 8'd0 : y_2[16] ? 8'd255 : y_2[15:8]; - pb <= pb_2[18] ? 8'd0 : pb_2[16] ? 8'd255 : pb_2[15:8]; - pr <= pr_2[18] ? 8'd0 : pr_2[16] ? 8'd255 : pr_2[15:8]; - - hsync_o <= hsync2; hsync2 <= hsync1; hsync1 <= hsync; - vsync_o <= vsync2; vsync2 <= vsync1; vsync1 <= vsync; - csync_o <= csync2; csync2 <= csync1; csync1 <= csync; - de_o <= de2; de2 <= de1; de1 <= de; - - rgb <= din2; din2 <= din1; din1 <= din; -end - -assign dout = ypbpr_en ? {pr, y, pb} : rgb; - -endmodule diff --git a/sys/video_cleaner.sv b/sys/video_cleaner.sv deleted file mode 100644 index b0acbc3..0000000 --- a/sys/video_cleaner.sv +++ /dev/null @@ -1,99 +0,0 @@ -// -// -// Copyright (c) 2018 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -module video_cleaner -( - input clk_vid, - input ce_pix, - - input [7:0] R, - input [7:0] G, - input [7:0] B, - - input HSync, - input VSync, - input HBlank, - input VBlank, - - //optional de - input DE_in, - - // video output signals - output reg [7:0] VGA_R, - output reg [7:0] VGA_G, - output reg [7:0] VGA_B, - output reg VGA_VS, - output reg VGA_HS, - output VGA_DE, - - // optional aligned blank - output reg HBlank_out, - output reg VBlank_out, - - // optional aligned de - output reg DE_out -); - -wire hs, vs; -s_fix sync_v(clk_vid, HSync, hs); -s_fix sync_h(clk_vid, VSync, vs); - -wire hbl = hs | HBlank; -wire vbl = vs | VBlank; - -assign VGA_DE = ~(HBlank_out | VBlank_out); - -always @(posedge clk_vid) begin - if(ce_pix) begin - HBlank_out <= hbl; - - VGA_HS <= hs; - if(~VGA_HS & hs) VGA_VS <= vs; - - VGA_R <= R; - VGA_G <= G; - VGA_B <= B; - DE_out <= DE_in; - - if(HBlank_out & ~hbl) VBlank_out <= vbl; - end -end - -endmodule - -module s_fix -( - input clk, - - input sync_in, - output sync_out -); - -assign sync_out = sync_in ^ pol; - -reg pol; -always @(posedge clk) begin - integer pos = 0, neg = 0, cnt = 0; - reg s1,s2; - - s1 <= sync_in; - s2 <= s1; - - if(~s2 & s1) neg <= cnt; - if(s2 & ~s1) pos <= cnt; - - cnt <= cnt + 1; - if(s2 != s1) cnt <= 0; - - pol <= pos > neg; -end - -endmodule diff --git a/sys/video_freak.sv b/sys/video_freak.sv deleted file mode 100644 index 65375cd..0000000 --- a/sys/video_freak.sv +++ /dev/null @@ -1,329 +0,0 @@ -// -// -// Video crop -// Copyright (c) 2020 Grabulosaure, (c) 2021 Alexey Melnikov -// -// Integer scaling -// Copyright (c) 2021 Alexey Melnikov -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -module video_freak -( - input CLK_VIDEO, - input CE_PIXEL, - input VGA_VS, - input [11:0] HDMI_WIDTH, - input [11:0] HDMI_HEIGHT, - output VGA_DE, - output reg [12:0] VIDEO_ARX, - output reg [12:0] VIDEO_ARY, - - input VGA_DE_IN, - input [11:0] ARX, - input [11:0] ARY, - input [11:0] CROP_SIZE, - input [4:0] CROP_OFF, // -16...+15 - input [2:0] SCALE //0 - normal, 1 - V-integer, 2 - HV-Integer-, 3 - HV-Integer+, 4 - HV-Integer -); - -reg mul_start; -wire mul_run; -reg [11:0] mul_arg1, mul_arg2; -wire [23:0] mul_res; -sys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res); - -reg vde; -reg [11:0] arxo,aryo; -reg [11:0] vsize; -reg [11:0] hsize; - -always @(posedge CLK_VIDEO) begin - reg old_de, old_vs,ovde; - reg [11:0] vtot,vcpt,vcrop,voff; - reg [11:0] hcpt; - reg [11:0] vadj; - reg [23:0] ARXG,ARYG; - reg [11:0] arx,ary; - reg [1:0] vcalc; - - if (CE_PIXEL) begin - old_de <= VGA_DE_IN; - old_vs <= VGA_VS; - if (VGA_VS & ~old_vs) begin - vcpt <= 0; - vtot <= vcpt; - vcalc <= 1; - vcrop <= (CROP_SIZE >= vcpt) ? 12'd0 : CROP_SIZE; - end - - if (VGA_DE_IN) hcpt <= hcpt + 1'd1; - if (~VGA_DE_IN & old_de) begin - vcpt <= vcpt + 1'd1; - if(!vcpt) hsize <= hcpt; - hcpt <= 0; - end - end - - arx <= ARX; - ary <= ARY; - - vsize <= vcrop ? vcrop : vtot; - - mul_start <= 0; - - if(!vcrop || !ary || !arx) begin - arxo <= arx; - aryo <= ary; - end - else if (vcalc) begin - if(~mul_start & ~mul_run) begin - vcalc <= vcalc + 1'd1; - case(vcalc) - 1: begin - mul_arg1 <= arx; - mul_arg2 <= vtot; - mul_start <= 1; - end - - 2: begin - ARXG <= mul_res; - mul_arg1 <= ary; - mul_arg2 <= vcrop; - mul_start <= 1; - end - - 3: begin - ARYG <= mul_res; - end - endcase - end - end - else if (ARXG[23] | ARYG[23]) begin - arxo <= ARXG[23:12]; - aryo <= ARYG[23:12]; - end - else begin - ARXG <= ARXG << 1; - ARYG <= ARYG << 1; - end - - vadj <= (vtot-vcrop) + {{6{CROP_OFF[4]}},CROP_OFF,1'b0}; - voff <= vadj[11] ? 12'd0 : ((vadj[11:1] + vcrop) > vtot) ? vtot-vcrop : vadj[11:1]; - ovde <= ((vcpt >= voff) && (vcpt < (vcrop + voff))) || !vcrop; - vde <= ovde; -end - -assign VGA_DE = vde & VGA_DE_IN; - -video_scale_int scale -( - .CLK_VIDEO(CLK_VIDEO), - .HDMI_WIDTH(HDMI_WIDTH), - .HDMI_HEIGHT(HDMI_HEIGHT), - .SCALE(SCALE), - .hsize(hsize), - .vsize(vsize), - .arx_i(arxo), - .ary_i(aryo), - .arx_o(VIDEO_ARX), - .ary_o(VIDEO_ARY) -); - -endmodule - - -module video_scale_int -( - input CLK_VIDEO, - - input [11:0] HDMI_WIDTH, - input [11:0] HDMI_HEIGHT, - - input [2:0] SCALE, - - input [11:0] hsize, - input [11:0] vsize, - - input [11:0] arx_i, - input [11:0] ary_i, - - output reg [12:0] arx_o, - output reg [12:0] ary_o -); - -reg div_start; -wire div_run; -reg [23:0] div_num; -reg [11:0] div_den; -wire [23:0] div_res; -sys_udiv #(24,12) div(CLK_VIDEO,div_start,div_run, div_num,div_den,div_res); - -reg mul_start; -wire mul_run; -reg [11:0] mul_arg1, mul_arg2; -wire [23:0] mul_res; -sys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res); - -always @(posedge CLK_VIDEO) begin - reg [11:0] oheight,htarget,wres,hinteger,wideres; - reg [12:0] arxf,aryf; - reg [3:0] cnt; - reg narrow; - - div_start <= 0; - mul_start <= 0; - - if (!SCALE || (!ary_i && arx_i)) begin - arxf <= arx_i; - aryf <= ary_i; - end - else if(~div_start & ~div_run & ~mul_start & ~mul_run) begin - cnt <= cnt + 1'd1; - case(cnt) - // example ideal and non-ideal cases: - // [1] 720x400 4:3 VGA 80x25 text-mode (non-square pixels) - // [2] 640x480 4:3 VGA graphics mode (square pixels) - // [3] 512x512 4:3 X68000 graphics mode (non-square pixels) - 0: begin - div_num <= HDMI_HEIGHT; - div_den <= vsize; - div_start <= 1; - end - // [1] 1080 / 400 -> 2 - // [2] 1080 / 480 -> 2 - // [3] 1080 / 512 -> 2 - - 1: if(!div_res[11:0]) begin - // screen resolution is lower than video resolution. - // Integer scaling is impossible. - arxf <= arx_i; - aryf <= ary_i; - cnt <= 0; - end - else begin - mul_arg1 <= vsize; - mul_arg2 <= div_res[11:0]; - mul_start <= 1; - end - // [1] 1080 / 400 * 400 -> 800 - // [2] 1080 / 480 * 480 -> 960 - // [3] 1080 / 512 * 512 -> 1024 - - 2: begin - oheight <= mul_res[11:0]; - if(!ary_i) begin - cnt <= 8; - end - end - - 3: begin - mul_arg1 <= mul_res[11:0]; - mul_arg2 <= arx_i; - mul_start <= 1; - end - // [1] 1080 / 400 * 400 * 4 -> 3200 - // [2] 1080 / 480 * 480 * 4 -> 3840 - // [3] 1080 / 512 * 512 * 4 -> 4096 - - 4: begin - div_num <= mul_res; - div_den <= ary_i; - div_start <= 1; - end - // [1] 1080 / 480 * 480 * 4 / 3 -> 1066 - // [2] 1080 / 480 * 480 * 4 / 3 -> 1280 - // [3] 1080 / 512 * 512 * 4 / 3 -> 1365 - // saved as htarget - - 5: begin - htarget <= div_res[11:0]; - div_num <= div_res; - div_den <= hsize; - div_start <= 1; - end - // computes wide scaling factor as a ceiling division - // [1] 1080 / 400 * 400 * 4 / 3 / 720 -> 1 - // [2] 1080 / 480 * 480 * 4 / 3 / 640 -> 2 - // [3] 1080 / 512 * 512 * 4 / 3 / 512 -> 2 - - 6: begin - mul_arg1 <= hsize; - mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1; - mul_start <= 1; - end - // [1] 1080 / 400 * 400 * 4 / 3 / 720 * 720 -> 720 - // [2] 1080 / 480 * 480 * 4 / 3 / 640 * 640 -> 1280 - // [3] 1080 / 512 * 512 * 4 / 3 / 512 * 512 -> 1024 - - 7: if(mul_res <= HDMI_WIDTH) begin - hinteger = mul_res[11:0]; - cnt <= 12; - end - - 8: begin - div_num <= HDMI_WIDTH; - div_den <= hsize; - div_start <= 1; - end - // [1] 1920 / 720 -> 2 - // [2] 1920 / 640 -> 3 - // [3] 1920 / 512 -> 3 - - 9: begin - mul_arg1 <= hsize; - mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1; - mul_start <= 1; - end - // [1] 1920 / 720 * 720 -> 1440 - // [2] 1920 / 640 * 640 -> 1920 - // [3] 1920 / 512 * 512 -> 1536 - - 10: begin - hinteger <= mul_res[11:0]; - mul_arg1 <= vsize; - mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1; - mul_start <= 1; - end - - 11: begin - oheight <= mul_res[11:0]; - end - - 12: begin - wideres <= hinteger + hsize; - narrow <= ((htarget - hinteger) <= (wideres - htarget)) || (wideres > HDMI_WIDTH); - wres <= hinteger == htarget ? hinteger : wideres; - end - // [1] 1066 - 720 = 346 <= 1440 - 1066 = 374 || 1440 > 1920 -> true - // [2] 1280 - 1280 = 0 <= 1920 - 1280 = 640 || 1920 > 1920 -> true - // [3] 1365 - 1024 = 341 <= 1536 - 1365 = 171 || 1536 > 1920 -> false - // 1. narrow flag is true when mul_res[11:0] narrow width is closer to - // htarget aspect ratio target width or when wideres wider width - // does not fit to the screen. - // 2. wres becomes wideres only when mul_res[11:0] narrow width not equal - // to target width, meaning it is not optimal for source aspect ratio. - // otherwise it is set to narrow width that is optimal. - - 13: begin - case(SCALE) - 2: arxf <= {1'b1, hinteger}; - 3: arxf <= {1'b1, (wres > HDMI_WIDTH) ? hinteger : wres}; - 4: arxf <= {1'b1, narrow ? hinteger : wres}; - default: arxf <= {1'b1, div_num[11:0]}; - endcase - aryf <= {1'b1, oheight}; - end - endcase - end - - arx_o <= arxf; - ary_o <= aryf; -end - -endmodule diff --git a/sys/video_freezer.sv b/sys/video_freezer.sv deleted file mode 100644 index 24d2c65..0000000 --- a/sys/video_freezer.sv +++ /dev/null @@ -1,143 +0,0 @@ -// -// video freeze with sync -// (C) Alexey Melnikov -// -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - - -module video_freezer -( - input clk, - - output sync, - input freeze, - - input hs_in, - input vs_in, - input hbl_in, - input vbl_in, - - output hs_out, - output vs_out, - output hbl_out, - output vbl_out -); - -sync_lock #(33) vs_lock -( - .clk(clk), - .sync_in(vs_in), - .sync_out(vs_out), - .de_in(vbl_in), - .de_out(vbl_out), - .freeze(freeze) -); - -wire sync_pt; -sync_lock #(21) hs_lock -( - .clk(clk), - .sync_in(hs_in), - .sync_out(hs_out), - .de_in(hbl_in), - .de_out(hbl_out), - .freeze(freeze), - .sync_pt(sync_pt) -); - -reg sync_o; -always @(posedge clk) begin - reg old_hs, old_vs; - reg vs_sync; - - old_vs <= vs_out; - - if(~old_vs & vs_out) vs_sync <= 1; - if(sync_pt & vs_sync) begin - vs_sync <= 0; - sync_o <= ~sync_o; - end -end - -assign sync = sync_o; - -endmodule - - -module sync_lock #(parameter WIDTH) -( - input clk, - - input sync_in, - input de_in, - - output sync_out, - output de_out, - - input freeze, - output sync_pt, - output valid -); - -reg [WIDTH-1:0] f_len, s_len, de_start, de_end; -reg sync_valid; - -reg old_sync; -always @(posedge clk) old_sync <= sync_in; - -always @(posedge clk) begin - reg [WIDTH-1:0] cnti; - reg f_valid; - reg old_de; - - cnti <= cnti + 1'd1; - if(~old_sync & sync_in) begin - if(sync_valid) f_len <= cnti; - f_valid <= 1; - sync_valid <= f_valid; - cnti <= 0; - end - - if(old_sync & ~sync_in & sync_valid) s_len <= cnti; - - old_de <= de_in; - if(~old_de & de_in & sync_valid) de_start <= cnti; - if(old_de & ~de_in & sync_valid) de_end <= cnti; - - if(freeze) {f_valid, sync_valid} <= 0; -end - -reg sync_o, de_o, sync_o_pre; -always @(posedge clk) begin - reg [WIDTH-1:0] cnto; - - cnto <= cnto + 1'd1; - if(old_sync & ~sync_in & sync_valid) cnto <= s_len + 2'd2; - if(cnto == f_len) cnto <= 0; - - sync_o_pre <= (cnto == (s_len>>1)); // middle in sync - if(cnto == f_len) sync_o <= 1; - if(cnto == s_len) sync_o <= 0; - if(cnto == de_start) de_o <= 1; - if(cnto == de_end) de_o <= 0; -end - -assign sync_out = freeze ? sync_o : sync_in; -assign valid = sync_valid; -assign sync_pt = sync_o_pre; -assign de_out = freeze ? de_o : de_in; - -endmodule diff --git a/sys/video_mixer.sv b/sys/video_mixer.sv deleted file mode 100644 index e53e1c0..0000000 --- a/sys/video_mixer.sv +++ /dev/null @@ -1,219 +0,0 @@ -// -// -// Copyright (c) 2017,2021 Alexey Melnikov -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -// -// LINE_LENGTH: Length of display line in pixels when HBlank = 0; -// HALF_DEPTH: If =1 then color dept is 4 bits per component -// -// altera message_off 10720 -// altera message_off 12161 - -module video_mixer -#( - parameter LINE_LENGTH = 768, - parameter HALF_DEPTH = 0, - parameter GAMMA = 0 -) -( - input CLK_VIDEO, // should be multiple by (ce_pix*4) - output reg CE_PIXEL, // output pixel clock enable - - input ce_pix, // input pixel clock or clock_enable - - input scandoubler, - input hq2x, // high quality 2x scaling - - inout [21:0] gamma_bus, - - // color - input [DWIDTH:0] R, - input [DWIDTH:0] G, - input [DWIDTH:0] B, - - // Positive pulses. - input HSync, - input VSync, - input HBlank, - input VBlank, - - // Freeze engine - // HDMI: displays last frame - // VGA: black screen with HSync and VSync - input HDMI_FREEZE, - output freeze_sync, - - // video output signals - output reg [7:0] VGA_R, - output reg [7:0] VGA_G, - output reg [7:0] VGA_B, - output reg VGA_VS, - output reg VGA_HS, - output reg VGA_DE -); - -localparam DWIDTH = HALF_DEPTH ? 3 : 7; -localparam DWIDTH_SD = GAMMA ? 7 : DWIDTH; -localparam HALF_DEPTH_SD = GAMMA ? 0 : HALF_DEPTH; - -wire frz_hs, frz_vs; -wire frz_hbl, frz_vbl; -video_freezer freezer -( - .clk(CLK_VIDEO), - .freeze(HDMI_FREEZE), - .hs_in(HSync), - .vs_in(VSync), - .hbl_in(HBlank), - .vbl_in(VBlank), - .sync(freeze_sync), - .hs_out(frz_hs), - .vs_out(frz_vs), - .hbl_out(frz_hbl), - .vbl_out(frz_vbl) -); - -reg frz; -always @(posedge CLK_VIDEO) begin - reg frz1; - - frz1 <= HDMI_FREEZE; - frz <= frz1; -end - -generate - if(GAMMA && HALF_DEPTH) begin - wire [7:0] R_in = frz ? 8'd0 : {R,R}; - wire [7:0] G_in = frz ? 8'd0 : {G,G}; - wire [7:0] B_in = frz ? 8'd0 : {B,B}; - end else begin - wire [DWIDTH:0] R_in = frz ? 1'd0 : R; - wire [DWIDTH:0] G_in = frz ? 1'd0 : G; - wire [DWIDTH:0] B_in = frz ? 1'd0 : B; - end -endgenerate - -wire hs_g, vs_g; -wire hb_g, vb_g; -wire [DWIDTH_SD:0] R_gamma, G_gamma, B_gamma; - -generate - if(GAMMA) begin - assign gamma_bus[21] = 1; - gamma_corr gamma( - .clk_sys(gamma_bus[20]), - .clk_vid(CLK_VIDEO), - .ce_pix(ce_pix), - - .gamma_en(gamma_bus[19]), - .gamma_wr(gamma_bus[18]), - .gamma_wr_addr(gamma_bus[17:8]), - .gamma_value(gamma_bus[7:0]), - - .HSync(frz_hs), - .VSync(frz_vs), - .HBlank(frz_hbl), - .VBlank(frz_vbl), - .RGB_in({R_in,G_in,B_in}), - - .HSync_out(hs_g), - .VSync_out(vs_g), - .HBlank_out(hb_g), - .VBlank_out(vb_g), - .RGB_out({R_gamma,G_gamma,B_gamma}) - ); - end else begin - assign gamma_bus[21] = 0; - assign {R_gamma,G_gamma,B_gamma} = {R_in,G_in,B_in}; - assign {hs_g, vs_g, hb_g, vb_g} = {frz_hs, frz_vs, frz_hbl, frz_vbl}; - end -endgenerate - -wire [DWIDTH_SD:0] R_sd; -wire [DWIDTH_SD:0] G_sd; -wire [DWIDTH_SD:0] B_sd; -wire hs_sd, vs_sd, hb_sd, vb_sd, ce_pix_sd; - -scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH_SD)) sd -( - .clk_vid(CLK_VIDEO), - .hq2x(hq2x), - - .ce_pix(ce_pix), - .hs_in(hs_g), - .vs_in(vs_g), - .hb_in(hb_g), - .vb_in(vb_g), - .r_in(R_gamma), - .g_in(G_gamma), - .b_in(B_gamma), - - .ce_pix_out(ce_pix_sd), - .hs_out(hs_sd), - .vs_out(vs_sd), - .hb_out(hb_sd), - .vb_out(vb_sd), - .r_out(R_sd), - .g_out(G_sd), - .b_out(B_sd) -); - -wire [DWIDTH_SD:0] rt = (scandoubler ? R_sd : R_gamma); -wire [DWIDTH_SD:0] gt = (scandoubler ? G_sd : G_gamma); -wire [DWIDTH_SD:0] bt = (scandoubler ? B_sd : B_gamma); - -always @(posedge CLK_VIDEO) begin - reg [7:0] r,g,b; - reg hde,vde,hs,vs, old_vs; - reg old_hde; - reg old_ce; - reg ce_osc, fs_osc; - - old_ce <= ce_pix; - ce_osc <= ce_osc | (old_ce ^ ce_pix); - - old_vs <= vs; - if(~old_vs & vs) begin - fs_osc <= ce_osc; - ce_osc <= 0; - end - - CE_PIXEL <= scandoubler ? ce_pix_sd : fs_osc ? (~old_ce & ce_pix) : ce_pix; - - if(!GAMMA && HALF_DEPTH) begin - r <= {rt,rt}; - g <= {gt,gt}; - b <= {bt,bt}; - end - else begin - r <= rt; - g <= gt; - b <= bt; - end - - hde <= scandoubler ? ~hb_sd : ~hb_g; - vde <= scandoubler ? ~vb_sd : ~vb_g; - vs <= scandoubler ? vs_sd : vs_g; - hs <= scandoubler ? hs_sd : hs_g; - - if(CE_PIXEL) begin - VGA_R <= r; - VGA_G <= g; - VGA_B <= b; - - VGA_VS <= vs; - VGA_HS <= hs; - - old_hde <= hde; - if(old_hde ^ hde) VGA_DE <= vde & hde; - end -end - -endmodule diff --git a/sys/yc_out.sv b/sys/yc_out.sv deleted file mode 100644 index 984fc37..0000000 --- a/sys/yc_out.sv +++ /dev/null @@ -1,233 +0,0 @@ -//============================================================================ -// YC - Luma / Chroma Generation -// Copyright (C) 2022 Mike Simone -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -// -//============================================================================ -/* -Colorspace -Y 0.299R' + 0.587G' + 0.114B' -U 0.492(B' - Y) = 504 (X 1024) -V 0.877(R' - Y) = 898 (X 1024) -*/ -////////////////////////////////////////////////////////// - -module yc_out -( - input clk, - input [39:0] PHASE_INC, - input PAL_EN, - input CVBS, - input [16:0] COLORBURST_RANGE, - - input hsync, - input vsync, - input csync, - input de, - - input [23:0] din, - output [23:0] dout, - - output reg hsync_o, - output reg vsync_o, - output reg csync_o, - output reg de_o -); - -wire [7:0] red = din[23:16]; -wire [7:0] green = din[15:8]; -wire [7:0] blue = din[7:0]; - -logic [9:0] red_1, blue_1, green_1, red_2, blue_2, green_2; - -logic signed [20:0] yr = 0, yb = 0, yg = 0; - -typedef struct { - logic signed [20:0] y; - logic signed [20:0] c; - logic signed [20:0] u; - logic signed [20:0] v; - logic hsync; - logic vsync; - logic csync; - logic de; -} phase_t; - -localparam MAX_PHASES = 7'd8; - -phase_t phase[MAX_PHASES]; -reg unsigned [7:0] Y, C, c, U, V; - - -reg [10:0] cburst_phase; // colorburst counter -reg unsigned [7:0] vref = 'd128; // Voltage reference point (Used for Chroma) -logic [7:0] chroma_LUT_COS; // Chroma cos LUT reference -logic [7:0] chroma_LUT_SIN; // Chroma sin LUT reference -logic [7:0] chroma_LUT_BURST; // Chroma colorburst LUT reference -logic [7:0] chroma_LUT = 8'd0; - -/* -THe following LUT table was calculated by Sin(2*pi*t/2^8) where t: 0 - 255 -*/ - -/************************************* - 8 bit Sine look up Table -**************************************/ -wire signed [10:0] chroma_SIN_LUT[256] = '{ - 11'h000, 11'h006, 11'h00C, 11'h012, 11'h018, 11'h01F, 11'h025, 11'h02B, 11'h031, 11'h037, 11'h03D, 11'h044, 11'h04A, 11'h04F, - 11'h055, 11'h05B, 11'h061, 11'h067, 11'h06D, 11'h072, 11'h078, 11'h07D, 11'h083, 11'h088, 11'h08D, 11'h092, 11'h097, 11'h09C, - 11'h0A1, 11'h0A6, 11'h0AB, 11'h0AF, 11'h0B4, 11'h0B8, 11'h0BC, 11'h0C1, 11'h0C5, 11'h0C9, 11'h0CC, 11'h0D0, 11'h0D4, 11'h0D7, - 11'h0DA, 11'h0DD, 11'h0E0, 11'h0E3, 11'h0E6, 11'h0E9, 11'h0EB, 11'h0ED, 11'h0F0, 11'h0F2, 11'h0F4, 11'h0F5, 11'h0F7, 11'h0F8, - 11'h0FA, 11'h0FB, 11'h0FC, 11'h0FD, 11'h0FD, 11'h0FE, 11'h0FE, 11'h0FE, 11'h0FF, 11'h0FE, 11'h0FE, 11'h0FE, 11'h0FD, 11'h0FD, - 11'h0FC, 11'h0FB, 11'h0FA, 11'h0F8, 11'h0F7, 11'h0F5, 11'h0F4, 11'h0F2, 11'h0F0, 11'h0ED, 11'h0EB, 11'h0E9, 11'h0E6, 11'h0E3, - 11'h0E0, 11'h0DD, 11'h0DA, 11'h0D7, 11'h0D4, 11'h0D0, 11'h0CC, 11'h0C9, 11'h0C5, 11'h0C1, 11'h0BC, 11'h0B8, 11'h0B4, 11'h0AF, - 11'h0AB, 11'h0A6, 11'h0A1, 11'h09C, 11'h097, 11'h092, 11'h08D, 11'h088, 11'h083, 11'h07D, 11'h078, 11'h072, 11'h06D, 11'h067, - 11'h061, 11'h05B, 11'h055, 11'h04F, 11'h04A, 11'h044, 11'h03D, 11'h037, 11'h031, 11'h02B, 11'h025, 11'h01F, 11'h018, 11'h012, - 11'h00C, 11'h006, 11'h000, 11'h7F9, 11'h7F3, 11'h7ED, 11'h7E7, 11'h7E0, 11'h7DA, 11'h7D4, 11'h7CE, 11'h7C8, 11'h7C2, 11'h7BB, - 11'h7B5, 11'h7B0, 11'h7AA, 11'h7A4, 11'h79E, 11'h798, 11'h792, 11'h78D, 11'h787, 11'h782, 11'h77C, 11'h777, 11'h772, 11'h76D, - 11'h768, 11'h763, 11'h75E, 11'h759, 11'h754, 11'h750, 11'h74B, 11'h747, 11'h743, 11'h73E, 11'h73A, 11'h736, 11'h733, 11'h72F, - 11'h72B, 11'h728, 11'h725, 11'h722, 11'h71F, 11'h71C, 11'h719, 11'h716, 11'h714, 11'h712, 11'h70F, 11'h70D, 11'h70B, 11'h70A, - 11'h708, 11'h707, 11'h705, 11'h704, 11'h703, 11'h702, 11'h702, 11'h701, 11'h701, 11'h701, 11'h701, 11'h701, 11'h701, 11'h701, - 11'h702, 11'h702, 11'h703, 11'h704, 11'h705, 11'h707, 11'h708, 11'h70A, 11'h70B, 11'h70D, 11'h70F, 11'h712, 11'h714, 11'h716, - 11'h719, 11'h71C, 11'h71F, 11'h722, 11'h725, 11'h728, 11'h72B, 11'h72F, 11'h733, 11'h736, 11'h73A, 11'h73E, 11'h743, 11'h747, - 11'h74B, 11'h750, 11'h754, 11'h759, 11'h75E, 11'h763, 11'h768, 11'h76D, 11'h772, 11'h777, 11'h77C, 11'h782, 11'h787, 11'h78D, - 11'h792, 11'h798, 11'h79E, 11'h7A4, 11'h7AA, 11'h7B0, 11'h7B5, 11'h7BB, 11'h7C2, 11'h7C8, 11'h7CE, 11'h7D4, 11'h7DA, 11'h7E0, - 11'h7E7, 11'h7ED, 11'h7F3, 11'h7F9 -}; - -logic [39:0] phase_accum; -logic PAL_FLIP = 1'd0; -logic PAL_line_count = 1'd0; - -/************************************** - Generate Luma and Chroma Signals -***************************************/ - -always_ff @(posedge clk) begin - for (logic [3:0] x = 0; x < (MAX_PHASES - 1'd1); x = x + 1'd1) begin - phase[x + 1] <= phase[x]; - end - - // delay red / blue signals to align luma with U/V calculation (Fixes colorbleeding) - red_1 <= red; - blue_1 <= blue; - red_2 <= red_1; - blue_2 <= blue_1; - - // Calculate Luma signal - yr <= {red, 8'd0} + {red, 5'd0}+ {red, 4'd0} + {red, 1'd0}; - yg <= {green, 9'd0} + {green, 6'd0} + {green, 4'd0} + {green, 3'd0} + green; - yb <= {blue, 6'd0} + {blue, 5'd0} + {blue, 4'd0} + {blue, 2'd0} + blue; - phase[0].y <= yr + yg + yb; - - // Generate the LUT values using the phase accumulator reference. - phase_accum <= phase_accum + PHASE_INC; - chroma_LUT <= phase_accum[39:32]; - - // Adjust SINE carrier reference for PAL (Also adjust for PAL Switch) - if (PAL_EN) begin - if (PAL_FLIP) - chroma_LUT_BURST <= chroma_LUT + 8'd160; - else - chroma_LUT_BURST <= chroma_LUT + 8'd96; - end else // Adjust SINE carrier reference for NTSC - chroma_LUT_BURST <= chroma_LUT + 8'd128; - - // Prepare LUT values for sin / cos (+90 degress) - chroma_LUT_SIN <= chroma_LUT; - chroma_LUT_COS <= chroma_LUT + 8'd64; - - // Calculate for U, V - Bit Shift Multiple by u = by * 1024 x 0.492 = 504, v = ry * 1024 x 0.877 = 898 - phase[0].u <= $signed({2'b0 ,(blue_2)}) - $signed({2'b0 ,phase[0].y[17:10]}); - phase[0].v <= $signed({2'b0 , (red_2)}) - $signed({2'b0 ,phase[0].y[17:10]}); - phase[1].u <= 21'($signed({phase[0].u, 8'd0}) + $signed({phase[0].u, 7'd0}) + $signed({phase[0].u, 6'd0}) + $signed({phase[0].u, 5'd0}) + $signed({phase[0].u, 4'd0}) + $signed({phase[0].u, 3'd0})); - phase[1].v <= 21'($signed({phase[0].v, 9'd0}) + $signed({phase[0].v, 8'd0}) + $signed({phase[0].v, 7'd0}) + $signed({phase[0].v, 1'd0})); - - phase[0].c <= vref; - phase[1].c <= phase[0].c; - phase[2].c <= phase[1].c; - phase[3].c <= phase[2].c; - - if (hsync) begin // Reset colorburst counter, as well as the calculated cos / sin values. - cburst_phase <= 'd0; - phase[2].u <= 21'b0; - phase[2].v <= 21'b0; - phase[4].c <= phase[3].c; - - if (PAL_line_count) begin - PAL_FLIP <= ~PAL_FLIP; - PAL_line_count <= ~PAL_line_count; - end - end - else begin // Generate Colorburst for 9 cycles - if (cburst_phase >= COLORBURST_RANGE[16:10] && cburst_phase <= COLORBURST_RANGE[9:0]) begin // Start the color burst signal at 40 samples or 0.9 us - // COLORBURST SIGNAL GENERATION (9 CYCLES ONLY or between count 40 - 240) - phase[2].u <= $signed({chroma_SIN_LUT[chroma_LUT_BURST],5'd0}); - phase[2].v <= 21'b0; - - // Division to scale down the results to fit 8 bit. - if (PAL_EN) - phase[3].u <= $signed(phase[2].u[20:8]) + $signed(phase[2].u[20:10]) + $signed(phase[2].u[20:14]); - else - phase[3].u <= $signed(phase[2].u[20:8]) + $signed(phase[2].u[20:11]) + $signed(phase[2].u[20:12]) + $signed(phase[2].u[20:13]); - - phase[3].v <= phase[2].v; - end else begin // MODULATE U, V for chroma - /* - U,V are both multiplied by 1024 earlier to scale for the decimals in the YUV colorspace conversion. - U and V are both divided by 2^10 which introduce chroma subsampling of 4:1:1 (25% or from 8 bit to 6 bit) - */ - phase[2].u <= $signed((phase[1].u)>>>10) * $signed(chroma_SIN_LUT[chroma_LUT_SIN]); - phase[2].v <= $signed((phase[1].v)>>>10) * $signed(chroma_SIN_LUT[chroma_LUT_COS]); - - // Divide U*sin(wt) and V*cos(wt) to fit results to 8 bit - phase[3].u <= $signed(phase[2].u[20:9]) + $signed(phase[2].u[20:10]) + $signed(phase[2].u[20:14]); - phase[3].v <= $signed(phase[2].v[20:9]) + $signed(phase[2].v[20:10]) + $signed(phase[2].u[20:14]); - end - - // Stop the colorburst timer as its only needed for the initial pulse - if (cburst_phase <= COLORBURST_RANGE[9:0]) - cburst_phase <= cburst_phase + 9'd1; - - // Calculate for chroma (Note: "PAL SWITCH" routine flips V * COS(Wt) every other line) - if (PAL_EN) begin - if (PAL_FLIP) - phase[4].c <= vref + phase[3].u - phase[3].v; - else - phase[4].c <= vref + phase[3].u + phase[3].v; - PAL_line_count <= 1'd1; - end else - phase[4].c <= vref + phase[3].u + phase[3].v; - end - - // Adjust sync timing correctly - phase[1].hsync <= hsync; phase[1].vsync <= vsync; phase[1].csync <= csync; phase[1].de <= de; - phase[2].hsync <= phase[1].hsync; phase[2].vsync <= phase[1].vsync; phase[2].csync <= phase[1].csync; phase[2].de <= phase[1].de; - phase[3].hsync <= phase[2].hsync; phase[3].vsync <= phase[2].vsync; phase[3].csync <= phase[2].csync; phase[3].de <= phase[2].de; - phase[4].hsync <= phase[3].hsync; phase[4].vsync <= phase[3].vsync; phase[4].csync <= phase[3].csync; phase[4].de <= phase[3].de; - hsync_o <= phase[4].hsync; vsync_o <= phase[4].vsync; csync_o <= phase[4].csync; de_o <= phase[4].de; - - phase[1].y <= phase[0].y; phase[2].y <= phase[1].y; phase[3].y <= phase[2].y; phase[4].y <= phase[3].y; phase[5].y <= phase[4].y; - - // Set Chroma / Luma output - C <= CVBS ? 8'd0 : phase[4].c[7:0]; - Y <= CVBS ? ({1'b0, phase[5].y[17:11]} + {1'b0, phase[4].c[7:1]}) : phase[5].y[17:10]; -end - -assign dout = {C, Y, 8'd0}; - -endmodule -