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Update zmaps and zports.

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sorgelig
2018-08-24 02:50:41 +08:00
parent 75334f38f8
commit 94ffbcd437
3 changed files with 404 additions and 549 deletions
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23
src/cpu/zmaps.v
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@ -1,8 +1,8 @@
// This module makes mapping z80 memory accesses into FPGA EABs // This module maps z80 memory accesses into FPGA RAM and ports
module zmaps(
module zmaps
(
// Z80 controls // Z80 controls
input wire clk, input wire clk,
input wire memwr_s, input wire memwr_s,
@ -22,38 +22,35 @@ module zmaps(
input wire dma_cram_we, input wire dma_cram_we,
input wire dma_sfile_we, input wire dma_sfile_we,
// FPRAM controls // write strobes
output wire cram_we, output wire cram_we,
output wire sfile_we output wire sfile_we,
output wire regs_we
); );
// addresses of files withing zmaps // addresses of files withing zmaps
localparam CRAM = 3'b000; localparam CRAM = 3'b000;
localparam SFYS = 3'b001; localparam SFYS = 3'b001;
localparam REGS = 4'b0100;
// control signals // control signals
wire hit = (a[15:12] == fmaddr[3:0]) && fmaddr[4] && memwr_s; wire hit = (a[15:12] == fmaddr[3:0]) && fmaddr[4] && memwr_s;
// write enables // write enables
assign cram_we = dma_req ? dma_cram_we : (a[11:9] == CRAM) && a[0] && hit; assign cram_we = dma_req ? dma_cram_we : (a[11:9] == CRAM) && a[0] && hit;
assign sfile_we = dma_req ? dma_sfile_we : (a[11:9] == SFYS) && a[0] && hit; assign sfile_we = dma_req ? dma_sfile_we : (a[11:9] == SFYS) && a[0] && hit;
assign regs_we = (a[11:8] == REGS) && hit;
// LSB fetching // LSB fetching
assign zma = dma_req ? dma_wraddr : a[8:1]; assign zma = dma_req ? dma_wraddr : a[8:1];
assign zmd = dma_req ? dma_data : {d, zmd0}; // for a[0] = 1 assign zmd = dma_req ? dma_data : {d, zmd0};
reg [7:0] zmd0; reg [7:0] zmd0;
always @(posedge clk) always @(posedge clk) if (!a[0] && hit) zmd0 <= d;
if (!a[0] && hit)
zmd0 <= d; // a[0] = 0
// DMA // DMA
wire dma_req = dma_cram_we || dma_sfile_we; wire dma_req = dma_cram_we || dma_sfile_we;
endmodule endmodule

554
src/cpu/zports.v
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@ -3,168 +3,124 @@
module zports module zports
( (
input wire clk, input clk,
input wire [ 7:0] din, input [7:0] din,
output reg [7:0] dout, output reg [7:0] dout,
output wire dataout, output dataout,
input wire [15:0] a, input [15:0] a,
input wire rst, // system reset input rst, // system reset
input wire loader, // input opfetch,
input wire opfetch,
input wire rd, input rd,
input wire wr, input wr,
input wire rdwr, input rdwr,
input wire iorq, input iorq,
input wire iorq_s, input iorq_s,
input wire iord, input iord,
input wire iord_s, input iord_s,
input wire iowr, input iowr,
input wire iowr_s, input iowr_s,
input wire iorw, input iordwr,
input wire iorw_s, input iordwr_s,
output wire porthit, // when internal port hit occurs, this is 1, else 0; used for iorq1_n iorq2_n on zxbus output porthit, // when internal port hit occurs, this is 1, else 0; used for iorq1_n iorq2_n on zxbus
output wire external_port, // asserts for AY and VG93 accesses output external_port, // asserts for AY and VG93 accesses
output wire zborder_wr, output zborder_wr,
output wire border_wr, output border_wr,
output wire zvpage_wr, output zvpage_wr,
output wire vpage_wr, output vpage_wr,
output wire vconf_wr, output vconf_wr,
output wire gx_offsl_wr, output gx_offsl_wr,
output wire gx_offsh_wr, output gx_offsh_wr,
output wire gy_offsl_wr, output gy_offsl_wr,
output wire gy_offsh_wr, output gy_offsh_wr,
output wire t0x_offsl_wr, output t0x_offsl_wr,
output wire t0x_offsh_wr, output t0x_offsh_wr,
output wire t0y_offsl_wr, output t0y_offsl_wr,
output wire t0y_offsh_wr, output t0y_offsh_wr,
output wire t1x_offsl_wr, output t1x_offsl_wr,
output wire t1x_offsh_wr, output t1x_offsh_wr,
output wire t1y_offsl_wr, output t1y_offsl_wr,
output wire t1y_offsh_wr, output t1y_offsh_wr,
output wire tsconf_wr, output tsconf_wr,
output wire palsel_wr, output palsel_wr,
output wire tmpage_wr, output tmpage_wr,
output wire t0gpage_wr, output t0gpage_wr,
output wire t1gpage_wr, output t1gpage_wr,
output wire sgpage_wr, output sgpage_wr,
output wire hint_beg_wr, output hint_beg_wr ,
output wire vint_begl_wr, output vint_begl_wr,
output wire vint_begh_wr, output vint_begh_wr,
output wire [31:0] xt_page, output [31:0] xt_page,
output reg [4:0] fmaddr, output reg [4:0] fmaddr,
//----Conf----------------- input regs_we,
output reg [7:0] sysconf, output reg [7:0] sysconf,
output reg [7:0] memconf, output reg [7:0] memconf,
output reg [3:0] cacheconf, output reg [3:0] cacheconf,
//------------------------- output reg [7:0] fddvirt,
output reg [3:0] fddvirt,
output [8:0] dmaport_wr,
input dma_act,
output reg [1:0] dmawpdev,
output reg [7:0] intmask, output reg [7:0] intmask,
output wire [8:0] dmaport_wr, input dos,
input wire dma_act, input vdos,
output vdos_on,
output vdos_off,
input wire dos, output ay_bdir,
input wire vdos, output ay_bc1,
output wire vdos_on, output covox_wr,
output wire vdos_off, output beeper_wr,
output wire ay_bdir, input tape_read,
output wire ay_bc1,
output wire covox_wr,
output wire beeper_wr,
input wire [ 1:0] rstrom, input [4:0] keys_in, // keys (port FE)
input wire tape_read, input [7:0] mus_in, // mouse (xxDF)
input [5:0] kj_in,
input wire [ 4:0] keys_in, // keys (port FE) input vg_intrq,
input wire [ 7:0] mus_in, // mouse (xxDF) input vg_drq, // from vg93 module - drq + irq read
input wire [ 5:0] kj_in, output vg_cs_n,
output vg_wrFF,
input wire vg_intrq, output [1:0] drive_sel, // disk drive selection
input wire vg_drq, // from vg93 module - drq + irq read
output wire vg_cs_n,
output wire vg_wrFF,
output reg [1:0] drive_sel, // disk drive selection
// SPI // SPI
output reg sdcs_n, output sdcs_n,
output wire sd_start, output sd_start,
output wire [ 7:0] sd_datain, output [7:0] sd_datain,
input wire [ 7:0] sd_dataout, input [7:0] sd_dataout,
// WAIT-ports related // WAIT-ports related
output reg [ 7:0] gluclock_addr, output reg [7:0] wait_addr,
output reg [ 2:0] comport_addr, output wait_start_gluclock, // begin wait from some ports
output wire wait_start_gluclock, // begin wait from some ports output wait_start_comport, //
output wire wait_start_comport, //
output reg [7:0] wait_write, output reg [7:0] wait_write,
input wire [ 7:0] wait_read, input [7:0] wait_read
//---COM PORT------------------------
input wire [ 7:0] com_data_rx,
input wire [ 7:0] com_status,
//------------------------------
output wire [ 7:0] TST,
input wire lock_conf
); );
assign TST = 7'h00|sd_start; assign sdcs_n = spi_cs_n[0];
localparam FDR_VER = 1'b0;
///////////////////=========RESET ============================ localparam VDAC_VER = 3'h3;
//---SELECT ROM PAGE0---------
localparam DOS_RESET = 1'h1; //DOS-ON
//-----------rampage value after RESET --------------------
localparam CPU_BANK_0_RESET = 8'h00; //not used for mode3
localparam CPU_BANK_1_RESET = 8'h05; //VIDEO PAGE =5
localparam CPU_BANK_2_RESET = 8'h02; //RAM PAGE =2
localparam CPU_BANK_3_RESET = 8'h00; //WR 7FFD
localparam MEMCONF_RESET = 8'h04; // xtpage[0] = xt_page[7:0],
localparam CACHECONF_RESET = 4'h0; // disable
//---SELECT PENTAGON Config--------------
//localparam MEMCONF_RESET = 8'hC0; // MODE3, normal map
//rampage[3] <= (MODE3) {2'b0,7ffd[5],7ffd[7:6], 7ffd[2:0]}; -PENTAGON
//MEMCONF[0] : <=(WR 7FFD)7ffd[4]-ROM128
//MEMCONF[1] :(W0_WE // WR_BANK0) 0-DIS, 1-ENA
//MEMCONF[2] :!W0_MAP - 0 for use MODE3
//MEMCONF[3] : W0_RAM(BANK0) 0-ROM, 1-RAM
//MEMCONF[6:4]:
//MEMCONF[7:6]: LOCK128
// 11 - MODE3 lock128_3 = 8'hC0;
///==============================
localparam PORTFE = 8'hFE; localparam PORTFE = 8'hFE;
localparam PORTFD = 8'hFD; localparam PORTFD = 8'hFD;
localparam PORTXT = 8'hAF; localparam PORTXT = 8'hAF;
localparam PORTF7 = 8'hF7; localparam PORTF7 = 8'hF7;
localparam COVOX = 8'hFB; localparam COVOX = 8'hFB;
localparam NIDE10 = 8'h10;
localparam NIDE11 = 8'h11;
localparam NIDE30 = 8'h30;
localparam NIDE50 = 8'h50;
localparam NIDE70 = 8'h70;
localparam NIDE90 = 8'h90;
localparam NIDEB0 = 8'hB0;
localparam NIDED0 = 8'hD0;
localparam NIDEF0 = 8'hF0;
localparam NIDE08 = 8'h08;
localparam NIDE28 = 8'h28;
localparam NIDE48 = 8'h48;
localparam NIDE68 = 8'h68;
localparam NIDE88 = 8'h88;
localparam NIDEA8 = 8'hA8;
localparam NIDEC8 = 8'hC8;
localparam NIDEE8 = 8'hE8;
localparam VGCOM = 8'h1F; localparam VGCOM = 8'h1F;
localparam VGTRK = 8'h3F; localparam VGTRK = 8'h3F;
localparam VGSEC = 8'h5F; localparam VGSEC = 8'h5F;
@ -181,31 +137,23 @@ module zports
wire [7:0] loa = a[7:0]; wire [7:0] loa = a[7:0];
wire [7:0] hoa=a[15:8]; wire [7:0] hoa = regs_we ? a[7:0] : a[15:8];
assign porthit = assign porthit = ((loa==PORTFE) || (loa==PORTXT) || (loa==PORTFD) || (loa==COVOX))
((loa==PORTFE) || (loa==PORTXT) || (loa==PORTFD) || (loa==COVOX))
|| ((loa==PORTF7) && !dos) || ((loa==PORTF7) && !dos)
// || ide_all || ((vg_port || vgsys_port) && (dos || open_vg))
|| ((vg_port || vgsys_port) && dos) || ((loa==KJOY) && !dos && !open_vg)
|| ((loa==KJOY) && !dos)
|| (loa==KMOUSE) || (loa==KMOUSE)
|| (((loa==SDCFG) || (loa==SDDAT)) && (!dos || vdos)) || (((loa==SDCFG) || (loa==SDDAT)) && (!dos || vdos))
|| (loa==COMPORT); || (loa==COMPORT);
// wire ide_all = ide_even || ide_port11; wire vg_port = (loa==VGCOM) || (loa==VGTRK) || (loa==VGSEC) || (loa==VGDAT);
// wire ide_even = (loa[2:0] == 3'b000) && (loa[3] != loa[4]); // even ports
// wire ide_port11 = (loa==NIDE11); // 11
// wire ide_port10 = (loa==NIDE10); // 10
// wire ide_portc8 = (loa==NIDEC8); // C8
wire vg_port = (loa==VGCOM) | (loa==VGTRK) | (loa==VGSEC) | (loa==VGDAT);
wire vgsys_port = (loa==VGSYS); wire vgsys_port = (loa==VGSYS);
assign external_port = ((loa==PORTFD) & a[15]) // AY assign external_port = ((loa==PORTFD) && a[15]) // AY
|| (((loa==VGCOM) || (loa==VGTRK) || (loa==VGSEC) || (loa==VGDAT)) && dos); || (((loa==VGCOM) || (loa==VGTRK) || (loa==VGSEC) || (loa==VGDAT)) && (dos || open_vg));
assign dataout = porthit & iord & (~external_port); assign dataout = porthit && iord && (~external_port);
reg iowr_reg; reg iowr_reg;
@ -213,48 +161,28 @@ module zports
reg port_wr; reg port_wr;
reg port_rd; reg port_rd;
always @(posedge clk) always @(posedge clk) begin
begin
iowr_reg <= iowr; iowr_reg <= iowr;
port_wr <= (!iowr_reg && iowr);
iord_reg <= iord; iord_reg <= iord;
port_rd <= (!iord_reg && iord);
if (!iowr_reg && iowr)
port_wr <= 1'b1;
else
port_wr <= 1'b0;
if (!iord_reg && iord)
port_rd <= 1'b1;
else
port_rd <= 1'b0;
end end
// wire no_ide = 1'b0; // this should be compiled conditionally
// reading ports // reading ports
always @* always @(*) begin
begin
dout = 8'hFF;
case (loa) case (loa)
PORTFE: PORTFE:
// dout = {1'b1, tape_read, 1'b0, keys_in}; dout = {1'b1, tape_read, 1'b0, keys_in};
dout = {1'b1, tape_read, 1'b1, keys_in}; // MVV 31.10.2014
// NIDE10,NIDE30,NIDE50,NIDE70,NIDE90,NIDEB0,NIDED0,NIDEF0,NIDE08,NIDE28,NIDE48,NIDE68,NIDE88,NIDEA8,NIDEC8,NIDEE8: PORTXT:
// dout = iderdeven;
// NIDE11:
// dout = iderdodd;
PORTXT: //--hAF
begin begin
case (hoa) case (hoa)
XSTAT: XSTAT:
dout = {1'b0, pwr_up_reg, 6'b000011}; // MVV IDE Video DAC Added (<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> $00AF. 2 <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: 0 (1<EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>) <EFBFBD><EFBFBD><EFBFBD> 3 (2<EFBFBD>)) dout = {1'b0, pwr_up_reg, FDR_VER, 2'b0, VDAC_VER};
//--ADDR h27AF
DMASTAT: //-8'h27 DMASTAT:
dout = {dma_act, 7'b0}; dout = {dma_act, 7'b0};
RAMPAGE + 8'd2, RAMPAGE + 8'd3: RAMPAGE + 8'd2, RAMPAGE + 8'd3:
@ -279,23 +207,14 @@ module zports
SDDAT: SDDAT:
dout = sd_dataout; dout = sd_dataout;
PORTF7: PORTF7:
begin begin
if (!a[14] && (a[8] ^ dos) && gluclock_on) // $BFF7 - data i/o if (!a[14] && (a[8] ^ dos) && gluclock_on) dout = wait_read; // $BFF7 - data i/o
dout = wait_read; else dout = 8'hFF; // any other $xxF7 port
// dout = 8'h55;
else // any other $xxF7 port
dout = 8'hFF;
end end
COMPORT: // loa = EF // $F8EF..$FFEF ====== COMPORT:
begin dout = wait_read; // $F8EF..$FFEF
if (hoa[7:0] == 8'hF8) //COM RX DATA
dout = com_data_rx;
if (hoa[7:0] == 8'hFD) //COM STATUS DATA
dout = com_status;
end
default: default:
dout = 8'hFF; dout = 8'hFF;
@ -306,16 +225,14 @@ module zports
// power-up // power-up
// This bit is loaded as 1 while FPGA is configured // This bit is loaded as 1 while FPGA is configured
// and automatically reset to 0 after STATUS port reading // and automatically reset to 0 after STATUS port reading
reg pwr_up_reg; reg pwr_up_reg;
reg pwr_up = 1'b1; reg pwr_up = 1;
always @(posedge clk) always @(posedge clk) begin
if (iord_s & (loa == PORTXT) & (hoa == XSTAT)) if (iord_s & (loa == PORTXT) & (hoa == XSTAT)) begin
begin
pwr_up_reg <= pwr_up; pwr_up_reg <= pwr_up;
pwr_up <= 1'b0; pwr_up <= 1'b0;
end end
end
// writing ports // writing ports
@ -357,61 +274,59 @@ module zports
localparam HSINT = 8'h22; localparam HSINT = 8'h22;
localparam VSINTL = 8'h23; localparam VSINTL = 8'h23;
localparam VSINTH = 8'h24; localparam VSINTH = 8'h24;
localparam IM2VECT = 8'h25; localparam DMAWPD = 8'h25;
localparam INTFRM = 3'b000;
localparam INTLIN = 3'b001;
localparam INTDMA = 3'b010;
localparam DMALEN = 8'h26; localparam DMALEN = 8'h26;
localparam DMACTRL = 8'h27; localparam DMACTRL = 8'h27;
localparam DMANUM = 8'h28; localparam DMANUM = 8'h28;
localparam FDDVIRT = 8'h29; localparam FDDVIRT = 8'h29;
localparam INTMASK = 8'h2A; localparam INTMASK = 8'h2A;
localparam CACHECONF = 8'h2B; localparam CACHECONF = 8'h2B;
localparam DMAWPA = 8'h2D;
localparam XSTAT = 8'h00; localparam XSTAT = 8'h00;
localparam DMASTAT = 8'h27; localparam DMASTAT = 8'h27;
assign dmaport_wr[0] = portxt_wr & (hoa == DMASADDRL); assign dmaport_wr[0] = portxt_wr && (hoa == DMASADDRL);
assign dmaport_wr[1] = portxt_wr & (hoa == DMASADDRH); assign dmaport_wr[1] = portxt_wr && (hoa == DMASADDRH);
assign dmaport_wr[2] = portxt_wr & (hoa == DMASADDRX); assign dmaport_wr[2] = portxt_wr && (hoa == DMASADDRX);
assign dmaport_wr[3] = portxt_wr & (hoa == DMADADDRL); assign dmaport_wr[3] = portxt_wr && (hoa == DMADADDRL);
assign dmaport_wr[4] = portxt_wr & (hoa == DMADADDRH); assign dmaport_wr[4] = portxt_wr && (hoa == DMADADDRH);
assign dmaport_wr[5] = portxt_wr & (hoa == DMADADDRX); assign dmaport_wr[5] = portxt_wr && (hoa == DMADADDRX);
assign dmaport_wr[6] = portxt_wr & (hoa == DMALEN); assign dmaport_wr[6] = portxt_wr && (hoa == DMALEN);
assign dmaport_wr[7] = portxt_wr & (hoa == DMACTRL); assign dmaport_wr[7] = portxt_wr && (hoa == DMACTRL);
assign dmaport_wr[8] = portxt_wr & (hoa == DMANUM); assign dmaport_wr[8] = portxt_wr && (hoa == DMANUM);
assign zborder_wr = portfe_wr; assign zborder_wr = portfe_wr;
assign border_wr = (portxt_wr & (hoa == XBORDER)); assign border_wr = (portxt_wr && (hoa == XBORDER));
assign zvpage_wr = p7ffd_wr; assign zvpage_wr = p7ffd_wr;
assign vpage_wr = (portxt_wr & (hoa == VPAGE )); assign vpage_wr = (portxt_wr && (hoa == VPAGE ));
assign vconf_wr = (portxt_wr & (hoa == VCONF )); assign vconf_wr = (portxt_wr && (hoa == VCONF ));
assign gx_offsl_wr = (portxt_wr & (hoa == GXOFFSL)); assign gx_offsl_wr = (portxt_wr && (hoa == GXOFFSL));
assign gx_offsh_wr = (portxt_wr & (hoa == GXOFFSH)); assign gx_offsh_wr = (portxt_wr && (hoa == GXOFFSH));
assign gy_offsl_wr = (portxt_wr & (hoa == GYOFFSL)); assign gy_offsl_wr = (portxt_wr && (hoa == GYOFFSL));
assign gy_offsh_wr = (portxt_wr & (hoa == GYOFFSH)); assign gy_offsh_wr = (portxt_wr && (hoa == GYOFFSH));
assign t0x_offsl_wr = (portxt_wr & (hoa == T0XOFFSL)); assign t0x_offsl_wr = (portxt_wr && (hoa == T0XOFFSL));
assign t0x_offsh_wr = (portxt_wr & (hoa == T0XOFFSH)); assign t0x_offsh_wr = (portxt_wr && (hoa == T0XOFFSH));
assign t0y_offsl_wr = (portxt_wr & (hoa == T0YOFFSL)); assign t0y_offsl_wr = (portxt_wr && (hoa == T0YOFFSL));
assign t0y_offsh_wr = (portxt_wr & (hoa == T0YOFFSH)); assign t0y_offsh_wr = (portxt_wr && (hoa == T0YOFFSH));
assign t1x_offsl_wr = (portxt_wr & (hoa == T1XOFFSL)); assign t1x_offsl_wr = (portxt_wr && (hoa == T1XOFFSL));
assign t1x_offsh_wr = (portxt_wr & (hoa == T1XOFFSH)); assign t1x_offsh_wr = (portxt_wr && (hoa == T1XOFFSH));
assign t1y_offsl_wr = (portxt_wr & (hoa == T1YOFFSL)); assign t1y_offsl_wr = (portxt_wr && (hoa == T1YOFFSL));
assign t1y_offsh_wr = (portxt_wr & (hoa == T1YOFFSH)); assign t1y_offsh_wr = (portxt_wr && (hoa == T1YOFFSH));
assign tsconf_wr = (portxt_wr & (hoa == TSCONF)); assign tsconf_wr = (portxt_wr && (hoa == TSCONF));
assign palsel_wr = (portxt_wr & (hoa == PALSEL)); assign palsel_wr = (portxt_wr && (hoa == PALSEL));
assign tmpage_wr = (portxt_wr & (hoa == TMPAGE)); assign tmpage_wr = (portxt_wr && (hoa == TMPAGE));
assign t0gpage_wr = (portxt_wr & (hoa == T0GPAGE)); assign t0gpage_wr = (portxt_wr && (hoa == T0GPAGE));
assign t1gpage_wr = (portxt_wr & (hoa == T1GPAGE)); assign t1gpage_wr = (portxt_wr && (hoa == T1GPAGE));
assign sgpage_wr = (portxt_wr & (hoa == SGPAGE)); assign sgpage_wr = (portxt_wr && (hoa == SGPAGE));
assign hint_beg_wr = (portxt_wr & (hoa == HSINT )); assign hint_beg_wr = (portxt_wr && (hoa == HSINT ));
assign vint_begl_wr = (portxt_wr & (hoa == VSINTL)); assign vint_begl_wr = (portxt_wr && (hoa == VSINTL));
assign vint_begh_wr = (portxt_wr & (hoa == VSINTH)); assign vint_begh_wr = (portxt_wr && (hoa == VSINTH));
assign beeper_wr = portfe_wr; assign beeper_wr = portfe_wr;
wire portfe_wr = (loa==PORTFE) && iowr_s; wire portfe_wr = (loa==PORTFE) && iowr_s;
assign covox_wr = (loa==COVOX) && iowr_s; assign covox_wr = (loa==COVOX) && iowr_s;
wire portxt_wr = (loa==PORTXT) && iowr_s; wire portxt_wr = ((loa==PORTXT) && iowr_s) || regs_we;
reg [7:0] rampage[0:3]; reg [7:0] rampage[0:3];
assign xt_page = {rampage[3], rampage[2], rampage[1], rampage[0]}; assign xt_page = {rampage[3], rampage[2], rampage[1], rampage[0]};
@ -421,175 +336,130 @@ module zports
wire lock128_3 = memconf[7:6] == 2'b11; // mode 3 wire lock128_3 = memconf[7:6] == 2'b11; // mode 3
reg m1_lock128; reg m1_lock128;
always @(posedge clk) always @(posedge clk) if (opfetch) m1_lock128 <= !(din[7] ^ din[6]);
if (opfetch)
m1_lock128 <= !(din[7] ^ din[6]);
always @(posedge clk) begin
always @(posedge clk) if (rst) begin
if (rst)
begin
fmaddr[4] <= 1'b0; fmaddr[4] <= 1'b0;
//im2v_frm <= 3'b111;
intmask <= 8'b1; intmask <= 8'b1;
//fddvirt <= 4'b0; fddvirt <= 8'b0;
fddvirt <= 4'b0001; // VIRTUAL DOS A driver virtual sysconf <= 8'h00; // 3.5 MHz
sysconf <= 8'h01; // turbo 7 MHz memconf <= 8'h04; // no map
//------- cacheconf <= 4'h0; // no cache
memconf <= MEMCONF_RESET; // mode=3, normal map
cacheconf <= CACHECONF_RESET; // no cache rampage[0]<= 8'h00;
//--------------------------------------------- rampage[1]<= 8'h05;
rampage[0] <= CPU_BANK_0_RESET; //8'h00; rampage[2]<= 8'h02;
rampage[1] <= CPU_BANK_1_RESET; //8'h05; rampage[3]<= 8'h00;
rampage[2] <= CPU_BANK_2_RESET; //8'h02;
rampage[3] <= CPU_BANK_3_RESET; //8'h00;
end end
else if (p7ffd_wr) begin
else memconf[0] <= din[4];
if (p7ffd_wr)
begin
memconf[0] <= din[4]; //<= din[4] = ROM128
rampage[3] <= {2'b0, lock128_3 ? {din[5], din[7:6]} : ({1'b0, lock128 ? 2'b0 : din[7:6]}), din[2:0]}; rampage[3] <= {2'b0, lock128_3 ? {din[5], din[7:6]} : ({1'b0, lock128 ? 2'b0 : din[7:6]}), din[2:0]};
end //lock128_3 = memconf[7:6] == 2'b11; // mode 3 end
else if (portxt_wr) begin
if (hoa[7:2] == RAMPAGE[7:2]) rampage[hoa[1:0]] <= din;
else if (hoa == FMADDR) fmaddr <= din[4:0];
if (portxt_wr)
begin if (hoa == SYSCONF) begin
if (hoa[7:2] == RAMPAGE[7:2])
rampage[hoa[1:0]] <= din;
if (hoa == FMADDR)
fmaddr <= din[4:0];
if (hoa == SYSCONF)
begin
sysconf <= din; sysconf <= din;
cacheconf <= {4{din[2]}}; cacheconf <= {4{din[2]}};
end end
if (hoa == CACHECONF)
cacheconf <= din[3:0];
if (hoa == MEMCONF) // & !lock_conf
memconf <= din;
//================================
//if (hoa == IM2VECT)
//begin
// if (din[6:4] == INTFRM)
// im2v_frm <= din[3:1];
// if (din[6:4] == INTLIN)
// im2v_lin <= din[3:1];
// if (din[6:4] == INTDMA)
// im2v_dma <= din[3:1];
//end
//================================
if (hoa == FDDVIRT)
fddvirt <= din[3:0];
if (hoa == INTMASK)
intmask <= din;
end
if (hoa == DMAWPD) dmawpdev <= din[1:0];
if (hoa == CACHECONF) cacheconf <= din[3:0];
if (hoa == MEMCONF) memconf <= din;
if (hoa == FDDVIRT) fddvirt <= din;
if (hoa == INTMASK) intmask <= din;
end
end
// 7FFD port // 7FFD port
wire p7ffd_wr = !a[15] && (loa==PORTFD) && iowr_s && !lock48; wire p7ffd_wr = !a[15] && (loa==PORTFD) && iowr_s && !lock48;
reg lock48; reg lock48;
always @(posedge clk) always @(posedge clk) begin
if (rst) if (rst) lock48 <= 1'b0;
lock48 <= 1'b0; else if (p7ffd_wr && !lock128_3) lock48 <= din[5];
else if (p7ffd_wr && !lock128_3) end
lock48 <= din[5];
// AY control // AY control
wire ay_hit = (loa==PORTFD) & a[15]; wire ay_hit = (loa==PORTFD) & a[15];
assign ay_bc1 = ay_hit & a[14] & iorw; assign ay_bc1 = ay_hit & a[14] & iordwr;
assign ay_bdir = ay_hit & iowr; assign ay_bdir = ay_hit & iowr;
//===========================================
// VG93 // VG93
wire virt_vg = fddvirt[drive_sel]; wire [3:0] fddvrt = fddvirt[3:0];
wire virt_vg = fddvrt[drive_sel_raw];
wire open_vg = fddvirt[7];
assign drive_sel = {drive_sel_raw[1], drive_sel_raw[0]};
assign vg_cs_n = !(iorw && vg_port && dos && !vdos && !virt_vg); wire vg_wen = (dos || open_vg) && !vdos && !virt_vg;
assign vg_wrFF = wr && iorq_s && vgsys_port && dos && !vdos && !virt_vg; assign vg_cs_n = !(iordwr && vg_port && vg_wen);
assign vg_wrFF = iowr_s && vgsys_port && vg_wen;
wire vg_wrDS = iowr_s && vgsys_port && (dos || open_vg);
assign vdos_on = rdwr && iorq_s && (vg_port || vgsys_port) && dos && !vdos && virt_vg; assign vdos_on = iordwr_s && (vg_port || vgsys_port) && dos && !vdos && virt_vg;
assign vdos_off = rdwr && iorq_s && vg_port && vdos; assign vdos_off = iordwr_s && vg_port && vdos;
// write drive number // write drive number
always @(posedge clk) reg [1:0] drive_sel_raw;
if (iowr_s && vgsys_port && dos) always @(posedge clk) if (vg_wrDS) drive_sel_raw <= din[1:0];
drive_sel <= din[1:0];
// SD card (Z-controller compatible)
// SD card (Z-control?r compatible)
wire sdcfg_wr; wire sdcfg_wr;
wire sddat_wr; wire sddat_wr;
wire sddat_rd; wire sddat_rd;
// if loader =1 should be ENABLE reg [1:0] spi_cs_n;
assign sdcfg_wr = ((loa==SDCFG) && iowr_s && ((!dos || vdos)) || loader);
assign sddat_wr = ((loa==SDDAT) && iowr_s && ((!dos || vdos)) || loader); assign sdcfg_wr = ((loa==SDCFG) && iowr_s && (!dos || vdos));
assign sddat_wr = ((loa==SDDAT) && iowr_s && (!dos || vdos));
assign sddat_rd = ((loa==SDDAT) && iord_s); assign sddat_rd = ((loa==SDDAT) && iord_s);
// SDCFG write - sdcs_n control // SDCFG write - sdcs_n control
always @(posedge clk) always @(posedge clk) begin
if (rst) if (rst) spi_cs_n <= 2'b11;
sdcs_n <= 1'b1; else if (sdcfg_wr) spi_cs_n <= {~din[2], din[1]};
else if (sdcfg_wr) end
sdcs_n <= din[1];
// start signal for SPI module with resyncing to fclk // start signal for SPI module with resyncing to fclk
assign sd_start = sddat_wr || sddat_rd; assign sd_start = sddat_wr || sddat_rd;
// data for SPI module // data for SPI module
assign sd_datain = wr ? din : 8'hFF; assign sd_datain = wr ? din : 8'hFF;
// xxF7 // xxF7
wire portf7_wr = ((loa==PORTF7) && (a[8]==1'b1) && port_wr && (!dos || vdos)); wire portf7_wr = ((loa==PORTF7) && (a[8]==1'b1) && port_wr && (!dos || vdos));
wire portf7_rd = ((loa==PORTF7) && (a[8]==1'b1) && port_rd && (!dos || vdos)); wire portf7_rd = ((loa==PORTF7) && (a[8]==1'b1) && port_rd && (!dos || vdos));
// EFF7 port // EFF7 port
reg [7:0] peff7; reg [7:0] peff7;
always @(posedge clk) always @(posedge clk) begin
if (rst) if (rst) peff7 <= 8'h00;
peff7 <= 8'h00; else if (!a[12] && portf7_wr && !dos) peff7 <= din; // #EEF7 in dos is not accessible
else if (!a[12] && portf7_wr && !dos) // #EEF7 in dos is not accessible end
peff7 <= din;
// gluclock ports // gluclock ports
wire gluclock_on = peff7[7] || dos; // in dos mode EEF7 is not accessible, gluclock access is ON in dos mode. wire gluclock_on = peff7[7] || dos; // in dos mode EEF7 is not accessible, gluclock access is ON in dos mode.
always @(posedge clk) begin
if (gluclock_on && portf7_wr) // gluclocks on
if( !a[13] ) // $DFF7 - addr reg
gluclock_addr <= din;
end
// write to wait registers
always @(posedge clk) begin
// gluclocks
if (gluclock_on && portf7_wr && !a[14]) // $BFF7 - data reg
wait_write <= din;
// com ports
else if (comport_wr) // $F8EF..$FFEF - comports
wait_write <= din;
end
// comports // comports
wire comport_wr = ((loa == COMPORT) && port_wr); wire comport_wr = ((loa == COMPORT) && port_wr);
wire comport_rd = ((loa == COMPORT) && port_rd); wire comport_rd = ((loa == COMPORT) && port_rd);
// write to wait registers
always @(posedge clk) begin always @(posedge clk) begin
if (comport_wr || comport_rd) // gluclocks
comport_addr <= a[10:8]; if (gluclock_on && portf7_wr) begin
if (!a[14]) wait_write <= din; // $BFF7 - data reg
if (!a[13]) wait_addr <= din; // $DFF7 - addr reg
end end
// com ports
if (comport_wr) wait_write <= din; // $xxEF
if (comport_wr || comport_rd) wait_addr <= a[15:8];
if ((loa==PORTXT) && (hoa == DMAWPA)) wait_addr <= din;
end
// wait from wait registers // wait from wait registers
// ACHTUNG!!!! here portxx_wr are ON Z80 CLOCK! logic must change when moving to clk strobes // ACHTUNG!!!! here portxx_wr are ON Z80 CLOCK! logic must change when moving to clk strobes

38
src/tsconf.v
View File

@ -160,8 +160,6 @@ wire dram_req;
wire dram_rnw; wire dram_rnw;
wire dos; wire dos;
wire [7:0] gluclock_addr;
wire vdos; wire vdos;
wire pre_vdos; wire pre_vdos;
wire vdos_off; wire vdos_off;
@ -186,6 +184,7 @@ wire iowr_s;
wire iorw_s; wire iorw_s;
wire memwr_s; wire memwr_s;
wire opfetch_s; wire opfetch_s;
wire regs_we;
// zports OUT // zports OUT
wire [7:0] dout_ports; wire [7:0] dout_ports;
@ -382,7 +381,6 @@ zports TS05
.dataout(ena_ports), .dataout(ena_ports),
.a(cpu_a_bus), .a(cpu_a_bus),
.rst(reset), .rst(reset),
.loader(0), //loader, -- for load ROM, SPI should be enable
.opfetch(opfetch), // from zsignals .opfetch(opfetch), // from zsignals
.rd(rd), .rd(rd),
.wr(wr), .wr(wr),
@ -393,9 +391,8 @@ zports TS05
.iord_s(iord_s), .iord_s(iord_s),
.iowr(iowr), .iowr(iowr),
.iowr_s(iowr_s), .iowr_s(iowr_s),
.iorw(iorw), .iordwr(iorw),
.iorw_s(iorw_s), .iordwr_s(iorw_s),
.external_port(), // asserts for AY and VG93 accesses
.zborder_wr(zborder_wr), .zborder_wr(zborder_wr),
.border_wr(border_wr), .border_wr(border_wr),
.zvpage_wr(zvpage_wr), .zvpage_wr(zvpage_wr),
@ -424,6 +421,7 @@ zports TS05
.vint_begh_wr(vint_begh_wr), .vint_begh_wr(vint_begh_wr),
.xt_page(xt_page), .xt_page(xt_page),
.fmaddr(fmaddr), .fmaddr(fmaddr),
.regs_we(regs_we),
.sysconf(sysconf), .sysconf(sysconf),
.memconf(memconf), .memconf(memconf),
.cacheconf(cacheconf), .cacheconf(cacheconf),
@ -434,7 +432,6 @@ zports TS05
.vdos(vdos), .vdos(vdos),
.vdos_on(vdos_on), .vdos_on(vdos_on),
.vdos_off(vdos_off), .vdos_off(vdos_off),
.rstrom(2'b11),
.tape_read(1), .tape_read(1),
.keys_in(kb_do_bus), // keys (port FE) .keys_in(kb_do_bus), // keys (port FE)
.mus_in(mouse_do), // mouse (xxDF) .mus_in(mouse_do), // mouse (xxDF)
@ -445,12 +442,9 @@ zports TS05
.sd_start(cpu_spi_req), // to SPI .sd_start(cpu_spi_req), // to SPI
.sd_datain(cpu_spi_din), // to SPI(7 downto 0); .sd_datain(cpu_spi_din), // to SPI(7 downto 0);
.sd_dataout(spi_dout), // from SPI(7 downto 0); .sd_dataout(spi_dout), // from SPI(7 downto 0);
.gluclock_addr(gluclock_addr), .wait_addr(wait_addr),
.wait_read(mc146818a_do_bus), .wait_start_gluclock(wait_start_gluclock),
.com_data_rx(8'b00000000), //uart_do_bus, .wait_read(mc146818a_do_bus)
.com_status(8'b10010000), //'1' & uart_tx_empty & uart_tx_fifo_empty & "1000" & uart_rx_avail,
//com_status=> '0' & uart_tx_empty & uart_tx_fifo_empty & "0000" & '1',
.lock_conf(1)
); );
zmem TS06 zmem TS06
@ -646,7 +640,8 @@ zmaps TS10
.dma_cram_we(dma_cram_we), .dma_cram_we(dma_cram_we),
.dma_sfile_we(dma_sfile_we), .dma_sfile_we(dma_sfile_we),
.cram_we(cram_we), .cram_we(cram_we),
.sfile_we(sfile_we) .sfile_we(sfile_we),
.regs_we(regs_we)
); );
spi TS11 spi TS11
@ -745,9 +740,9 @@ kempston_mouse KM
); );
// MC146818A,RTC // MC146818A,RTC
wire mc146818a_wr = port_bff7 && ~cpu_wr_n; wire [7:0] wait_addr;
wire wait_start_gluclock;
wire [7:0] mc146818a_do_bus; wire [7:0] mc146818a_do_bus;
wire port_bff7 = ~cpu_iorq_n && cpu_a_bus == 16'hBFF7 && cpu_m1_n && port_eff7_reg[7];
reg ena_0_4375mhz; reg ena_0_4375mhz;
always @(negedge clk_28mhz) begin always @(negedge clk_28mhz) begin
@ -756,12 +751,6 @@ always @(negedge clk_28mhz) begin
ena_0_4375mhz <= !div; //28MHz/64 ena_0_4375mhz <= !div; //28MHz/64
end end
reg [7:0] port_eff7_reg;
always @(posedge clk_28mhz) begin
if (reset) port_eff7_reg <= 0;
else if (~cpu_iorq_n && ~cpu_wr_n && cpu_a_bus == 16'hEFF7) port_eff7_reg <= cpu_do_bus; //for RTC
end
mc146818a SE9 mc146818a SE9
( (
.RESET(reset), .RESET(reset),
@ -771,8 +760,8 @@ mc146818a SE9
.KEYSCANCODE(key_scancode), .KEYSCANCODE(key_scancode),
.RTC(RTC), .RTC(RTC),
.CMOSCfg(CMOSCfg), .CMOSCfg(CMOSCfg),
.WR(mc146818a_wr), .WR(wait_start_gluclock & ~cpu_wr_n),
.A(gluclock_addr[7:0]), .A(wait_addr),
.DI(cpu_do_bus), .DI(cpu_do_bus),
.DO(mc146818a_do_bus) .DO(mc146818a_do_bus)
); );
@ -912,7 +901,6 @@ assign cpu_di_bus =
(csrom && ~cpu_mreq_n && ~cpu_rd_n) ? bios_do_bus : // BIOS (csrom && ~cpu_mreq_n && ~cpu_rd_n) ? bios_do_bus : // BIOS
(~cpu_mreq_n && ~cpu_rd_n) ? sdr_do_bus : // SDRAM (~cpu_mreq_n && ~cpu_rd_n) ? sdr_do_bus : // SDRAM
(intack) ? im2vect : (intack) ? im2vect :
(port_bff7 && port_eff7_reg[7] && ~cpu_iorq_n && ~cpu_rd_n) ? mc146818a_do_bus : // MC146818A
(gs_sel && ~cpu_rd_n) ? gs_do_bus : // General Sound (gs_sel && ~cpu_rd_n) ? gs_do_bus : // General Sound
(ts_enable && ~cpu_rd_n) ? ts_do : // TurboSound (ts_enable && ~cpu_rd_n) ? ts_do : // TurboSound
(cpu_a_bus == 16'h0001 && ~cpu_iorq_n && ~cpu_rd_n) ? key_scancode : (cpu_a_bus == 16'h0001 && ~cpu_iorq_n && ~cpu_rd_n) ? key_scancode :