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https://github.com/UzixLS/TSConf_MiST.git
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Update zmaps and zports.
This commit is contained in:
sorgelig
@ -1,59 +1,56 @@
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// This module makes mapping z80 memory accesses into FPGA EABs
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// This module maps z80 memory accesses into FPGA RAM and ports
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module zmaps(
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// Z80 controls
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module zmaps
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(
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// Z80 controls
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input wire clk,
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input wire memwr_s,
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input wire [15:0] a,
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input wire [7:0] d,
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// config data
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// config data
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input wire [4:0] fmaddr,
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// FPRAM data
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// FPRAM data
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output wire [15:0] zmd,
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output wire [7:0] zma,
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// DMA
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// DMA
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input wire [15:0] dma_data,
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input wire [7:0] dma_wraddr,
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input wire dma_cram_we,
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input wire dma_sfile_we,
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input wire dma_cram_we,
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input wire dma_sfile_we,
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// FPRAM controls
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// write strobes
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output wire cram_we,
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output wire sfile_we
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output wire sfile_we,
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output wire regs_we
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);
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// addresses of files withing zmaps
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localparam CRAM = 3'b000;
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localparam SFYS = 3'b001;
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localparam CRAM = 3'b000;
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localparam SFYS = 3'b001;
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localparam REGS = 4'b0100;
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// control signals
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wire hit = (a[15:12] == fmaddr[3:0]) && fmaddr[4] && memwr_s;
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wire hit = (a[15:12] == fmaddr[3:0]) && fmaddr[4] && memwr_s;
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// write enables
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assign cram_we = dma_req ? dma_cram_we : (a[11:9] == CRAM) && a[0] && hit;
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assign sfile_we = dma_req ? dma_sfile_we : (a[11:9] == SFYS) && a[0] && hit;
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assign cram_we = dma_req ? dma_cram_we : (a[11:9] == CRAM) && a[0] && hit;
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assign sfile_we = dma_req ? dma_sfile_we : (a[11:9] == SFYS) && a[0] && hit;
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assign regs_we = (a[11:8] == REGS) && hit;
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// LSB fetching
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assign zma = dma_req ? dma_wraddr : a[8:1];
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assign zmd = dma_req ? dma_data : {d, zmd0}; // for a[0] = 1
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assign zma = dma_req ? dma_wraddr : a[8:1];
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assign zmd = dma_req ? dma_data : {d, zmd0};
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reg [7:0] zmd0;
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always @(posedge clk)
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if (!a[0] && hit)
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zmd0 <= d; // a[0] = 0
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reg [7:0] zmd0;
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always @(posedge clk) if (!a[0] && hit) zmd0 <= d;
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// DMA
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wire dma_req = dma_cram_we || dma_sfile_we;
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wire dma_req = dma_cram_we || dma_sfile_we;
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endmodule
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838
src/cpu/zports.v
838
src/cpu/zports.v
@ -3,268 +3,196 @@
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module zports
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(
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input wire clk,
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input clk,
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input wire [ 7:0] din,
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output reg [ 7:0] dout,
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output wire dataout,
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input wire [15:0] a,
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input [7:0] din,
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output reg [7:0] dout,
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output dataout,
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input [15:0] a,
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input wire rst, // system reset
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input wire loader, //
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input wire opfetch,
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input rst, // system reset
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input opfetch,
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input wire rd,
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input wire wr,
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input wire rdwr,
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input rd,
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input wr,
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input rdwr,
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input wire iorq,
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input wire iorq_s,
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input wire iord,
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input wire iord_s,
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input wire iowr,
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input wire iowr_s,
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input wire iorw,
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input wire iorw_s,
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input iorq,
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input iorq_s,
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input iord,
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input iord_s,
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input iowr,
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input iowr_s,
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input iordwr,
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input iordwr_s,
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output wire porthit, // when internal port hit occurs, this is 1, else 0; used for iorq1_n iorq2_n on zxbus
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output wire external_port, // asserts for AY and VG93 accesses
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output porthit, // when internal port hit occurs, this is 1, else 0; used for iorq1_n iorq2_n on zxbus
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output external_port, // asserts for AY and VG93 accesses
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output wire zborder_wr,
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output wire border_wr,
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output wire zvpage_wr,
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output wire vpage_wr,
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output wire vconf_wr,
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output wire gx_offsl_wr,
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output wire gx_offsh_wr,
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output wire gy_offsl_wr,
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output wire gy_offsh_wr,
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output wire t0x_offsl_wr,
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output wire t0x_offsh_wr,
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output wire t0y_offsl_wr,
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output wire t0y_offsh_wr,
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output wire t1x_offsl_wr,
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output wire t1x_offsh_wr,
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output wire t1y_offsl_wr,
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output wire t1y_offsh_wr,
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output wire tsconf_wr,
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output wire palsel_wr,
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output wire tmpage_wr,
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output wire t0gpage_wr,
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output wire t1gpage_wr,
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output wire sgpage_wr,
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output wire hint_beg_wr,
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output wire vint_begl_wr,
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output wire vint_begh_wr,
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output zborder_wr,
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output border_wr,
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output zvpage_wr,
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output vpage_wr,
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output vconf_wr,
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output gx_offsl_wr,
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output gx_offsh_wr,
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output gy_offsl_wr,
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output gy_offsh_wr,
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output t0x_offsl_wr,
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output t0x_offsh_wr,
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output t0y_offsl_wr,
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output t0y_offsh_wr,
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output t1x_offsl_wr,
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output t1x_offsh_wr,
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output t1y_offsl_wr,
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output t1y_offsh_wr,
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output tsconf_wr,
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output palsel_wr,
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output tmpage_wr,
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output t0gpage_wr,
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output t1gpage_wr,
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output sgpage_wr,
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output hint_beg_wr ,
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output vint_begl_wr,
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output vint_begh_wr,
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output wire [31:0] xt_page,
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output [31:0] xt_page,
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output reg [4:0] fmaddr,
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//----Conf-----------------
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output reg [7:0] sysconf,
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output reg [7:0] memconf,
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output reg [3:0] cacheconf,
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//-------------------------
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output reg [3:0] fddvirt,
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output reg [4:0] fmaddr,
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input regs_we,
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output reg [7:0] intmask,
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output reg [7:0] sysconf,
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output reg [7:0] memconf,
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output reg [3:0] cacheconf,
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output reg [7:0] fddvirt,
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output wire [8:0] dmaport_wr,
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input wire dma_act,
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output [8:0] dmaport_wr,
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input dma_act,
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output reg [1:0] dmawpdev,
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input wire dos,
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input wire vdos,
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output wire vdos_on,
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output wire vdos_off,
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output wire ay_bdir,
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output wire ay_bc1,
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output wire covox_wr,
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output wire beeper_wr,
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output reg [7:0] intmask,
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input wire [ 1:0] rstrom,
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input wire tape_read,
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input dos,
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input vdos,
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output vdos_on,
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output vdos_off,
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input wire [ 4:0] keys_in, // keys (port FE)
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input wire [ 7:0] mus_in, // mouse (xxDF)
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input wire [ 5:0] kj_in,
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output ay_bdir,
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output ay_bc1,
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output covox_wr,
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output beeper_wr,
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input wire vg_intrq,
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input wire vg_drq, // from vg93 module - drq + irq read
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output wire vg_cs_n,
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output wire vg_wrFF,
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output reg [1:0] drive_sel, // disk drive selection
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input tape_read,
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input [4:0] keys_in, // keys (port FE)
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input [7:0] mus_in, // mouse (xxDF)
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input [5:0] kj_in,
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input vg_intrq,
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input vg_drq, // from vg93 module - drq + irq read
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output vg_cs_n,
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output vg_wrFF,
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output [1:0] drive_sel, // disk drive selection
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// SPI
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output reg sdcs_n,
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output wire sd_start,
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output wire [ 7:0] sd_datain,
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input wire [ 7:0] sd_dataout,
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output sdcs_n,
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output sd_start,
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output [7:0] sd_datain,
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input [7:0] sd_dataout,
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// WAIT-ports related
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output reg [ 7:0] gluclock_addr,
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output reg [ 2:0] comport_addr,
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output wire wait_start_gluclock, // begin wait from some ports
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output wire wait_start_comport, //
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output reg [ 7:0] wait_write,
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input wire [ 7:0] wait_read,
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//---COM PORT------------------------
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input wire [ 7:0] com_data_rx,
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input wire [ 7:0] com_status,
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//------------------------------
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output wire [ 7:0] TST,
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input wire lock_conf
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output reg [7:0] wait_addr,
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output wait_start_gluclock, // begin wait from some ports
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output wait_start_comport, //
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output reg [7:0] wait_write,
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input [7:0] wait_read
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);
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assign TST = 7'h00|sd_start;
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assign sdcs_n = spi_cs_n[0];
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localparam FDR_VER = 1'b0;
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localparam VDAC_VER = 3'h3;
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localparam PORTFE = 8'hFE;
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localparam PORTFD = 8'hFD;
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localparam PORTXT = 8'hAF;
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localparam PORTF7 = 8'hF7;
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localparam COVOX = 8'hFB;
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localparam VGCOM = 8'h1F;
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localparam VGTRK = 8'h3F;
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localparam VGSEC = 8'h5F;
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localparam VGDAT = 8'h7F;
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localparam VGSYS = 8'hFF;
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localparam KJOY = 8'h1F;
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localparam KMOUSE = 8'hDF;
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localparam SDCFG = 8'h77;
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localparam SDDAT = 8'h57;
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localparam COMPORT = 8'hEF; // F8EF..FFEF - rs232 ports
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///////////////////=========RESET ============================
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//---SELECT ROM PAGE0---------
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localparam DOS_RESET = 1'h1; //DOS-ON
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//-----------rampage value after RESET --------------------
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localparam CPU_BANK_0_RESET = 8'h00; //not used for mode3
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localparam CPU_BANK_1_RESET = 8'h05; //VIDEO PAGE =5
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localparam CPU_BANK_2_RESET = 8'h02; //RAM PAGE =2
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localparam CPU_BANK_3_RESET = 8'h00; //WR 7FFD
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localparam MEMCONF_RESET = 8'h04; // xtpage[0] = xt_page[7:0],
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localparam CACHECONF_RESET = 4'h0; // disable
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//---SELECT PENTAGON Config--------------
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//localparam MEMCONF_RESET = 8'hC0; // MODE3, normal map
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//rampage[3] <= (MODE3) {2'b0,7ffd[5],7ffd[7:6], 7ffd[2:0]}; -PENTAGON
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//MEMCONF[0] : <=(WR 7FFD)7ffd[4]-ROM128
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//MEMCONF[1] :(W0_WE // WR_BANK0) 0-DIS, 1-ENA
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//MEMCONF[2] :!W0_MAP - 0 for use MODE3
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//MEMCONF[3] : W0_RAM(BANK0) 0-ROM, 1-RAM
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//MEMCONF[6:4]:
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//MEMCONF[7:6]: LOCK128
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// 11 - MODE3 lock128_3 = 8'hC0;
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///==============================
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localparam PORTFE = 8'hFE;
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localparam PORTFD = 8'hFD;
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localparam PORTXT = 8'hAF;
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localparam PORTF7 = 8'hF7;
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localparam COVOX = 8'hFB;
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localparam NIDE10 = 8'h10;
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localparam NIDE11 = 8'h11;
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localparam NIDE30 = 8'h30;
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localparam NIDE50 = 8'h50;
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localparam NIDE70 = 8'h70;
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localparam NIDE90 = 8'h90;
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localparam NIDEB0 = 8'hB0;
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localparam NIDED0 = 8'hD0;
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localparam NIDEF0 = 8'hF0;
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localparam NIDE08 = 8'h08;
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localparam NIDE28 = 8'h28;
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localparam NIDE48 = 8'h48;
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localparam NIDE68 = 8'h68;
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localparam NIDE88 = 8'h88;
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localparam NIDEA8 = 8'hA8;
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localparam NIDEC8 = 8'hC8;
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localparam NIDEE8 = 8'hE8;
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wire [7:0] loa = a[7:0];
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wire [7:0] hoa = regs_we ? a[7:0] : a[15:8];
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localparam VGCOM = 8'h1F;
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localparam VGTRK = 8'h3F;
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localparam VGSEC = 8'h5F;
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localparam VGDAT = 8'h7F;
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localparam VGSYS = 8'hFF;
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assign porthit = ((loa==PORTFE) || (loa==PORTXT) || (loa==PORTFD) || (loa==COVOX))
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|| ((loa==PORTF7) && !dos)
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|| ((vg_port || vgsys_port) && (dos || open_vg))
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|| ((loa==KJOY) && !dos && !open_vg)
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|| (loa==KMOUSE)
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|| (((loa==SDCFG) || (loa==SDDAT)) && (!dos || vdos))
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|| (loa==COMPORT);
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localparam KJOY = 8'h1F;
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localparam KMOUSE = 8'hDF;
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wire vg_port = (loa==VGCOM) || (loa==VGTRK) || (loa==VGSEC) || (loa==VGDAT);
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wire vgsys_port = (loa==VGSYS);
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localparam SDCFG = 8'h77;
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localparam SDDAT = 8'h57;
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assign external_port = ((loa==PORTFD) && a[15]) // AY
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|| (((loa==VGCOM) || (loa==VGTRK) || (loa==VGSEC) || (loa==VGDAT)) && (dos || open_vg));
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localparam COMPORT = 8'hEF; // F8EF..FFEF - rs232 ports
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assign dataout = porthit && iord && (~external_port);
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wire [7:0] loa=a[7:0];
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wire [7:0] hoa=a[15:8];
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reg iowr_reg;
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reg iord_reg;
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reg port_wr;
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reg port_rd;
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assign porthit =
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((loa==PORTFE) || (loa==PORTXT) || (loa==PORTFD) || (loa==COVOX))
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|| ((loa==PORTF7) && !dos)
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// || ide_all
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|| ((vg_port || vgsys_port) && dos)
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|| ((loa==KJOY) && !dos)
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|| (loa==KMOUSE)
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|| (((loa==SDCFG) || (loa==SDDAT)) && (!dos || vdos))
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|| (loa==COMPORT);
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// wire ide_all = ide_even || ide_port11;
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// wire ide_even = (loa[2:0] == 3'b000) && (loa[3] != loa[4]); // even ports
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// wire ide_port11 = (loa==NIDE11); // 11
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// wire ide_port10 = (loa==NIDE10); // 10
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// wire ide_portc8 = (loa==NIDEC8); // C8
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wire vg_port = (loa==VGCOM) | (loa==VGTRK) | (loa==VGSEC) | (loa==VGDAT);
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wire vgsys_port = (loa==VGSYS);
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assign external_port = ((loa==PORTFD) & a[15]) // AY
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|| (((loa==VGCOM) || (loa==VGTRK) || (loa==VGSEC) || (loa==VGDAT)) && dos);
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assign dataout = porthit & iord & (~external_port);
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reg iowr_reg;
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reg iord_reg;
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reg port_wr;
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reg port_rd;
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always @(posedge clk)
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begin
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iowr_reg <= iowr;
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iord_reg <= iord;
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if (!iowr_reg && iowr)
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port_wr <= 1'b1;
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else
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port_wr <= 1'b0;
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if (!iord_reg && iord)
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port_rd <= 1'b1;
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else
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port_rd <= 1'b0;
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end
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// wire no_ide = 1'b0; // this should be compiled conditionally
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always @(posedge clk) begin
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iowr_reg <= iowr;
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port_wr <= (!iowr_reg && iowr);
|
||||
|
||||
iord_reg <= iord;
|
||||
port_rd <= (!iord_reg && iord);
|
||||
end
|
||||
|
||||
|
||||
// reading ports
|
||||
always @*
|
||||
begin
|
||||
dout = 8'hFF;
|
||||
case (loa)
|
||||
always @(*) begin
|
||||
case (loa)
|
||||
PORTFE:
|
||||
// dout = {1'b1, tape_read, 1'b0, keys_in};
|
||||
dout = {1'b1, tape_read, 1'b1, keys_in}; // MVV 31.10.2014
|
||||
dout = {1'b1, tape_read, 1'b0, keys_in};
|
||||
|
||||
// NIDE10,NIDE30,NIDE50,NIDE70,NIDE90,NIDEB0,NIDED0,NIDEF0,NIDE08,NIDE28,NIDE48,NIDE68,NIDE88,NIDEA8,NIDEC8,NIDEE8:
|
||||
// dout = iderdeven;
|
||||
// NIDE11:
|
||||
// dout = iderdodd;
|
||||
PORTXT:
|
||||
begin
|
||||
case (hoa)
|
||||
XSTAT:
|
||||
dout = {1'b0, pwr_up_reg, FDR_VER, 2'b0, VDAC_VER};
|
||||
|
||||
PORTXT: //--hAF
|
||||
begin
|
||||
case (hoa)
|
||||
DMASTAT:
|
||||
dout = {dma_act, 7'b0};
|
||||
|
||||
XSTAT:
|
||||
dout = {1'b0, pwr_up_reg, 6'b000011}; // MVV IDE Video DAC Added (<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> $00AF. 2 <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: 0 (1<EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>) <EFBFBD><EFBFBD><EFBFBD> 3 (2<EFBFBD>))
|
||||
//--ADDR h27AF
|
||||
DMASTAT: //-8'h27
|
||||
dout = {dma_act, 7'b0};
|
||||
RAMPAGE + 8'd2, RAMPAGE + 8'd3:
|
||||
dout = rampage[hoa[1:0]];
|
||||
|
||||
RAMPAGE+8'd2, RAMPAGE+8'd3:
|
||||
dout = rampage[hoa[1:0]];
|
||||
default:
|
||||
dout = 8'hFF;
|
||||
|
||||
default:
|
||||
dout = 8'hFF;
|
||||
|
||||
endcase
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
VGSYS:
|
||||
dout = {vg_intrq, vg_drq, 6'b111111};
|
||||
@ -279,321 +207,263 @@ module zports
|
||||
SDDAT:
|
||||
dout = sd_dataout;
|
||||
|
||||
|
||||
PORTF7:
|
||||
begin
|
||||
if (!a[14] && (a[8] ^ dos) && gluclock_on) // $BFF7 - data i/o
|
||||
dout = wait_read;
|
||||
// dout = 8'h55;
|
||||
else // any other $xxF7 port
|
||||
dout = 8'hFF;
|
||||
end
|
||||
begin
|
||||
if (!a[14] && (a[8] ^ dos) && gluclock_on) dout = wait_read; // $BFF7 - data i/o
|
||||
else dout = 8'hFF; // any other $xxF7 port
|
||||
end
|
||||
|
||||
COMPORT: // loa = EF // $F8EF..$FFEF ======
|
||||
begin
|
||||
if (hoa[7:0] == 8'hF8) //COM RX DATA
|
||||
dout = com_data_rx;
|
||||
if (hoa[7:0] == 8'hFD) //COM STATUS DATA
|
||||
dout = com_status;
|
||||
end
|
||||
COMPORT:
|
||||
dout = wait_read; // $F8EF..$FFEF
|
||||
|
||||
default:
|
||||
dout = 8'hFF;
|
||||
endcase
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
// power-up
|
||||
// This bit is loaded as 1 while FPGA is configured
|
||||
// and automatically reset to 0 after STATUS port reading
|
||||
|
||||
reg pwr_up_reg;
|
||||
reg pwr_up = 1'b1;
|
||||
always @(posedge clk)
|
||||
if (iord_s & (loa == PORTXT) & (hoa == XSTAT))
|
||||
begin
|
||||
pwr_up_reg <= pwr_up;
|
||||
pwr_up <= 1'b0;
|
||||
end
|
||||
|
||||
reg pwr_up_reg;
|
||||
reg pwr_up = 1;
|
||||
always @(posedge clk) begin
|
||||
if (iord_s & (loa == PORTXT) & (hoa == XSTAT)) begin
|
||||
pwr_up_reg <= pwr_up;
|
||||
pwr_up <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// writing ports
|
||||
|
||||
//#nnAF
|
||||
localparam VCONF = 8'h00;
|
||||
localparam VPAGE = 8'h01;
|
||||
localparam GXOFFSL = 8'h02;
|
||||
localparam GXOFFSH = 8'h03;
|
||||
localparam GYOFFSL = 8'h04;
|
||||
localparam GYOFFSH = 8'h05;
|
||||
localparam TSCONF = 8'h06;
|
||||
localparam PALSEL = 8'h07;
|
||||
localparam XBORDER = 8'h0F;
|
||||
localparam VCONF = 8'h00;
|
||||
localparam VPAGE = 8'h01;
|
||||
localparam GXOFFSL = 8'h02;
|
||||
localparam GXOFFSH = 8'h03;
|
||||
localparam GYOFFSL = 8'h04;
|
||||
localparam GYOFFSH = 8'h05;
|
||||
localparam TSCONF = 8'h06;
|
||||
localparam PALSEL = 8'h07;
|
||||
localparam XBORDER = 8'h0F;
|
||||
|
||||
localparam T0XOFFSL = 8'h40;
|
||||
localparam T0XOFFSH = 8'h41;
|
||||
localparam T0YOFFSL = 8'h42;
|
||||
localparam T0YOFFSH = 8'h43;
|
||||
localparam T1XOFFSL = 8'h44;
|
||||
localparam T1XOFFSH = 8'h45;
|
||||
localparam T1YOFFSL = 8'h46;
|
||||
localparam T1YOFFSH = 8'h47;
|
||||
localparam T0XOFFSL = 8'h40;
|
||||
localparam T0XOFFSH = 8'h41;
|
||||
localparam T0YOFFSL = 8'h42;
|
||||
localparam T0YOFFSH = 8'h43;
|
||||
localparam T1XOFFSL = 8'h44;
|
||||
localparam T1XOFFSH = 8'h45;
|
||||
localparam T1YOFFSL = 8'h46;
|
||||
localparam T1YOFFSH = 8'h47;
|
||||
|
||||
localparam RAMPAGE = 8'h10; // this covers #10-#13
|
||||
localparam FMADDR = 8'h15;
|
||||
localparam TMPAGE = 8'h16;
|
||||
localparam T0GPAGE = 8'h17;
|
||||
localparam T1GPAGE = 8'h18;
|
||||
localparam SGPAGE = 8'h19;
|
||||
localparam DMASADDRL = 8'h1A;
|
||||
localparam DMASADDRH = 8'h1B;
|
||||
localparam DMASADDRX = 8'h1C;
|
||||
localparam DMADADDRL = 8'h1D;
|
||||
localparam DMADADDRH = 8'h1E;
|
||||
localparam DMADADDRX = 8'h1F;
|
||||
localparam RAMPAGE = 8'h10; // this covers #10-#13
|
||||
localparam FMADDR = 8'h15;
|
||||
localparam TMPAGE = 8'h16;
|
||||
localparam T0GPAGE = 8'h17;
|
||||
localparam T1GPAGE = 8'h18;
|
||||
localparam SGPAGE = 8'h19;
|
||||
localparam DMASADDRL = 8'h1A;
|
||||
localparam DMASADDRH = 8'h1B;
|
||||
localparam DMASADDRX = 8'h1C;
|
||||
localparam DMADADDRL = 8'h1D;
|
||||
localparam DMADADDRH = 8'h1E;
|
||||
localparam DMADADDRX = 8'h1F;
|
||||
|
||||
localparam SYSCONF = 8'h20;
|
||||
localparam MEMCONF = 8'h21;
|
||||
localparam HSINT = 8'h22;
|
||||
localparam VSINTL = 8'h23;
|
||||
localparam VSINTH = 8'h24;
|
||||
localparam IM2VECT = 8'h25;
|
||||
localparam INTFRM = 3'b000;
|
||||
localparam INTLIN = 3'b001;
|
||||
localparam INTDMA = 3'b010;
|
||||
localparam DMALEN = 8'h26;
|
||||
localparam DMACTRL = 8'h27;
|
||||
localparam DMANUM = 8'h28;
|
||||
localparam FDDVIRT = 8'h29;
|
||||
localparam INTMASK = 8'h2A;
|
||||
localparam CACHECONF = 8'h2B;
|
||||
localparam SYSCONF = 8'h20;
|
||||
localparam MEMCONF = 8'h21;
|
||||
localparam HSINT = 8'h22;
|
||||
localparam VSINTL = 8'h23;
|
||||
localparam VSINTH = 8'h24;
|
||||
localparam DMAWPD = 8'h25;
|
||||
localparam DMALEN = 8'h26;
|
||||
localparam DMACTRL = 8'h27;
|
||||
localparam DMANUM = 8'h28;
|
||||
localparam FDDVIRT = 8'h29;
|
||||
localparam INTMASK = 8'h2A;
|
||||
localparam CACHECONF = 8'h2B;
|
||||
localparam DMAWPA = 8'h2D;
|
||||
|
||||
localparam XSTAT = 8'h00;
|
||||
localparam DMASTAT = 8'h27;
|
||||
localparam XSTAT = 8'h00;
|
||||
localparam DMASTAT = 8'h27;
|
||||
|
||||
assign dmaport_wr[0] = portxt_wr & (hoa == DMASADDRL);
|
||||
assign dmaport_wr[1] = portxt_wr & (hoa == DMASADDRH);
|
||||
assign dmaport_wr[2] = portxt_wr & (hoa == DMASADDRX);
|
||||
assign dmaport_wr[3] = portxt_wr & (hoa == DMADADDRL);
|
||||
assign dmaport_wr[4] = portxt_wr & (hoa == DMADADDRH);
|
||||
assign dmaport_wr[5] = portxt_wr & (hoa == DMADADDRX);
|
||||
assign dmaport_wr[6] = portxt_wr & (hoa == DMALEN);
|
||||
assign dmaport_wr[7] = portxt_wr & (hoa == DMACTRL);
|
||||
assign dmaport_wr[8] = portxt_wr & (hoa == DMANUM);
|
||||
assign dmaport_wr[0] = portxt_wr && (hoa == DMASADDRL);
|
||||
assign dmaport_wr[1] = portxt_wr && (hoa == DMASADDRH);
|
||||
assign dmaport_wr[2] = portxt_wr && (hoa == DMASADDRX);
|
||||
assign dmaport_wr[3] = portxt_wr && (hoa == DMADADDRL);
|
||||
assign dmaport_wr[4] = portxt_wr && (hoa == DMADADDRH);
|
||||
assign dmaport_wr[5] = portxt_wr && (hoa == DMADADDRX);
|
||||
assign dmaport_wr[6] = portxt_wr && (hoa == DMALEN);
|
||||
assign dmaport_wr[7] = portxt_wr && (hoa == DMACTRL);
|
||||
assign dmaport_wr[8] = portxt_wr && (hoa == DMANUM);
|
||||
|
||||
assign zborder_wr = portfe_wr;
|
||||
assign border_wr = (portxt_wr & (hoa == XBORDER));
|
||||
assign zvpage_wr = p7ffd_wr;
|
||||
assign vpage_wr = (portxt_wr & (hoa == VPAGE ));
|
||||
assign vconf_wr = (portxt_wr & (hoa == VCONF ));
|
||||
assign gx_offsl_wr = (portxt_wr & (hoa == GXOFFSL));
|
||||
assign gx_offsh_wr = (portxt_wr & (hoa == GXOFFSH));
|
||||
assign gy_offsl_wr = (portxt_wr & (hoa == GYOFFSL));
|
||||
assign gy_offsh_wr = (portxt_wr & (hoa == GYOFFSH));
|
||||
assign t0x_offsl_wr = (portxt_wr & (hoa == T0XOFFSL));
|
||||
assign t0x_offsh_wr = (portxt_wr & (hoa == T0XOFFSH));
|
||||
assign t0y_offsl_wr = (portxt_wr & (hoa == T0YOFFSL));
|
||||
assign t0y_offsh_wr = (portxt_wr & (hoa == T0YOFFSH));
|
||||
assign t1x_offsl_wr = (portxt_wr & (hoa == T1XOFFSL));
|
||||
assign t1x_offsh_wr = (portxt_wr & (hoa == T1XOFFSH));
|
||||
assign t1y_offsl_wr = (portxt_wr & (hoa == T1YOFFSL));
|
||||
assign t1y_offsh_wr = (portxt_wr & (hoa == T1YOFFSH));
|
||||
assign tsconf_wr = (portxt_wr & (hoa == TSCONF));
|
||||
assign palsel_wr = (portxt_wr & (hoa == PALSEL));
|
||||
assign tmpage_wr = (portxt_wr & (hoa == TMPAGE));
|
||||
assign t0gpage_wr = (portxt_wr & (hoa == T0GPAGE));
|
||||
assign t1gpage_wr = (portxt_wr & (hoa == T1GPAGE));
|
||||
assign sgpage_wr = (portxt_wr & (hoa == SGPAGE));
|
||||
assign hint_beg_wr = (portxt_wr & (hoa == HSINT ));
|
||||
assign vint_begl_wr = (portxt_wr & (hoa == VSINTL));
|
||||
assign vint_begh_wr = (portxt_wr & (hoa == VSINTH));
|
||||
assign zborder_wr = portfe_wr;
|
||||
assign border_wr = (portxt_wr && (hoa == XBORDER));
|
||||
assign zvpage_wr = p7ffd_wr;
|
||||
assign vpage_wr = (portxt_wr && (hoa == VPAGE ));
|
||||
assign vconf_wr = (portxt_wr && (hoa == VCONF ));
|
||||
assign gx_offsl_wr = (portxt_wr && (hoa == GXOFFSL));
|
||||
assign gx_offsh_wr = (portxt_wr && (hoa == GXOFFSH));
|
||||
assign gy_offsl_wr = (portxt_wr && (hoa == GYOFFSL));
|
||||
assign gy_offsh_wr = (portxt_wr && (hoa == GYOFFSH));
|
||||
assign t0x_offsl_wr = (portxt_wr && (hoa == T0XOFFSL));
|
||||
assign t0x_offsh_wr = (portxt_wr && (hoa == T0XOFFSH));
|
||||
assign t0y_offsl_wr = (portxt_wr && (hoa == T0YOFFSL));
|
||||
assign t0y_offsh_wr = (portxt_wr && (hoa == T0YOFFSH));
|
||||
assign t1x_offsl_wr = (portxt_wr && (hoa == T1XOFFSL));
|
||||
assign t1x_offsh_wr = (portxt_wr && (hoa == T1XOFFSH));
|
||||
assign t1y_offsl_wr = (portxt_wr && (hoa == T1YOFFSL));
|
||||
assign t1y_offsh_wr = (portxt_wr && (hoa == T1YOFFSH));
|
||||
assign tsconf_wr = (portxt_wr && (hoa == TSCONF));
|
||||
assign palsel_wr = (portxt_wr && (hoa == PALSEL));
|
||||
assign tmpage_wr = (portxt_wr && (hoa == TMPAGE));
|
||||
assign t0gpage_wr = (portxt_wr && (hoa == T0GPAGE));
|
||||
assign t1gpage_wr = (portxt_wr && (hoa == T1GPAGE));
|
||||
assign sgpage_wr = (portxt_wr && (hoa == SGPAGE));
|
||||
assign hint_beg_wr = (portxt_wr && (hoa == HSINT ));
|
||||
assign vint_begl_wr = (portxt_wr && (hoa == VSINTL));
|
||||
assign vint_begh_wr = (portxt_wr && (hoa == VSINTH));
|
||||
|
||||
assign beeper_wr = portfe_wr;
|
||||
wire portfe_wr = (loa==PORTFE) && iowr_s;
|
||||
assign covox_wr = (loa==COVOX) && iowr_s;
|
||||
wire portxt_wr = (loa==PORTXT) && iowr_s;
|
||||
assign beeper_wr = portfe_wr;
|
||||
wire portfe_wr = (loa==PORTFE) && iowr_s;
|
||||
assign covox_wr = (loa==COVOX) && iowr_s;
|
||||
wire portxt_wr = ((loa==PORTXT) && iowr_s) || regs_we;
|
||||
|
||||
reg [7:0] rampage[0:3];
|
||||
assign xt_page = {rampage[3], rampage[2], rampage[1], rampage[0]};
|
||||
reg [7:0] rampage[0:3];
|
||||
assign xt_page = {rampage[3], rampage[2], rampage[1], rampage[0]};
|
||||
|
||||
wire lock128 = lock128_3 ? 1'b0 : (lock128_2 ? m1_lock128 : memconf[6]);
|
||||
wire lock128_2 = memconf[7:6] == 2'b10; // mode 2
|
||||
wire lock128_3 = memconf[7:6] == 2'b11; // mode 3
|
||||
wire lock128 = lock128_3 ? 1'b0 : (lock128_2 ? m1_lock128 : memconf[6]);
|
||||
wire lock128_2 = memconf[7:6] == 2'b10; // mode 2
|
||||
wire lock128_3 = memconf[7:6] == 2'b11; // mode 3
|
||||
|
||||
reg m1_lock128;
|
||||
always @(posedge clk)
|
||||
if (opfetch)
|
||||
m1_lock128 <= !(din[7] ^ din[6]);
|
||||
reg m1_lock128;
|
||||
always @(posedge clk) if (opfetch) m1_lock128 <= !(din[7] ^ din[6]);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
fmaddr[4] <= 1'b0;
|
||||
intmask <= 8'b1;
|
||||
fddvirt <= 8'b0;
|
||||
sysconf <= 8'h00; // 3.5 MHz
|
||||
memconf <= 8'h04; // no map
|
||||
cacheconf <= 4'h0; // no cache
|
||||
|
||||
always @(posedge clk)
|
||||
if (rst)
|
||||
begin
|
||||
fmaddr[4] <= 1'b0;
|
||||
//im2v_frm <= 3'b111;
|
||||
intmask <= 8'b1;
|
||||
//fddvirt <= 4'b0;
|
||||
fddvirt <= 4'b0001; // VIRTUAL DOS A driver virtual
|
||||
sysconf <= 8'h01; // turbo 7 MHz
|
||||
//-------
|
||||
memconf <= MEMCONF_RESET; // mode=3, normal map
|
||||
cacheconf <= CACHECONF_RESET; // no cache
|
||||
//---------------------------------------------
|
||||
rampage[0] <= CPU_BANK_0_RESET; //8'h00;
|
||||
rampage[1] <= CPU_BANK_1_RESET; //8'h05;
|
||||
rampage[2] <= CPU_BANK_2_RESET; //8'h02;
|
||||
rampage[3] <= CPU_BANK_3_RESET; //8'h00;
|
||||
end
|
||||
|
||||
else
|
||||
if (p7ffd_wr)
|
||||
begin
|
||||
memconf[0] <= din[4]; //<= din[4] = ROM128
|
||||
rampage[3] <= {2'b0, lock128_3 ? {din[5], din[7:6]} : ({1'b0, lock128 ? 2'b0 : din[7:6]}), din[2:0]};
|
||||
end //lock128_3 = memconf[7:6] == 2'b11; // mode 3
|
||||
|
||||
else
|
||||
if (portxt_wr)
|
||||
begin
|
||||
if (hoa[7:2] == RAMPAGE[7:2])
|
||||
rampage[hoa[1:0]] <= din;
|
||||
if (hoa == FMADDR)
|
||||
fmaddr <= din[4:0];
|
||||
if (hoa == SYSCONF)
|
||||
begin
|
||||
sysconf <= din;
|
||||
cacheconf <= {4{din[2]}};
|
||||
end
|
||||
if (hoa == CACHECONF)
|
||||
cacheconf <= din[3:0];
|
||||
if (hoa == MEMCONF) // & !lock_conf
|
||||
memconf <= din;
|
||||
//================================
|
||||
//if (hoa == IM2VECT)
|
||||
//begin
|
||||
// if (din[6:4] == INTFRM)
|
||||
// im2v_frm <= din[3:1];
|
||||
// if (din[6:4] == INTLIN)
|
||||
// im2v_lin <= din[3:1];
|
||||
// if (din[6:4] == INTDMA)
|
||||
// im2v_dma <= din[3:1];
|
||||
//end
|
||||
//================================
|
||||
if (hoa == FDDVIRT)
|
||||
fddvirt <= din[3:0];
|
||||
if (hoa == INTMASK)
|
||||
intmask <= din;
|
||||
rampage[0]<= 8'h00;
|
||||
rampage[1]<= 8'h05;
|
||||
rampage[2]<= 8'h02;
|
||||
rampage[3]<= 8'h00;
|
||||
end
|
||||
else if (p7ffd_wr) begin
|
||||
memconf[0] <= din[4];
|
||||
rampage[3] <= {2'b0, lock128_3 ? {din[5], din[7:6]} : ({1'b0, lock128 ? 2'b0 : din[7:6]}), din[2:0]};
|
||||
end
|
||||
else if (portxt_wr) begin
|
||||
if (hoa[7:2] == RAMPAGE[7:2]) rampage[hoa[1:0]] <= din;
|
||||
|
||||
if (hoa == FMADDR) fmaddr <= din[4:0];
|
||||
|
||||
if (hoa == SYSCONF) begin
|
||||
sysconf <= din;
|
||||
cacheconf <= {4{din[2]}};
|
||||
end
|
||||
|
||||
if (hoa == DMAWPD) dmawpdev <= din[1:0];
|
||||
if (hoa == CACHECONF) cacheconf <= din[3:0];
|
||||
if (hoa == MEMCONF) memconf <= din;
|
||||
if (hoa == FDDVIRT) fddvirt <= din;
|
||||
if (hoa == INTMASK) intmask <= din;
|
||||
end
|
||||
end
|
||||
|
||||
// 7FFD port
|
||||
wire p7ffd_wr = !a[15] && (loa==PORTFD) && iowr_s && !lock48;
|
||||
|
||||
reg lock48;
|
||||
always @(posedge clk)
|
||||
if (rst)
|
||||
lock48 <= 1'b0;
|
||||
else if (p7ffd_wr && !lock128_3)
|
||||
lock48 <= din[5];
|
||||
wire p7ffd_wr = !a[15] && (loa==PORTFD) && iowr_s && !lock48;
|
||||
|
||||
reg lock48;
|
||||
always @(posedge clk) begin
|
||||
if (rst) lock48 <= 1'b0;
|
||||
else if (p7ffd_wr && !lock128_3) lock48 <= din[5];
|
||||
end
|
||||
|
||||
// AY control
|
||||
wire ay_hit = (loa==PORTFD) & a[15];
|
||||
assign ay_bc1 = ay_hit & a[14] & iorw;
|
||||
assign ay_bdir = ay_hit & iowr;
|
||||
//===========================================
|
||||
|
||||
wire ay_hit = (loa==PORTFD) & a[15];
|
||||
assign ay_bc1 = ay_hit & a[14] & iordwr;
|
||||
assign ay_bdir = ay_hit & iowr;
|
||||
|
||||
// VG93
|
||||
wire virt_vg = fddvirt[drive_sel];
|
||||
wire [3:0] fddvrt = fddvirt[3:0];
|
||||
wire virt_vg = fddvrt[drive_sel_raw];
|
||||
wire open_vg = fddvirt[7];
|
||||
assign drive_sel = {drive_sel_raw[1], drive_sel_raw[0]};
|
||||
|
||||
assign vg_cs_n = !(iorw && vg_port && dos && !vdos && !virt_vg);
|
||||
assign vg_wrFF = wr && iorq_s && vgsys_port && dos && !vdos && !virt_vg;
|
||||
wire vg_wen = (dos || open_vg) && !vdos && !virt_vg;
|
||||
assign vg_cs_n = !(iordwr && vg_port && vg_wen);
|
||||
assign vg_wrFF = iowr_s && vgsys_port && vg_wen;
|
||||
wire vg_wrDS = iowr_s && vgsys_port && (dos || open_vg);
|
||||
|
||||
assign vdos_on = rdwr && iorq_s && (vg_port || vgsys_port) && dos && !vdos && virt_vg;
|
||||
assign vdos_off = rdwr && iorq_s && vg_port && vdos;
|
||||
assign vdos_on = iordwr_s && (vg_port || vgsys_port) && dos && !vdos && virt_vg;
|
||||
assign vdos_off = iordwr_s && vg_port && vdos;
|
||||
|
||||
// write drive number
|
||||
always @(posedge clk)
|
||||
if (iowr_s && vgsys_port && dos)
|
||||
drive_sel <= din[1:0];
|
||||
// write drive number
|
||||
reg [1:0] drive_sel_raw;
|
||||
always @(posedge clk) if (vg_wrDS) drive_sel_raw <= din[1:0];
|
||||
|
||||
// SD card (Z-controller compatible)
|
||||
wire sdcfg_wr;
|
||||
wire sddat_wr;
|
||||
wire sddat_rd;
|
||||
reg [1:0] spi_cs_n;
|
||||
|
||||
// SD card (Z-control?r compatible)
|
||||
wire sdcfg_wr;
|
||||
wire sddat_wr;
|
||||
wire sddat_rd;
|
||||
// if loader =1 should be ENABLE
|
||||
assign sdcfg_wr = ((loa==SDCFG) && iowr_s && ((!dos || vdos)) || loader);
|
||||
assign sddat_wr = ((loa==SDDAT) && iowr_s && ((!dos || vdos)) || loader);
|
||||
assign sddat_rd = ((loa==SDDAT) && iord_s);
|
||||
assign sdcfg_wr = ((loa==SDCFG) && iowr_s && (!dos || vdos));
|
||||
assign sddat_wr = ((loa==SDDAT) && iowr_s && (!dos || vdos));
|
||||
assign sddat_rd = ((loa==SDDAT) && iord_s);
|
||||
|
||||
// SDCFG write - sdcs_n control
|
||||
always @(posedge clk)
|
||||
if (rst)
|
||||
sdcs_n <= 1'b1;
|
||||
else if (sdcfg_wr)
|
||||
sdcs_n <= din[1];
|
||||
// SDCFG write - sdcs_n control
|
||||
always @(posedge clk) begin
|
||||
if (rst) spi_cs_n <= 2'b11;
|
||||
else if (sdcfg_wr) spi_cs_n <= {~din[2], din[1]};
|
||||
end
|
||||
|
||||
// start signal for SPI module with resyncing to fclk
|
||||
assign sd_start = sddat_wr || sddat_rd;
|
||||
|
||||
// start signal for SPI module with resyncing to fclk
|
||||
assign sd_start = sddat_wr || sddat_rd;
|
||||
|
||||
|
||||
// data for SPI module
|
||||
assign sd_datain = wr ? din : 8'hFF;
|
||||
|
||||
// data for SPI module
|
||||
assign sd_datain = wr ? din : 8'hFF;
|
||||
|
||||
// xxF7
|
||||
wire portf7_wr = ((loa==PORTF7) && (a[8]==1'b1) && port_wr && (!dos || vdos));
|
||||
wire portf7_rd = ((loa==PORTF7) && (a[8]==1'b1) && port_rd && (!dos || vdos));
|
||||
|
||||
wire portf7_wr = ((loa==PORTF7) && (a[8]==1'b1) && port_wr && (!dos || vdos));
|
||||
wire portf7_rd = ((loa==PORTF7) && (a[8]==1'b1) && port_rd && (!dos || vdos));
|
||||
|
||||
// EFF7 port
|
||||
reg [7:0] peff7;
|
||||
always @(posedge clk)
|
||||
if (rst)
|
||||
peff7 <= 8'h00;
|
||||
else if (!a[12] && portf7_wr && !dos) // #EEF7 in dos is not accessible
|
||||
peff7 <= din;
|
||||
|
||||
reg [7:0] peff7;
|
||||
always @(posedge clk) begin
|
||||
if (rst) peff7 <= 8'h00;
|
||||
else if (!a[12] && portf7_wr && !dos) peff7 <= din; // #EEF7 in dos is not accessible
|
||||
end
|
||||
|
||||
// gluclock ports
|
||||
wire gluclock_on = peff7[7] || dos; // in dos mode EEF7 is not accessible, gluclock access is ON in dos mode.
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (gluclock_on && portf7_wr) // gluclocks on
|
||||
if( !a[13] ) // $DFF7 - addr reg
|
||||
gluclock_addr <= din;
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
// write to wait registers
|
||||
always @(posedge clk) begin
|
||||
// gluclocks
|
||||
if (gluclock_on && portf7_wr && !a[14]) // $BFF7 - data reg
|
||||
wait_write <= din;
|
||||
// com ports
|
||||
else if (comport_wr) // $F8EF..$FFEF - comports
|
||||
wait_write <= din;
|
||||
end
|
||||
|
||||
wire gluclock_on = peff7[7] || dos; // in dos mode EEF7 is not accessible, gluclock access is ON in dos mode.
|
||||
|
||||
// comports
|
||||
wire comport_wr = ((loa==COMPORT) && port_wr);
|
||||
wire comport_rd = ((loa==COMPORT) && port_rd);
|
||||
wire comport_wr = ((loa == COMPORT) && port_wr);
|
||||
wire comport_rd = ((loa == COMPORT) && port_rd);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (comport_wr || comport_rd)
|
||||
comport_addr <= a[10:8];
|
||||
// write to wait registers
|
||||
always @(posedge clk) begin
|
||||
// gluclocks
|
||||
if (gluclock_on && portf7_wr) begin
|
||||
if (!a[14]) wait_write <= din; // $BFF7 - data reg
|
||||
if (!a[13]) wait_addr <= din; // $DFF7 - addr reg
|
||||
end
|
||||
|
||||
|
||||
// com ports
|
||||
if (comport_wr) wait_write <= din; // $xxEF
|
||||
if (comport_wr || comport_rd) wait_addr <= a[15:8];
|
||||
|
||||
if ((loa==PORTXT) && (hoa == DMAWPA)) wait_addr <= din;
|
||||
end
|
||||
|
||||
// wait from wait registers
|
||||
// ACHTUNG!!!! here portxx_wr are ON Z80 CLOCK! logic must change when moving to clk strobes
|
||||
assign wait_start_gluclock = (gluclock_on && !a[14] && (portf7_rd || portf7_wr)); // $BFF7 - gluclock r/w
|
||||
assign wait_start_comport = (comport_rd || comport_wr);
|
||||
// ACHTUNG!!!! here portxx_wr are ON Z80 CLOCK! logic must change when moving to clk strobes
|
||||
assign wait_start_gluclock = (gluclock_on && !a[14] && (portf7_rd || portf7_wr)); // $BFF7 - gluclock r/w
|
||||
assign wait_start_comport = (comport_rd || comport_wr);
|
||||
|
||||
endmodule
|
||||
|
||||
56
src/tsconf.v
56
src/tsconf.v
@ -160,8 +160,6 @@ wire dram_req;
|
||||
wire dram_rnw;
|
||||
wire dos;
|
||||
|
||||
wire [7:0] gluclock_addr;
|
||||
|
||||
wire vdos;
|
||||
wire pre_vdos;
|
||||
wire vdos_off;
|
||||
@ -186,6 +184,7 @@ wire iowr_s;
|
||||
wire iorw_s;
|
||||
wire memwr_s;
|
||||
wire opfetch_s;
|
||||
wire regs_we;
|
||||
|
||||
// zports OUT
|
||||
wire [7:0] dout_ports;
|
||||
@ -382,7 +381,6 @@ zports TS05
|
||||
.dataout(ena_ports),
|
||||
.a(cpu_a_bus),
|
||||
.rst(reset),
|
||||
.loader(0), //loader, -- for load ROM, SPI should be enable
|
||||
.opfetch(opfetch), // from zsignals
|
||||
.rd(rd),
|
||||
.wr(wr),
|
||||
@ -393,9 +391,8 @@ zports TS05
|
||||
.iord_s(iord_s),
|
||||
.iowr(iowr),
|
||||
.iowr_s(iowr_s),
|
||||
.iorw(iorw),
|
||||
.iorw_s(iorw_s),
|
||||
.external_port(), // asserts for AY and VG93 accesses
|
||||
.iordwr(iorw),
|
||||
.iordwr_s(iorw_s),
|
||||
.zborder_wr(zborder_wr),
|
||||
.border_wr(border_wr),
|
||||
.zvpage_wr(zvpage_wr),
|
||||
@ -424,6 +421,7 @@ zports TS05
|
||||
.vint_begh_wr(vint_begh_wr),
|
||||
.xt_page(xt_page),
|
||||
.fmaddr(fmaddr),
|
||||
.regs_we(regs_we),
|
||||
.sysconf(sysconf),
|
||||
.memconf(memconf),
|
||||
.cacheconf(cacheconf),
|
||||
@ -434,7 +432,6 @@ zports TS05
|
||||
.vdos(vdos),
|
||||
.vdos_on(vdos_on),
|
||||
.vdos_off(vdos_off),
|
||||
.rstrom(2'b11),
|
||||
.tape_read(1),
|
||||
.keys_in(kb_do_bus), // keys (port FE)
|
||||
.mus_in(mouse_do), // mouse (xxDF)
|
||||
@ -445,12 +442,9 @@ zports TS05
|
||||
.sd_start(cpu_spi_req), // to SPI
|
||||
.sd_datain(cpu_spi_din), // to SPI(7 downto 0);
|
||||
.sd_dataout(spi_dout), // from SPI(7 downto 0);
|
||||
.gluclock_addr(gluclock_addr),
|
||||
.wait_read(mc146818a_do_bus),
|
||||
.com_data_rx(8'b00000000), //uart_do_bus,
|
||||
.com_status(8'b10010000), //'1' & uart_tx_empty & uart_tx_fifo_empty & "1000" & uart_rx_avail,
|
||||
//com_status=> '0' & uart_tx_empty & uart_tx_fifo_empty & "0000" & '1',
|
||||
.lock_conf(1)
|
||||
.wait_addr(wait_addr),
|
||||
.wait_start_gluclock(wait_start_gluclock),
|
||||
.wait_read(mc146818a_do_bus)
|
||||
);
|
||||
|
||||
zmem TS06
|
||||
@ -646,7 +640,8 @@ zmaps TS10
|
||||
.dma_cram_we(dma_cram_we),
|
||||
.dma_sfile_we(dma_sfile_we),
|
||||
.cram_we(cram_we),
|
||||
.sfile_we(sfile_we)
|
||||
.sfile_we(sfile_we),
|
||||
.regs_we(regs_we)
|
||||
);
|
||||
|
||||
spi TS11
|
||||
@ -745,9 +740,9 @@ kempston_mouse KM
|
||||
);
|
||||
|
||||
// MC146818A,RTC
|
||||
wire mc146818a_wr = port_bff7 && ~cpu_wr_n;
|
||||
wire [7:0] mc146818a_do_bus;
|
||||
wire port_bff7 = ~cpu_iorq_n && cpu_a_bus == 16'hBFF7 && cpu_m1_n && port_eff7_reg[7];
|
||||
wire [7:0] wait_addr;
|
||||
wire wait_start_gluclock;
|
||||
wire [7:0] mc146818a_do_bus;
|
||||
|
||||
reg ena_0_4375mhz;
|
||||
always @(negedge clk_28mhz) begin
|
||||
@ -756,12 +751,6 @@ always @(negedge clk_28mhz) begin
|
||||
ena_0_4375mhz <= !div; //28MHz/64
|
||||
end
|
||||
|
||||
reg [7:0] port_eff7_reg;
|
||||
always @(posedge clk_28mhz) begin
|
||||
if (reset) port_eff7_reg <= 0;
|
||||
else if (~cpu_iorq_n && ~cpu_wr_n && cpu_a_bus == 16'hEFF7) port_eff7_reg <= cpu_do_bus; //for RTC
|
||||
end
|
||||
|
||||
mc146818a SE9
|
||||
(
|
||||
.RESET(reset),
|
||||
@ -771,8 +760,8 @@ mc146818a SE9
|
||||
.KEYSCANCODE(key_scancode),
|
||||
.RTC(RTC),
|
||||
.CMOSCfg(CMOSCfg),
|
||||
.WR(mc146818a_wr),
|
||||
.A(gluclock_addr[7:0]),
|
||||
.WR(wait_start_gluclock & ~cpu_wr_n),
|
||||
.A(wait_addr),
|
||||
.DI(cpu_do_bus),
|
||||
.DO(mc146818a_do_bus)
|
||||
);
|
||||
@ -909,15 +898,14 @@ assign RESET_OUT = reset;
|
||||
|
||||
// CPU interface
|
||||
assign cpu_di_bus =
|
||||
(csrom && ~cpu_mreq_n && ~cpu_rd_n) ? bios_do_bus : // BIOS
|
||||
(~cpu_mreq_n && ~cpu_rd_n) ? sdr_do_bus : // SDRAM
|
||||
(intack) ? im2vect :
|
||||
(port_bff7 && port_eff7_reg[7] && ~cpu_iorq_n && ~cpu_rd_n) ? mc146818a_do_bus : // MC146818A
|
||||
(gs_sel && ~cpu_rd_n) ? gs_do_bus : // General Sound
|
||||
(ts_enable && ~cpu_rd_n) ? ts_do : // TurboSound
|
||||
(cpu_a_bus == 16'h0001 && ~cpu_iorq_n && ~cpu_rd_n) ? key_scancode :
|
||||
(ena_ports) ? dout_ports :
|
||||
8'b11111111;
|
||||
(csrom && ~cpu_mreq_n && ~cpu_rd_n) ? bios_do_bus : // BIOS
|
||||
(~cpu_mreq_n && ~cpu_rd_n) ? sdr_do_bus : // SDRAM
|
||||
(intack) ? im2vect :
|
||||
(gs_sel && ~cpu_rd_n) ? gs_do_bus : // General Sound
|
||||
(ts_enable && ~cpu_rd_n) ? ts_do : // TurboSound
|
||||
(cpu_a_bus == 16'h0001 && ~cpu_iorq_n && ~cpu_rd_n) ? key_scancode :
|
||||
(ena_ports) ? dout_ports :
|
||||
8'b11111111;
|
||||
// TURBO
|
||||
assign turbo = sysconf[1:0];
|
||||
|
||||
|
||||
Reference in New Issue
Block a user