mirror of
https://github.com/UzixLS/TSConf_MiST.git
synced 2025-07-18 14:51:25 +03:00
Update the video to latest version.
This commit is contained in:
sorgelig
@ -20,6 +20,8 @@
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{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Inferred RAM node \"emu:emu\|tsconf:tsconf\|gs:U15\|T80s:z80_unit\|T80:u0\|T80_Reg:Regs\|RegsH_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Inferred RAM node \"emu:emu\|tsconf:tsconf\|gs:U15\|T80s:z80_unit\|T80:u0\|T80_Reg:Regs\|RegsL_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Inferred RAM node \"emu:emu\|tsconf:tsconf\|T80s:CPU\|T80:u0\|T80_Reg:Regs\|RegsH_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Inferred RAM node \"emu:emu\|tsconf:tsconf\|T80s:CPU\|T80:u0\|T80_Reg:Regs\|RegsL_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
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||||
{ "" "" "" "*" { } { } 0 21074 "" 0 0 "Design Software" 0 -1 0 ""}
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||||
{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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||||
{ "" "" "" "sysmem_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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||||
@ -361,12 +361,7 @@ set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
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set_global_assignment -name CDF_FILE jtag.cdf
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set_global_assignment -name QIP_FILE sys/sys.qip
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set_global_assignment -name QSYS_FILE sys/vip.qsys
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set_global_assignment -name VHDL_FILE src/t80/T80_Reg.vhd
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||||
set_global_assignment -name VHDL_FILE src/t80/T80_Pack.vhd
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set_global_assignment -name VHDL_FILE src/t80/T80_MCode.vhd
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set_global_assignment -name VHDL_FILE src/t80/T80_ALU.vhd
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set_global_assignment -name VHDL_FILE src/t80/T80.vhd
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set_global_assignment -name VHDL_FILE src/t80/T80s.vhd
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set_global_assignment -name QIP_FILE src/t80/T80.qip
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set_global_assignment -name VERILOG_FILE src/cpu/zsignals.v
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set_global_assignment -name VERILOG_FILE src/cpu/zports.v
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set_global_assignment -name VERILOG_FILE src/cpu/zmem.v
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@ -96,7 +96,6 @@ module arbiter(
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// TS
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input wire [23:0] ts_addr,
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input wire ts_req,
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input wire ts_z80_lp,
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output wire ts_pre_next,
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output wire ts_next,
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@ -256,12 +256,10 @@ wire video_next;
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wire video_pre_next;
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wire next_video;
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wire video_strobe;
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wire video_next_strobe;
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// TS
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wire [20:0] ts_addr;
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wire ts_req;
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wire ts_z80_lp;
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// IN
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wire ts_pre_next;
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@ -518,7 +516,6 @@ arbiter TS07
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.video_pre_next(video_pre_next),
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.video_next(video_next), // (c2) at this signal video_addr may be changed; it is one clock leading the video_strobe
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.video_strobe(video_strobe), // (c3) one-cycle strobe meaning that video_data is available
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.video_next_strobe(video_next_strobe),
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.next_vid(next_video), // used for TM prefetch
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.cpu_addr({csvrom, 2'b00, cpu_addr_20}),
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.cpu_wrdata(cpu_do_bus),
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@ -537,7 +534,6 @@ arbiter TS07
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.dma_next(dma_next),
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.ts_addr({3'b000, ts_addr}),
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.ts_req(ts_req),
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.ts_z80_lp(ts_z80_lp),
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.ts_pre_next(ts_pre_next),
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.ts_next(ts_next),
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.tm_addr({3'b000, tm_addr}),
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@ -564,7 +560,6 @@ video_top TS08
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.hblank(VGA_HBLANK),
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.vblank(VGA_VBLANK),
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.pix_stb(VGA_CEPIX),
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.a(cpu_a_bus),
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.d(cpu_do_bus),
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.zmd(zmd),
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.zma(zma),
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@ -607,10 +602,8 @@ video_top TS08
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.video_pre_next(video_pre_next),
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.next_video(next_video),
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.video_strobe(video_strobe),
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.video_next_strobe(video_next_strobe),
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.ts_addr(ts_addr),
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.ts_req(ts_req),
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.ts_z80_lp(ts_z80_lp),
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.ts_pre_next(ts_pre_next),
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.ts_next(ts_next),
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.tm_addr(tm_addr),
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@ -14,7 +14,7 @@
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-- Quartus II generated Memory Initialization File (.mif)
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WIDTH=15;
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WIDTH=16;
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DEPTH=256;
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ADDRESS_RADIX=HEX;
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@ -1,7 +1,7 @@
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// This module fetches video data from DRAM
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module video_fetch (
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module video_fetch
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(
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// clocks
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input wire clk,
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@ -17,12 +17,9 @@ module video_fetch (
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// DRAM interface
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input wire video_strobe,
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input wire [15:0] video_data
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);
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// fetching data
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always @(posedge clk) if (video_strobe)
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begin
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if (f_sel[0]) fetch_temp[ 7: 0] <= b_sel[0] ? video_data[15:8] : video_data[ 7:0];
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@ -31,8 +28,6 @@ module video_fetch (
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if (f_sel[3]) fetch_temp[31:24] <= video_data[15:8];
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end
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always @(posedge clk) if (fetch_stb)
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fetch_data <= fetch_temp;
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always @(posedge clk) if (fetch_stb) fetch_data <= fetch_temp;
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endmodule
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@ -1,14 +1,15 @@
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// This module decodes video modes
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module video_mode (
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module video_mode
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(
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// clocks
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input wire clk, f1, c3,
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// video config
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input wire [7:0] vpage,
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input wire [7:0] vconf,
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input wire ts_rres_ext,
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input wire v60hz,
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// video parameters & mode controls
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@ -18,6 +19,10 @@ module video_mode (
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output wire [8:0] hpix_end,
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output wire [8:0] vpix_beg,
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output wire [8:0] vpix_end,
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output wire [8:0] hpix_beg_ts,
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output wire [8:0] hpix_end_ts,
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output wire [8:0] vpix_beg_ts,
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output wire [8:0] vpix_end_ts,
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output wire [5:0] x_tiles,
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output wire [4:0] go_offs,
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output wire [3:0] fetch_sel,
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@ -44,16 +49,13 @@ module video_mode (
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output wire [ 4:0] video_bw
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);
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wire [1:0] vmod = vconf[1:0];
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wire [1:0] rres = vconf[7:6];
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// clocking strobe for pixels (TV)
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assign pix_stb = tv_hires ? f1 : c3;
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always @(posedge clk)
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if (line_start_s)
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vga_hires <= tv_hires;
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always @(posedge clk) if (line_start_s) vga_hires <= tv_hires;
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// Modes
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localparam M_ZX = 2'h0; // ZX
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@ -198,8 +200,13 @@ module video_mode (
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assign hpix_end = hp_end[rres];
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assign vpix_beg = vp_beg[rres];
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assign vpix_end = vp_end[rres];
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assign x_tiles = x_tile[rres];
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assign hpix_beg_ts = ts_rres_ext ? hp_beg[3] : hp_beg[rres];
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assign hpix_end_ts = ts_rres_ext ? hp_end[3] : hp_end[rres];
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assign vpix_beg_ts = ts_rres_ext ? vp_beg[3] : vp_beg[rres];
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assign vpix_end_ts = ts_rres_ext ? vp_end[3] : vp_end[rres];
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assign x_tiles = ts_rres_ext ? x_tile[3] : x_tile[rres];
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// videomode addresses
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wire [20:0] v_addr[0:3];
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@ -1,9 +1,9 @@
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// This module generates video for DAC
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// MVV corrected 24bpp 24.08.2014
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module video_out (
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// (c)2015 TSL
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module video_out
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(
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// clocks
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input wire clk, f0, c3,
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@ -19,26 +19,19 @@ module video_out (
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input wire [3:0] palsel,
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// Z80 pins
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input wire [14:0] cram_data_in,
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input wire [15:0] cram_data_in,
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input wire [7:0] cram_addr_in,
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input wire cram_we,
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// video data
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input wire [7:0] vplex_in, //<====== INPUT
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input wire [7:0] vgaplex, //<====== INPUT VGA
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input wire [7:0] vplex_in,
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input wire [7:0] vgaplex,
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output wire [7:0] vred,
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output wire [7:0] vgrn,
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output wire [7:0] vblu,
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//---------------------
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output wire [3:0] tst
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output wire vdac_mode
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);
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assign tst[0] = clk; ////phase[0];
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assign tst[1] = cram_we; //phase[1];
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assign tst[2] = cram_addr_in[0]; //
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assign tst[3] = cram_data_in[0]; //pwm[3][{phase, 1'b0}]; //!pwm[igrn][{phase, 1'b1}];
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// TV/VGA mux
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reg [7:0] vplex;
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@ -49,28 +42,27 @@ wire plex_sel = vga_on ? plex_sel_in[0] : plex_sel_in[1];
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wire hires = vga_on ? vga_hires : tv_hires;
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wire [7:0] vdata = hires ? {palsel, plex_sel ? plex[3:0] : plex[7:4]} : plex;
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// CRAM =====================================================================
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wire [14:0] vpixel;
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dpram #(.DATAWIDTH(15), .ADDRWIDTH(8), .MEM_INIT_FILE("src/video/video_cram.mif")) video_cram
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// CRAM
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wire [15:0] vpixel;
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dpram #(.DATAWIDTH(16), .ADDRWIDTH(8), .MEM_INIT_FILE("src/video/video_cram.mif")) video_cram
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(
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.clock (clk),
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.address_a(cram_addr_in),
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.data_a (cram_data_in),
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.wren_a (cram_we),
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.address_b(vdata), //-<INPUT
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.address_b(vdata),
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.q_b (vpixel)
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);
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//=============VPIXEL=================================
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reg blank;
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always @(posedge clk) blank <= vga_on ? vga_blank : tv_blank;
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wire [14:0] vpix = blank ? 15'b0 : vpixel; //OK for Spectrum mode // 5 bits for every color
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wire [14:0] vpix = blank ? 15'b0 : vpixel[14:0];
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assign vred = {vpix[14:10], vpix[14:12]};
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assign vgrn = {vpix[ 9: 5], vpix[ 9: 7]};
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assign vblu = {vpix[ 4: 0], vpix[ 4: 2]};
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assign vdac_mode = vpixel[15];
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endmodule
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@ -1,7 +1,8 @@
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// This module latches all port parameters for video from Z80
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module video_ports (
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module video_ports
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(
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// clocks
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input wire clk,
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@ -56,7 +57,6 @@ module video_ports (
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output reg [7:0] t0gpage,
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output reg [7:0] t1gpage,
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output reg [7:0] sgpage
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);
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reg [7:0] vpage_r;
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@ -70,35 +70,23 @@ module video_ports (
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wire [8:0] vint_beg_inc = vint_beg + vint_inc;
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wire [8:0] vint_beg_next = {(vint_beg_inc[8:6] == 3'b101) ? 3'b0 : vint_beg_inc[8:6], vint_beg_inc[5:0]}; // if over 319 lines, decrement 320
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reg [3:0] vint_inc;
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always @(posedge clk)
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if (res)
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begin
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always @(posedge clk) begin
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if (res) begin
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||||
vint_beg <= 9'd0;
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vint_inc <= 4'b0;
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end
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else if (vint_begl_wr)
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vint_beg[7:0] <= d;
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//vint_beg[7:0] <= 8'd0; //--- мигает vint_beg[8] <= 1'b0; //----
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//vint_beg[7:0] <= 8'd10; //---мигает vint_beg[8] <= 1'b0; //----
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//vint_beg[7:0] <= 8'd20; //---мигает vint_beg[8] <= 1'b0; //----
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//vint_beg[7:0] <= 8'd50;--- нет картинки
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//vint_beg[7:0] <= 8'd255;
|
||||
|
||||
else if (vint_begh_wr)
|
||||
begin
|
||||
else if (vint_begl_wr) vint_beg[7:0] <= d;
|
||||
else if (vint_begh_wr) begin
|
||||
vint_beg[8] <= d[0];
|
||||
//vint_beg[8] <= 1'b0; //----
|
||||
vint_inc <= d[7:4];
|
||||
end
|
||||
else if (int_start) vint_beg <= vint_beg_next;
|
||||
end
|
||||
|
||||
else if (int_start)
|
||||
vint_beg <= vint_beg_next;
|
||||
|
||||
always @(posedge clk)
|
||||
if (res)
|
||||
begin
|
||||
always @(posedge clk) begin
|
||||
if (res) begin
|
||||
vpage_r <= 8'h05;
|
||||
vconf_r <= 8'h00;
|
||||
gx_offs_r <= 9'b0;
|
||||
@ -107,10 +95,8 @@ module video_ports (
|
||||
tsconf <= 8'b0;
|
||||
hint_beg <= 8'd1;
|
||||
end
|
||||
|
||||
else
|
||||
begin
|
||||
if (zborder_wr ) border <= {5'b11110, d[2:0]};
|
||||
else begin
|
||||
if (zborder_wr ) border <= {palsel[3:0], 1'b0, d[2:0]};
|
||||
if (border_wr ) border <= d;
|
||||
if (gy_offsl_wr ) gy_offs[7:0] <= d;
|
||||
if (gy_offsh_wr ) gy_offs[8] <= d[0];
|
||||
@ -135,17 +121,11 @@ module video_ports (
|
||||
if (t1x_offsh_wr) t1x_offs_r[8] <= d[0];
|
||||
if (t0gpage_wr ) t0gpage_r <= d;
|
||||
if (t1gpage_wr ) t1gpage_r <= d;
|
||||
// if (t0x_offsl_wr) t0x_offs[7:0] <= d;
|
||||
// if (t0x_offsh_wr) t0x_offs[8] <= d[0];
|
||||
// if (t1x_offsl_wr) t1x_offs[7:0] <= d;
|
||||
// if (t1x_offsh_wr) t1x_offs[8] <= d[0];
|
||||
// if (t0gpage_wr ) t0gpage <= d;
|
||||
// if (t1gpage_wr ) t1gpage <= d;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// latching regs at line start, delaying hires for 1 line
|
||||
always @(posedge clk)
|
||||
always @(posedge clk) begin
|
||||
if (res)
|
||||
begin
|
||||
vpage <= 8'h05;
|
||||
@ -153,12 +133,8 @@ module video_ports (
|
||||
gx_offs <= 9'b0;
|
||||
palsel <= 8'h0F;
|
||||
end
|
||||
|
||||
else if (zvpage_wr)
|
||||
vpage <= {6'b000001, d[3], 1'b1};
|
||||
|
||||
else if (line_start_s)
|
||||
begin
|
||||
else if (zvpage_wr) vpage <= {6'b000001, d[3], 1'b1};
|
||||
else if (line_start_s) begin
|
||||
vpage <= vpage_r;
|
||||
vconf <= vconf_r;
|
||||
gx_offs <= gx_offs_r;
|
||||
@ -168,6 +144,6 @@ module video_ports (
|
||||
t0gpage <= t0gpage_r;
|
||||
t1gpage <= t1gpage_r;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
@ -1,12 +1,13 @@
|
||||
// This module renders video data for output
|
||||
|
||||
module video_render (
|
||||
|
||||
module video_render
|
||||
(
|
||||
// clocks
|
||||
input wire clk, c1,
|
||||
|
||||
// video controls
|
||||
input wire hvpix,
|
||||
input wire hvtspix,
|
||||
input wire nogfx,
|
||||
input wire notsu,
|
||||
input wire gfxovr,
|
||||
@ -23,7 +24,6 @@ module video_render (
|
||||
input wire [ 7:0] border_in,
|
||||
input wire [ 7:0] tsdata_in,
|
||||
output wire [ 7:0] vplex_out
|
||||
|
||||
);
|
||||
|
||||
localparam R_ZX = 2'h0;
|
||||
@ -74,12 +74,11 @@ module video_render (
|
||||
wire gfx_visible = (pixv[render_mode] && !nogfx);
|
||||
wire [7:0] video1 = tsu_visible ? tsdata_in : (nogfx ? border_in : pix[render_mode]);
|
||||
wire [7:0] video2 = gfx_visible ? pix[render_mode] : (tsu_visible ? tsdata_in : border_in);
|
||||
wire [7:0] video = !hvpix ? border_in : (gfxovr ? video2 : video1);
|
||||
wire [7:0] video = hvpix ? (gfxovr ? video2 : video1) : ((hvtspix && tsu_visible) ? tsdata_in : border_in);
|
||||
assign vplex_out = hires ? {temp, video[3:0]} : video; // in hi-res plex contains two pixels 4 bits each
|
||||
|
||||
reg [3:0] temp;
|
||||
always @(posedge clk) if (c1)
|
||||
temp <= video[3:0];
|
||||
always @(posedge clk) if (c1) temp <= video[3:0];
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
@ -2,8 +2,8 @@
|
||||
// This module generates all video raster signals
|
||||
|
||||
|
||||
module video_sync (
|
||||
|
||||
module video_sync
|
||||
(
|
||||
// clocks
|
||||
input wire clk, f1, c0, c1, c3, pix_stb,
|
||||
|
||||
@ -12,6 +12,10 @@ module video_sync (
|
||||
input wire [8:0] hpix_end,
|
||||
input wire [8:0] vpix_beg,
|
||||
input wire [8:0] vpix_end,
|
||||
input wire [8:0] hpix_beg_ts,
|
||||
input wire [8:0] hpix_end_ts,
|
||||
input wire [8:0] vpix_beg_ts,
|
||||
input wire [8:0] vpix_end_ts,
|
||||
input wire [4:0] go_offs,
|
||||
input wire [1:0] x_offs,
|
||||
input wire [7:0] hint_beg,
|
||||
@ -35,6 +39,7 @@ module video_sync (
|
||||
output wire vpix,
|
||||
output wire v_ts,
|
||||
output wire hvpix,
|
||||
output wire hvtspix,
|
||||
output wire tv_hblank,
|
||||
output wire tv_vblank,
|
||||
output reg vga_hblank,
|
||||
@ -64,7 +69,6 @@ module video_sync (
|
||||
// ZX controls
|
||||
input wire y_offs_wr,
|
||||
output wire int_start
|
||||
|
||||
);
|
||||
|
||||
localparam HSYNC_BEG = 9'd11;
|
||||
@ -100,78 +104,61 @@ module video_sync (
|
||||
reg [8:0] cnt_out = 0;
|
||||
|
||||
// horizontal TV (7 MHz)
|
||||
always @(posedge clk) if (c3)
|
||||
hcount <= line_start ? 9'b0 : hcount + 9'b1;
|
||||
always @(posedge clk) if (c3) hcount <= line_start ? 9'b0 : hcount + 9'b1;
|
||||
|
||||
// vertical TV (15.625 kHz)
|
||||
always @(posedge clk) if (line_start_s)
|
||||
vcount <= (vcount == (vperiod - 1)) ? 9'b0 : vcount + 9'b1;
|
||||
always @(posedge clk) if (line_start_s) vcount <= (vcount == (vperiod - 1)) ? 9'b0 : vcount + 9'b1;
|
||||
|
||||
// horizontal VGA (14MHz)
|
||||
always @(posedge clk) if (f1)
|
||||
cnt_out <= vga_pix_start && c3 ? 9'b0 : cnt_out + 9'b1;
|
||||
always @(posedge clk) if (f1) cnt_out <= vga_pix_start && c3 ? 9'b0 : cnt_out + 9'b1;
|
||||
|
||||
// column address for DRAM
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (line_start2)
|
||||
begin
|
||||
always @(posedge clk) begin
|
||||
if (line_start2) begin
|
||||
cnt_col <= cstart;
|
||||
cptr <= 1'b0;
|
||||
end
|
||||
|
||||
else
|
||||
if (video_pre_next)
|
||||
begin
|
||||
else if (video_pre_next) begin
|
||||
cnt_col <= cnt_col + 8'b1;
|
||||
cptr <= ~cptr;
|
||||
end
|
||||
end
|
||||
|
||||
// row address for DRAM
|
||||
always @(posedge clk) if (c3)
|
||||
if (vis_start || (line_start && y_offs_wr_r))
|
||||
cnt_row <= rstart;
|
||||
else
|
||||
if (line_start && vpix)
|
||||
cnt_row <= cnt_row + 9'b1;
|
||||
|
||||
always @(posedge clk) begin if (c3)
|
||||
if (vis_start || (line_start && y_offs_wr_r)) cnt_row <= rstart;
|
||||
else if (line_start && vpix) cnt_row <= cnt_row + 9'b1;
|
||||
end
|
||||
|
||||
// pixel counter
|
||||
always @(posedge clk) if (pix_stb) // f1 or c3
|
||||
scnt <= pix_start ? 4'b0 : scnt + 4'b1;
|
||||
always @(posedge clk) if (pix_stb) scnt <= pix_start ? 4'b0 : scnt + 4'b1; // f1 or c3
|
||||
|
||||
assign vga_cnt_in = {vcount[0], hcount - HBLNK_END};
|
||||
assign vga_cnt_out = {~vcount[0], cnt_out};
|
||||
|
||||
|
||||
// TS-line counter
|
||||
assign ts_raddr = hcount - hpix_beg;
|
||||
|
||||
always @(posedge clk)
|
||||
if (ts_start_coarse)
|
||||
lcount <= vcount - vpix_beg + 9'b1;
|
||||
assign ts_raddr = hcount - hpix_beg_ts;
|
||||
|
||||
always @(posedge clk) if (ts_start_coarse) lcount <= vcount - vpix_beg_ts + 9'b1;
|
||||
|
||||
// Y offset re-latch trigger
|
||||
reg y_offs_wr_r;
|
||||
always @(posedge clk)
|
||||
if (y_offs_wr)
|
||||
y_offs_wr_r <= 1'b1;
|
||||
else
|
||||
if (line_start_s)
|
||||
y_offs_wr_r <= 1'b0;
|
||||
always @(posedge clk) begin
|
||||
if (y_offs_wr) y_offs_wr_r <= 1'b1;
|
||||
else if (line_start_s) y_offs_wr_r <= 1'b0;
|
||||
end
|
||||
|
||||
// FLASH generator
|
||||
reg [4:0] flash_ctr;
|
||||
assign frame = flash_ctr[0];
|
||||
assign flash = flash_ctr[4];
|
||||
always @(posedge clk)
|
||||
if (frame_start && c3)
|
||||
begin
|
||||
always @(posedge clk) begin
|
||||
if (frame_start && c3) begin
|
||||
v60hz <= !cfg_60hz; // re-sync of 60Hz mode selector
|
||||
flash_ctr <= flash_ctr + 5'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// sync strobes
|
||||
wire hs = (hcount >= HSYNC_BEG) && (hcount < HSYNC_END);
|
||||
@ -181,8 +168,7 @@ module video_sync (
|
||||
assign tv_vblank = (vcount >= vblnk_beg) && (vcount < vblnk_end);
|
||||
|
||||
wire vga_hblank1 = (cnt_out > 9'd359);
|
||||
always @(posedge clk) if (f1) // fix me - bydlocode !!!
|
||||
vga_hblank <= vga_hblank1;
|
||||
always @(posedge clk) if (f1) vga_hblank <= vga_hblank1;
|
||||
|
||||
wire hs_vga = ((hcount >= HSYNCV_BEG) && (hcount < HSYNCV_END)) ||
|
||||
((hcount >= (HSYNCV_BEG + HPERIOD/2)) && (hcount < (HSYNCV_END + HPERIOD/2)));
|
||||
@ -195,12 +181,16 @@ module video_sync (
|
||||
|
||||
assign hpix = (hcount >= hpix_beg) && (hcount < hpix_end);
|
||||
|
||||
assign vpix = (vcount >= vpix_beg) && (vcount < vpix_end); // vertical pixels window
|
||||
assign v_ts = (vcount >= (vpix_beg - 1)) && (vcount < (vpix_end - 1)); // vertical TS window
|
||||
assign v_pf = (vcount >= (vpix_beg - 17)) && (vcount < (vpix_end - 9)); // vertical tilemap prefetch window
|
||||
assign vpix = (vcount >= vpix_beg) && (vcount < vpix_end);
|
||||
|
||||
always @(posedge clk)
|
||||
video_go <= (hcount >= (hpix_beg - go_offs - x_offs)) && (hcount < (hpix_end - go_offs - x_offs + 4)) && vpix && !nogfx;
|
||||
assign hvtspix = htspix && vtspix;
|
||||
wire htspix = (hcount >= hpix_beg_ts) && (hcount < hpix_end_ts);
|
||||
wire vtspix = (vcount >= vpix_beg_ts) && (vcount < vpix_end_ts);
|
||||
|
||||
assign v_ts = (vcount >= (vpix_beg_ts - 1)) && (vcount < (vpix_end_ts - 1)); // vertical TS window
|
||||
assign v_pf = (vcount >= (vpix_beg_ts - 17)) && (vcount < (vpix_end_ts - 9)); // vertical tilemap prefetch window
|
||||
|
||||
always @(posedge clk) video_go <= (hcount >= (hpix_beg - go_offs - x_offs)) && (hcount < (hpix_end - go_offs - x_offs + 4)) && vpix && !nogfx;
|
||||
|
||||
wire line_start = hcount == (HPERIOD - 1);
|
||||
assign line_start_s = line_start && c3;
|
||||
@ -208,21 +198,16 @@ module video_sync (
|
||||
assign frame_start = line_start && (vcount == (vperiod - 1));
|
||||
wire vis_start = line_start && (vcount == (vblnk_end - 1));
|
||||
assign pix_start = hcount == (hpix_beg - x_offs - 1);
|
||||
wire ts_start_coarse = hcount == (hpix_beg - 1);
|
||||
wire ts_start_coarse = hcount == (hpix_beg_ts - 1);
|
||||
assign ts_start = c3 && ts_start_coarse;
|
||||
assign int_start = (hcount == {hint_beg, 1'b0}) && (vcount == vint_beg) && c0;
|
||||
|
||||
always @(posedge clk) if (line_start_s) vga_vblank <= tv_vblank;
|
||||
|
||||
always @(posedge clk) if (line_start_s) // fix me - bydlocode !!!
|
||||
vga_vblank <= tv_vblank;
|
||||
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
always @(posedge clk) begin
|
||||
hsync <= sync_pol ^ (vga_on ? hs_vga : hs);
|
||||
vsync <= sync_pol ^ vs;
|
||||
csync <= ~(vs ^ hs);
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
@ -15,6 +15,7 @@ module video_top
|
||||
output wire [7:0] vred,
|
||||
output wire [7:0] vgrn,
|
||||
output wire [7:0] vblu,
|
||||
output wire vdac_mode,
|
||||
|
||||
// video syncs
|
||||
output wire hsync,
|
||||
@ -25,7 +26,6 @@ module video_top
|
||||
output wire pix_stb,
|
||||
|
||||
// Z80 controls
|
||||
input wire [15:0] a,
|
||||
input wire [ 7:0] d,
|
||||
input wire [15:0] zmd,
|
||||
input wire [ 7:0] zma,
|
||||
@ -74,10 +74,8 @@ module video_top
|
||||
input wire video_pre_next,
|
||||
input wire next_video,
|
||||
input wire video_strobe,
|
||||
input wire video_next_strobe,
|
||||
output wire [20:0] ts_addr,
|
||||
output wire ts_req,
|
||||
output wire ts_z80_lp,
|
||||
input wire ts_pre_next,
|
||||
input wire ts_next,
|
||||
output wire [20:0] tm_addr,
|
||||
@ -87,14 +85,10 @@ module video_top
|
||||
// video controls
|
||||
input wire cfg_60hz,
|
||||
input wire sync_pol,
|
||||
input wire vga_on,
|
||||
|
||||
output wire [3:0] tst
|
||||
input wire vga_on
|
||||
);
|
||||
|
||||
|
||||
assign ts_z80_lp = tsconf[4];
|
||||
|
||||
// video config
|
||||
wire [7:0] vpage; // re-latched at line_start
|
||||
wire [7:0] vconf; //
|
||||
@ -116,6 +110,10 @@ wire [8:0] hpix_beg;
|
||||
wire [8:0] hpix_end;
|
||||
wire [8:0] vpix_beg;
|
||||
wire [8:0] vpix_end;
|
||||
wire [8:0] hpix_beg_ts;
|
||||
wire [8:0] hpix_end_ts;
|
||||
wire [8:0] vpix_beg_ts;
|
||||
wire [8:0] vpix_end_ts;
|
||||
wire [5:0] x_tiles;
|
||||
wire [9:0] x_offs_mode;
|
||||
wire [4:0] go_offs;
|
||||
@ -123,12 +121,9 @@ wire [1:0] render_mode;
|
||||
wire tv_hires;
|
||||
wire vga_hires;
|
||||
wire v60hz;
|
||||
//===zx-evo-fpga-564db5e984ef ===
|
||||
wire nogfx = vconf[5];
|
||||
wire notsu = vconf[4];
|
||||
wire gfxovr = vconf[3];
|
||||
//wire gfxovr;
|
||||
//===============================
|
||||
wire tv_hblank;
|
||||
wire tv_vblank;
|
||||
wire vga_hblank;
|
||||
@ -142,6 +137,7 @@ wire [3:0] scnt;
|
||||
wire [8:0] lcount;
|
||||
|
||||
// synchro
|
||||
wire frame_start;
|
||||
wire pix_start;
|
||||
wire tv_pix_start;
|
||||
wire vga_pix_start;
|
||||
@ -151,6 +147,7 @@ wire v_pf;
|
||||
wire hpix;
|
||||
wire vpix;
|
||||
wire hvpix;
|
||||
wire hvtspix;
|
||||
wire flash;
|
||||
|
||||
// fetcher
|
||||
@ -177,9 +174,6 @@ wire [3:0] tsr_pal;
|
||||
wire tsr_rdy;
|
||||
|
||||
// TS-line
|
||||
// wire [8:0] ts_waddr = a[8:0];
|
||||
// wire [7:0] ts_wdata = {d[7:1], 1'b1};
|
||||
// wire ts_we = c3;
|
||||
wire [8:0] ts_waddr;
|
||||
wire [7:0] ts_wdata;
|
||||
wire ts_we;
|
||||
@ -189,7 +183,8 @@ wire [8:0] ts_raddr;
|
||||
wire [9:0] vga_cnt_in;
|
||||
wire [9:0] vga_cnt_out;
|
||||
|
||||
video_ports video_ports (
|
||||
video_ports video_ports
|
||||
(
|
||||
.clk (clk),
|
||||
.d (d),
|
||||
.res (res),
|
||||
@ -232,6 +227,7 @@ video_ports video_ports (
|
||||
.palsel (palsel),
|
||||
.hint_beg (hint_beg),
|
||||
.vint_beg (vint_beg),
|
||||
.int_start (0),
|
||||
.tsconf (tsconf),
|
||||
.tmpage (tmpage),
|
||||
.t0gpage (t0gpage),
|
||||
@ -240,7 +236,8 @@ video_ports video_ports (
|
||||
);
|
||||
|
||||
|
||||
video_mode video_mode (
|
||||
video_mode video_mode
|
||||
(
|
||||
.clk (clk),
|
||||
.f1 (f1),
|
||||
.c3 (c3),
|
||||
@ -254,10 +251,15 @@ video_mode video_mode (
|
||||
.txt_char (fetch_temp[15:0]),
|
||||
.gx_offs (gx_offs),
|
||||
.x_offs_mode (x_offs_mode),
|
||||
.ts_rres_ext (tsconf[0]),
|
||||
.hpix_beg (hpix_beg),
|
||||
.hpix_end (hpix_end),
|
||||
.vpix_beg (vpix_beg),
|
||||
.vpix_end (vpix_end),
|
||||
.hpix_beg_ts (hpix_beg_ts),
|
||||
.hpix_end_ts (hpix_end_ts),
|
||||
.vpix_beg_ts (vpix_beg_ts),
|
||||
.vpix_end_ts (vpix_end_ts),
|
||||
.x_tiles (x_tiles),
|
||||
.go_offs (go_offs),
|
||||
.cnt_col (cnt_col),
|
||||
@ -274,7 +276,8 @@ video_mode video_mode (
|
||||
);
|
||||
|
||||
|
||||
video_sync video_sync (
|
||||
video_sync video_sync
|
||||
(
|
||||
.clk (clk),
|
||||
.f1 (f1),
|
||||
.c0 (c0),
|
||||
@ -284,6 +287,10 @@ video_sync video_sync (
|
||||
.hpix_end (hpix_end),
|
||||
.vpix_beg (vpix_beg),
|
||||
.vpix_end (vpix_end),
|
||||
.hpix_beg_ts (hpix_beg_ts),
|
||||
.hpix_end_ts (hpix_end_ts),
|
||||
.vpix_beg_ts (vpix_beg_ts),
|
||||
.vpix_end_ts (vpix_end_ts),
|
||||
.go_offs (go_offs),
|
||||
.x_offs (x_offs_mode[1:0]),
|
||||
.y_offs_wr (gy_offsl_wr || gy_offsh_wr),
|
||||
@ -311,12 +318,14 @@ video_sync video_sync (
|
||||
.ts_start (ts_start),
|
||||
.cstart (x_offs_mode[9:2]),
|
||||
.rstart (gy_offs),
|
||||
.frame_start (frame_start),
|
||||
.int_start (int_start),
|
||||
.v_pf (v_pf),
|
||||
.hpix (hpix),
|
||||
.v_ts (v_ts),
|
||||
.vpix (vpix),
|
||||
.hvpix (hvpix),
|
||||
.hvtspix (hvtspix),
|
||||
.nogfx (nogfx),
|
||||
.cfg_60hz (cfg_60hz),
|
||||
.sync_pol (sync_pol),
|
||||
@ -327,7 +336,8 @@ video_sync video_sync (
|
||||
);
|
||||
|
||||
|
||||
video_fetch video_fetch (
|
||||
video_fetch video_fetch
|
||||
(
|
||||
.clk (clk),
|
||||
.f_sel (fetch_sel),
|
||||
.b_sel (fetch_bsl),
|
||||
@ -338,7 +348,8 @@ video_fetch video_fetch (
|
||||
.video_data (dram_rdata)
|
||||
);
|
||||
|
||||
video_ts video_ts (
|
||||
video_ts video_ts
|
||||
(
|
||||
.clk (clk),
|
||||
.start (ts_start),
|
||||
.line (lcount),
|
||||
@ -378,8 +389,8 @@ video_ts video_ts (
|
||||
.sfile_we (sfile_we)
|
||||
);
|
||||
|
||||
|
||||
video_ts_render video_ts_render (
|
||||
video_ts_render video_ts_render
|
||||
(
|
||||
.clk (clk),
|
||||
|
||||
.reset (ts_start),
|
||||
@ -406,10 +417,12 @@ video_ts_render video_ts_render (
|
||||
);
|
||||
|
||||
|
||||
video_render video_render (
|
||||
video_render video_render
|
||||
(
|
||||
.clk (clk),
|
||||
.c1 (c1),
|
||||
.hvpix (hvpix),
|
||||
.hvtspix (hvtspix),
|
||||
.nogfx (nogfx),
|
||||
.notsu (notsu),
|
||||
.gfxovr (gfxovr),
|
||||
@ -424,7 +437,8 @@ video_render video_render (
|
||||
.vplex_out (vplex)
|
||||
);
|
||||
|
||||
video_out video_out (
|
||||
video_out video_out
|
||||
(
|
||||
.clk (clk),
|
||||
.f0 (f0),
|
||||
.c3 (c3),
|
||||
@ -436,14 +450,14 @@ video_out video_out (
|
||||
.tv_hires (tv_hires),
|
||||
.vga_hires (vga_hires),
|
||||
.cram_addr_in (zma),
|
||||
.cram_data_in (zmd[14:0]),
|
||||
.cram_data_in (zmd[15:0]),
|
||||
.cram_we (cram_we),
|
||||
.vplex_in (vplex),
|
||||
.vgaplex (vgaplex),
|
||||
.vred (vred),
|
||||
.vgrn (vgrn),
|
||||
.vblu (vblu),
|
||||
.tst (tst)
|
||||
.vdac_mode (vdac_mode)
|
||||
);
|
||||
|
||||
assign hblank = vga_on ? vga_hblank : tv_hblank;
|
||||
|
||||
@ -59,9 +59,7 @@ module video_ts
|
||||
output wire [20:0] dram_addr,
|
||||
output wire dram_req,
|
||||
input wire dram_next,
|
||||
input wire [15:0] dram_rdata,
|
||||
|
||||
output wire [2:0] tst
|
||||
input wire [15:0] dram_rdata
|
||||
);
|
||||
|
||||
|
||||
@ -86,26 +84,6 @@ module video_ts
|
||||
|
||||
// Layer selectors control
|
||||
|
||||
// DEBUG !!!
|
||||
assign tst = lyr;
|
||||
reg [2:0] lyr;
|
||||
always@*
|
||||
// if (layer_active[S0])
|
||||
// lyr = 2;
|
||||
// else if (layer_active[S1])
|
||||
// lyr = 6;
|
||||
// else if (layer_active[S2])
|
||||
// lyr = 4;
|
||||
// else if (layer_active[TM])
|
||||
// lyr = 1;
|
||||
// else if (layer_active[T0])
|
||||
// lyr = 3;
|
||||
// else if (layer_active[T1])
|
||||
// lyr = 5;
|
||||
// else lyr = 0;
|
||||
lyr = 0;
|
||||
// lyr = sr_valid;
|
||||
|
||||
localparam LAYERS = 6; // Total number of layers to process
|
||||
localparam TM = 0; // Individual layers
|
||||
localparam S0 = 1;
|
||||
@ -349,8 +327,7 @@ module video_ts
|
||||
reg [5:0] s_bmline_offset_r;
|
||||
reg s_leap_r;
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
always @(posedge clk) begin
|
||||
if (sr0_valid)
|
||||
begin
|
||||
s_leap_r <= s_leap;
|
||||
|
||||
@ -15,8 +15,8 @@
|
||||
// after TS request recognized and processed by DRAM controller.
|
||||
// It is recommended to assert 'tsr_go' at 'c2'.
|
||||
|
||||
module video_ts_render (
|
||||
|
||||
module video_ts_render
|
||||
(
|
||||
// clocks
|
||||
input wire clk,
|
||||
|
||||
@ -45,7 +45,6 @@ module video_ts_render (
|
||||
input wire [15:0] dram_rdata,
|
||||
input wire dram_pre_next,
|
||||
input wire dram_next
|
||||
|
||||
);
|
||||
|
||||
|
||||
@ -61,8 +60,7 @@ module video_ts_render (
|
||||
// as renderer can't move outside the single bitmap line, only 7 bits are processed
|
||||
|
||||
reg [20:0] addr_reg;
|
||||
always @(posedge clk)
|
||||
addr_reg <= dram_addr;
|
||||
always @(posedge clk) addr_reg <= dram_addr;
|
||||
|
||||
|
||||
// DRAM cycles counter
|
||||
@ -80,9 +78,7 @@ module video_ts_render (
|
||||
|
||||
// DRAM data fetching
|
||||
reg [15:0] data;
|
||||
always @(posedge clk)
|
||||
if (dram_next)
|
||||
data <= dram_rdata;
|
||||
always @(posedge clk) if (dram_next) data <= dram_rdata;
|
||||
|
||||
|
||||
// pixel render counter
|
||||
@ -128,8 +124,7 @@ module video_ts_render (
|
||||
wire [8:0] x_next = ts_waddr + {{8{flip_r}}, 1'b1};
|
||||
wire tsr_rld_stb = tsr_rld && dram_next;
|
||||
|
||||
always @(posedge clk)
|
||||
ts_waddr <= ts_waddr_mx;
|
||||
always @(posedge clk) ts_waddr <= ts_waddr_mx;
|
||||
|
||||
reg [3:0] pal_r;
|
||||
reg flip_r;
|
||||
|
||||
Reference in New Issue
Block a user