mirror of
https://github.com/UzixLS/TSConf_MiST.git
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85 lines
2.3 KiB
Verilog
85 lines
2.3 KiB
Verilog
// This module renders video data for output
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module video_render
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(
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// clocks
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input wire clk, c1,
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// video controls
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input wire hvpix,
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input wire hvtspix,
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input wire nogfx,
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input wire notsu,
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input wire gfxovr,
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input wire flash,
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input wire hires,
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input wire [3:0] psel,
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input wire [3:0] palsel,
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// mode controls
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input wire [1:0] render_mode,
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// video data
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input wire [31:0] data,
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input wire [ 7:0] border_in,
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input wire [ 7:0] tsdata_in,
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output wire [ 7:0] vplex_out
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);
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localparam R_ZX = 2'h0;
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localparam R_HC = 2'h1;
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localparam R_XC = 2'h2;
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localparam R_TX = 2'h3;
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// ZX graphics
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wire [15:0] zx_gfx = data[15: 0];
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wire [15:0] zx_atr = data[31:16];
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wire zx_dot = zx_gfx[{psel[3], ~psel[2:0]}];
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wire [7:0] zx_attr = ~psel[3] ? zx_atr[7:0] : zx_atr[15:8];
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wire [7:0] zx_pix = {palsel, zx_attr[6], zx_dot ^ (flash & zx_attr[7]) ? zx_attr[2:0] : zx_attr[5:3]};
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// text graphics
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// (it uses common renderer with ZX, but different attributes)
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wire [7:0] tx_pix = {palsel, zx_dot ? zx_attr[3:0] : zx_attr[7:4]};
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// 16c graphics
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wire [3:0] hc_dot[0:3];
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assign hc_dot[0] = data[ 7: 4];
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assign hc_dot[1] = data[ 3: 0];
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assign hc_dot[2] = data[15:12];
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assign hc_dot[3] = data[11: 8];
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wire [7:0] hc_pix = {palsel, hc_dot[psel[1:0]]};
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// 256c graphics
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wire [7:0] xc_dot[0:1];
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assign xc_dot[0] = data[ 7: 0];
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assign xc_dot[1] = data[15: 8];
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wire [7:0] xc_pix = xc_dot[psel[0]];
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// mode selects
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wire [7:0] pix[0:3];
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assign pix[R_ZX] = zx_pix; // ZX
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assign pix[R_HC] = hc_pix; // 16c
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assign pix[R_XC] = xc_pix; // 256c
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assign pix[R_TX] = tx_pix; // text
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wire pixv[0:3];
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assign pixv[R_ZX] = zx_dot ^ (flash & zx_attr[7]);
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assign pixv[R_HC] = |hc_dot[psel[1:0]];
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assign pixv[R_XC] = |xc_dot[psel[0]];
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assign pixv[R_TX] = zx_dot;
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// video plex muxer
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wire tsu_visible = (|tsdata_in[3:0] && !notsu);
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wire gfx_visible = (pixv[render_mode] && !nogfx);
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wire [7:0] video1 = tsu_visible ? tsdata_in : (nogfx ? border_in : pix[render_mode]);
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wire [7:0] video2 = gfx_visible ? pix[render_mode] : (tsu_visible ? tsdata_in : border_in);
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wire [7:0] video = hvpix ? (gfxovr ? video2 : video1) : ((hvtspix && tsu_visible) ? tsdata_in : border_in);
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assign vplex_out = hires ? {temp, video[3:0]} : video; // in hi-res plex contains two pixels 4 bits each
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reg [3:0] temp;
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always @(posedge clk) if (c1) temp <= video[3:0];
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endmodule
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