mirror of
https://github.com/UzixLS/TSConf_MiST.git
synced 2025-07-18 23:01:37 +03:00
Remove redundant modules.
This commit is contained in:
@ -367,8 +367,6 @@ set_global_assignment -name VERILOG_FILE src/cpu/zmem.v
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set_global_assignment -name VERILOG_FILE src/cpu/zmaps.v
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set_global_assignment -name VERILOG_FILE src/cpu/zmaps.v
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set_global_assignment -name VERILOG_FILE src/cpu/zint.v
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set_global_assignment -name VERILOG_FILE src/cpu/zint.v
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set_global_assignment -name VERILOG_FILE src/cpu/zclock.v
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set_global_assignment -name VERILOG_FILE src/cpu/zclock.v
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set_global_assignment -name VERILOG_FILE src/cpu/cache_data.v
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set_global_assignment -name VERILOG_FILE src/cpu/cache_addr.v
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set_global_assignment -name VHDL_FILE src/rtc/CMOS.vhd
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set_global_assignment -name VHDL_FILE src/rtc/CMOS.vhd
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set_global_assignment -name VHDL_FILE src/rtc/mc146818a.vhd
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set_global_assignment -name VHDL_FILE src/rtc/mc146818a.vhd
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set_global_assignment -name VHDL_FILE src/sound/soundrive.vhd
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set_global_assignment -name VHDL_FILE src/sound/soundrive.vhd
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@ -389,12 +387,6 @@ set_global_assignment -name VERILOG_FILE src/video/video_ports.v
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set_global_assignment -name VERILOG_FILE src/video/video_out.v
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set_global_assignment -name VERILOG_FILE src/video/video_out.v
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set_global_assignment -name VERILOG_FILE src/video/video_mode.v
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set_global_assignment -name VERILOG_FILE src/video/video_mode.v
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set_global_assignment -name VERILOG_FILE src/video/video_fetch.v
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set_global_assignment -name VERILOG_FILE src/video/video_fetch.v
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set_global_assignment -name VERILOG_FILE src/video/mem/video_vmem.v
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set_global_assignment -name VERILOG_FILE src/video/mem/video_tsline1.v
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set_global_assignment -name VERILOG_FILE src/video/mem/video_tsline0.v
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set_global_assignment -name VERILOG_FILE src/video/mem/video_tmbuf.v
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set_global_assignment -name VERILOG_FILE src/video/mem/video_sfile.v
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set_global_assignment -name VERILOG_FILE src/video/mem/video_cram.v
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set_global_assignment -name VERILOG_FILE src/video/video_top.v
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set_global_assignment -name VERILOG_FILE src/video/video_top.v
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set_global_assignment -name VHDL_FILE src/keyboard.vhd
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set_global_assignment -name VHDL_FILE src/keyboard.vhd
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set_global_assignment -name VERILOG_FILE src/kempston_mouse.v
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set_global_assignment -name VERILOG_FILE src/kempston_mouse.v
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@ -1,222 +0,0 @@
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// megafunction wizard: %RAM: 2-PORT%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altsyncram
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// ============================================================
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// File Name: cache_addr.v
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// Megafunction Name(s):
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// altsyncram
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 10.1 Build 153 11/29/2010 SJ Full Version
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// ************************************************************
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//Copyright (C) 1991-2010 Altera Corporation
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
|
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//functions, and any output files from any of the foregoing
|
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//(including device programming or simulation files), and any
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||||||
//associated documentation or information are expressly subject
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||||||
//to the terms and conditions of the Altera Program License
|
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||||||
//Subscription Agreement, Altera MegaCore Function License
|
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||||||
//Agreement, or other applicable license agreement, including,
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||||||
//without limitation, that your use is for the sole purpose of
|
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||||||
//programming logic devices manufactured by Altera and sold by
|
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||||||
//Altera or its authorized distributors. Please refer to the
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//applicable agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module cache_addr (
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clock,
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data,
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rdaddress,
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wraddress,
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wren,
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q);
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input clock;
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input [15:0] data;
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input [8:0] rdaddress;
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input [8:0] wraddress;
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input wren;
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output [15:0] q;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri1 clock;
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tri0 wren;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [15:0] sub_wire0;
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wire [15:0] q = sub_wire0[15:0];
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altsyncram altsyncram_component (
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.address_a (wraddress),
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.clock0 (clock),
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.data_a (data),
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.wren_a (wren),
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.address_b (rdaddress),
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.q_b (sub_wire0),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clock1 (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_b ({16{1'b1}}),
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.eccstatus (),
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.q_a (),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.wren_b (1'b0));
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defparam
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altsyncram_component.address_aclr_b = "NONE",
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altsyncram_component.address_reg_b = "CLOCK0",
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_input_b = "BYPASS",
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altsyncram_component.clock_enable_output_b = "BYPASS",
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altsyncram_component.intended_device_family = "Cyclone IV E",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = 512,
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altsyncram_component.numwords_b = 512,
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altsyncram_component.operation_mode = "DUAL_PORT",
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altsyncram_component.outdata_aclr_b = "NONE",
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altsyncram_component.outdata_reg_b = "UNREGISTERED",
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altsyncram_component.power_up_uninitialized = "FALSE",
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altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
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altsyncram_component.widthad_a = 9,
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altsyncram_component.widthad_b = 9,
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altsyncram_component.width_a = 16,
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altsyncram_component.width_b = 16,
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altsyncram_component.width_byteena_a = 1;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
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// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
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// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
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// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
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// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
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// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
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// Retrieval info: PRIVATE: CLRq NUMERIC "0"
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// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
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// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
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// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
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// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
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// Retrieval info: PRIVATE: Clock NUMERIC "0"
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// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
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// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
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// Retrieval info: PRIVATE: ECC NUMERIC "0"
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// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
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// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
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// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
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// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
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// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
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// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
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// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
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// Retrieval info: PRIVATE: MIFfilename STRING "./core_TSLab/video/mem/video_cram.mif"
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// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
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// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
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// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
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// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
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// Retrieval info: PRIVATE: REGdata NUMERIC "1"
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// Retrieval info: PRIVATE: REGq NUMERIC "0"
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// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
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// Retrieval info: PRIVATE: REGrren NUMERIC "1"
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// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
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// Retrieval info: PRIVATE: REGwren NUMERIC "1"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
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// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
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// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
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// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
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// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
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// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
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// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
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// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
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// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: enable NUMERIC "0"
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// Retrieval info: PRIVATE: rden NUMERIC "0"
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
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// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
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// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
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// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
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// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
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// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
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// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
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// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
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// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
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// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
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// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
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// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
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// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
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// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
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// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
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// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
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// Retrieval info: USED_PORT: rdaddress 0 0 9 0 INPUT NODEFVAL "rdaddress[8..0]"
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// Retrieval info: USED_PORT: wraddress 0 0 9 0 INPUT NODEFVAL "wraddress[8..0]"
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// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
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// Retrieval info: CONNECT: @address_a 0 0 9 0 wraddress 0 0 9 0
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||||||
// Retrieval info: CONNECT: @address_b 0 0 9 0 rdaddress 0 0 9 0
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||||||
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
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||||||
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
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||||||
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
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||||||
// Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0
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||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_cram.v TRUE
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||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_cram.inc FALSE
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||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_cram.cmp FALSE
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|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_cram.bsf FALSE
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||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_cram_inst.v FALSE
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|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_cram_bb.v FALSE
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|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_cram_waveforms.html FALSE
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|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_cram_wave*.jpg FALSE
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|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL cache_addr.v TRUE
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|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL cache_addr.inc FALSE
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|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL cache_addr.cmp FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL cache_addr.bsf FALSE
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|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL cache_addr_inst.v FALSE
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|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL cache_addr_bb.v TRUE
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|
||||||
// Retrieval info: LIB_FILE: altera_mf
|
|
@ -1,222 +0,0 @@
|
|||||||
// megafunction wizard: %RAM: 2-PORT%
|
|
||||||
// GENERATION: STANDARD
|
|
||||||
// VERSION: WM1.0
|
|
||||||
// MODULE: altsyncram
|
|
||||||
|
|
||||||
// ============================================================
|
|
||||||
// File Name: cache_data.v
|
|
||||||
// Megafunction Name(s):
|
|
||||||
// altsyncram
|
|
||||||
//
|
|
||||||
// Simulation Library Files(s):
|
|
||||||
// altera_mf
|
|
||||||
// ============================================================
|
|
||||||
// ************************************************************
|
|
||||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
|
||||||
//
|
|
||||||
// 10.1 Build 153 11/29/2010 SJ Full Version
|
|
||||||
// ************************************************************
|
|
||||||
|
|
||||||
|
|
||||||
//Copyright (C) 1991-2010 Altera Corporation
|
|
||||||
//Your use of Altera Corporation's design tools, logic functions
|
|
||||||
//and other software and tools, and its AMPP partner logic
|
|
||||||
//functions, and any output files from any of the foregoing
|
|
||||||
//(including device programming or simulation files), and any
|
|
||||||
//associated documentation or information are expressly subject
|
|
||||||
//to the terms and conditions of the Altera Program License
|
|
||||||
//Subscription Agreement, Altera MegaCore Function License
|
|
||||||
//Agreement, or other applicable license agreement, including,
|
|
||||||
//without limitation, that your use is for the sole purpose of
|
|
||||||
//programming logic devices manufactured by Altera and sold by
|
|
||||||
//Altera or its authorized distributors. Please refer to the
|
|
||||||
//applicable agreement for further details.
|
|
||||||
|
|
||||||
|
|
||||||
// synopsys translate_off
|
|
||||||
`timescale 1 ps / 1 ps
|
|
||||||
// synopsys translate_on
|
|
||||||
module cache_data (
|
|
||||||
clock,
|
|
||||||
data,
|
|
||||||
rdaddress,
|
|
||||||
wraddress,
|
|
||||||
wren,
|
|
||||||
q);
|
|
||||||
|
|
||||||
input clock;
|
|
||||||
input [15:0] data;
|
|
||||||
input [8:0] rdaddress;
|
|
||||||
input [8:0] wraddress;
|
|
||||||
input wren;
|
|
||||||
output [15:0] q;
|
|
||||||
`ifndef ALTERA_RESERVED_QIS
|
|
||||||
// synopsys translate_off
|
|
||||||
`endif
|
|
||||||
tri1 clock;
|
|
||||||
tri0 wren;
|
|
||||||
`ifndef ALTERA_RESERVED_QIS
|
|
||||||
// synopsys translate_on
|
|
||||||
`endif
|
|
||||||
|
|
||||||
wire [15:0] sub_wire0;
|
|
||||||
wire [15:0] q = sub_wire0[15:0];
|
|
||||||
|
|
||||||
altsyncram altsyncram_component (
|
|
||||||
.address_a (wraddress),
|
|
||||||
.clock0 (clock),
|
|
||||||
.data_a (data),
|
|
||||||
.wren_a (wren),
|
|
||||||
.address_b (rdaddress),
|
|
||||||
.q_b (sub_wire0),
|
|
||||||
.aclr0 (1'b0),
|
|
||||||
.aclr1 (1'b0),
|
|
||||||
.addressstall_a (1'b0),
|
|
||||||
.addressstall_b (1'b0),
|
|
||||||
.byteena_a (1'b1),
|
|
||||||
.byteena_b (1'b1),
|
|
||||||
.clock1 (1'b1),
|
|
||||||
.clocken0 (1'b1),
|
|
||||||
.clocken1 (1'b1),
|
|
||||||
.clocken2 (1'b1),
|
|
||||||
.clocken3 (1'b1),
|
|
||||||
.data_b ({16{1'b1}}),
|
|
||||||
.eccstatus (),
|
|
||||||
.q_a (),
|
|
||||||
.rden_a (1'b1),
|
|
||||||
.rden_b (1'b1),
|
|
||||||
.wren_b (1'b0));
|
|
||||||
defparam
|
|
||||||
altsyncram_component.address_aclr_b = "NONE",
|
|
||||||
altsyncram_component.address_reg_b = "CLOCK0",
|
|
||||||
altsyncram_component.clock_enable_input_a = "BYPASS",
|
|
||||||
altsyncram_component.clock_enable_input_b = "BYPASS",
|
|
||||||
altsyncram_component.clock_enable_output_b = "BYPASS",
|
|
||||||
altsyncram_component.intended_device_family = "Cyclone IV E",
|
|
||||||
altsyncram_component.lpm_type = "altsyncram",
|
|
||||||
altsyncram_component.numwords_a = 512,
|
|
||||||
altsyncram_component.numwords_b = 512,
|
|
||||||
altsyncram_component.operation_mode = "DUAL_PORT",
|
|
||||||
altsyncram_component.outdata_aclr_b = "NONE",
|
|
||||||
altsyncram_component.outdata_reg_b = "UNREGISTERED",
|
|
||||||
altsyncram_component.power_up_uninitialized = "FALSE",
|
|
||||||
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
|
|
||||||
altsyncram_component.widthad_a = 9,
|
|
||||||
altsyncram_component.widthad_b = 9,
|
|
||||||
altsyncram_component.width_a = 16,
|
|
||||||
altsyncram_component.width_b = 16,
|
|
||||||
altsyncram_component.width_byteena_a = 1;
|
|
||||||
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
// ============================================================
|
|
||||||
// CNX file retrieval info
|
|
||||||
// ============================================================
|
|
||||||
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
|
||||||
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: Clock NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: ECC NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
|
|
||||||
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
|
||||||
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
|
||||||
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
|
|
||||||
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: MIFfilename STRING "./core_TSLab/video/mem/video_cram.mif"
|
|
||||||
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
|
|
||||||
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
|
|
||||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
|
|
||||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
|
|
||||||
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGq NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
|
||||||
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
|
|
||||||
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: enable NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: rden NUMERIC "0"
|
|
||||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
|
||||||
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
|
|
||||||
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
|
|
||||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
|
||||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
|
|
||||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
|
|
||||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
|
||||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
|
||||||
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
|
|
||||||
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
|
|
||||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
|
|
||||||
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
|
|
||||||
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
|
|
||||||
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
|
|
||||||
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
|
|
||||||
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
|
|
||||||
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
|
|
||||||
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
|
|
||||||
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
|
|
||||||
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
|
||||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
|
|
||||||
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
|
|
||||||
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
|
|
||||||
// Retrieval info: USED_PORT: rdaddress 0 0 9 0 INPUT NODEFVAL "rdaddress[8..0]"
|
|
||||||
// Retrieval info: USED_PORT: wraddress 0 0 9 0 INPUT NODEFVAL "wraddress[8..0]"
|
|
||||||
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
|
|
||||||
// Retrieval info: CONNECT: @address_a 0 0 9 0 wraddress 0 0 9 0
|
|
||||||
// Retrieval info: CONNECT: @address_b 0 0 9 0 rdaddress 0 0 9 0
|
|
||||||
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
|
|
||||||
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
|
|
||||||
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
|
|
||||||
// Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_cram.v TRUE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_cram.inc FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_cram.cmp FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_cram.bsf FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_cram_inst.v FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_cram_bb.v FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_cram_waveforms.html FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_cram_wave*.jpg FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL cache_data.v TRUE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL cache_data.inc FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL cache_data.cmp FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL cache_data.bsf FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL cache_data_inst.v FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL cache_data_bb.v TRUE
|
|
||||||
// Retrieval info: LIB_FILE: altera_mf
|
|
@ -277,24 +277,26 @@ module zmem(
|
|||||||
wire cache_v; //data valid
|
wire cache_v; //data valid
|
||||||
wire [1:0] cache_tmp; //empty 16bit: 2 cache_tmp + csvrom + 13cpu_hi_addr1
|
wire [1:0] cache_tmp; //empty 16bit: 2 cache_tmp + csvrom + 13cpu_hi_addr1
|
||||||
|
|
||||||
cache_data cache_data (
|
dpram #(.DATAWIDTH(16), .ADDRWIDTH(9)) cache_data
|
||||||
|
(
|
||||||
.clock (clk), // -- CLK
|
.clock (clk), // -- CLK
|
||||||
.rdaddress ({csvrom1, ch_addr1}), // ADDR for RD
|
.address_b ({csvrom1, ch_addr1}), // ADDR for RD
|
||||||
.wraddress (loader ? za[8:0] : cpu_strobe ? {csvrom2, ch_addr2} : {csvrom1, ch_addr1}),//WR
|
.address_a (loader ? za[8:0] : cpu_strobe ? {csvrom2, ch_addr2} : {csvrom1, ch_addr1}),//WR
|
||||||
//-----------------CACHE DATA -------------------------
|
//-----------------CACHE DATA -------------------------
|
||||||
.wren (loader ? 1'b1 : cpu_strobe), //c2 -strobe
|
.wren_a (loader ? 1'b1 : cpu_strobe), //c2 -strobe
|
||||||
.data (loader ? 16'b0 : cpu_rddata), //<=====
|
.data_a (loader ? 16'b0 : cpu_rddata), //<=====
|
||||||
.q (cache_d) // ==> data from CACHE
|
.q_b (cache_d) // ==> data from CACHE
|
||||||
);
|
);
|
||||||
|
|
||||||
cache_addr cache_addr (
|
dpram #(.DATAWIDTH(16), .ADDRWIDTH(9)) cache_addr
|
||||||
|
(
|
||||||
.clock (clk), //---- CLK
|
.clock (clk), //---- CLK
|
||||||
.rdaddress ({csvrom1, ch_addr1}), //
|
.address_b ({csvrom1, ch_addr1}), //
|
||||||
.wraddress (loader ? za[8:0] : cpu_strobe ? {csvrom2, ch_addr2} : {csvrom1, ch_addr1}), //WR
|
.address_a (loader ? za[8:0] : cpu_strobe ? {csvrom2, ch_addr2} : {csvrom1, ch_addr1}), //WR
|
||||||
//--------------arbiter.cpu_strobe <= curr_cpu && cpu_rnw_r;
|
//--------------arbiter.cpu_strobe <= curr_cpu && cpu_rnw_r;
|
||||||
.q ({cache_tmp, cache_v, cache_a}), // valid, addr from CACHE
|
.q_b ({cache_tmp, cache_v, cache_a}), // valid, addr from CACHE
|
||||||
.data (loader ? 16'b0 : cpu_strobe ? {cache_tmp, 1'b1, cpu_hi_addr2} : {2'b0, 1'b0, 8'b0}), //wrdata
|
.data_a (loader ? 16'b0 : cpu_strobe ? {cache_tmp, 1'b1, cpu_hi_addr2} : {2'b0, 1'b0, 8'b0}), //wrdata
|
||||||
.wren (loader ? 1'b1 : (cpu_strobe || cache_inv)) //c2 -strobe
|
.wren_a (loader ? 1'b1 : (cpu_strobe || cache_inv)) //c2 -strobe
|
||||||
);
|
);
|
||||||
//-----------
|
//-----------
|
||||||
wire cache_hit = (cpu_hi_addr1 == cache_a) && cache_v;
|
wire cache_hit = (cpu_hi_addr1 == cache_a) && cache_v;
|
||||||
@ -307,6 +309,4 @@ module zmem(
|
|||||||
wire cache_hit_en = (cache_hit && (cache_en[win] || csvrom)) ;
|
wire cache_hit_en = (cache_hit && (cache_en[win] || csvrom)) ;
|
||||||
wire cache_inv = ramwr_s && cache_hit; // cache invalidation should be only performed if write happens to cached address
|
wire cache_inv = ramwr_s && cache_hit; // cache invalidation should be only performed if write happens to cached address
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
@ -1,3 +0,0 @@
|
|||||||
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
|
|
||||||
set_global_assignment -name IP_TOOL_VERSION "11.0"
|
|
||||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "video_cram.v"]
|
|
@ -1,219 +0,0 @@
|
|||||||
// megafunction wizard: %RAM: 2-PORT%
|
|
||||||
// GENERATION: STANDARD
|
|
||||||
// VERSION: WM1.0
|
|
||||||
// MODULE: altsyncram
|
|
||||||
|
|
||||||
// ============================================================
|
|
||||||
// File Name: video_cram.v
|
|
||||||
// Megafunction Name(s):
|
|
||||||
// altsyncram
|
|
||||||
//
|
|
||||||
// Simulation Library Files(s):
|
|
||||||
// altera_mf
|
|
||||||
// ============================================================
|
|
||||||
// ************************************************************
|
|
||||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
|
||||||
//
|
|
||||||
// 11.0 Build 157 04/27/2011 SJ Full Version
|
|
||||||
// ************************************************************
|
|
||||||
|
|
||||||
|
|
||||||
//Copyright (C) 1991-2011 Altera Corporation
|
|
||||||
//Your use of Altera Corporation's design tools, logic functions
|
|
||||||
//and other software and tools, and its AMPP partner logic
|
|
||||||
//functions, and any output files from any of the foregoing
|
|
||||||
//(including device programming or simulation files), and any
|
|
||||||
//associated documentation or information are expressly subject
|
|
||||||
//to the terms and conditions of the Altera Program License
|
|
||||||
//Subscription Agreement, Altera MegaCore Function License
|
|
||||||
//Agreement, or other applicable license agreement, including,
|
|
||||||
//without limitation, that your use is for the sole purpose of
|
|
||||||
//programming logic devices manufactured by Altera and sold by
|
|
||||||
//Altera or its authorized distributors. Please refer to the
|
|
||||||
//applicable agreement for further details.
|
|
||||||
|
|
||||||
|
|
||||||
// synopsys translate_off
|
|
||||||
`timescale 1 ps / 1 ps
|
|
||||||
// synopsys translate_on
|
|
||||||
module video_cram (
|
|
||||||
clock,
|
|
||||||
data,
|
|
||||||
rdaddress,
|
|
||||||
wraddress,
|
|
||||||
wren,
|
|
||||||
q);
|
|
||||||
|
|
||||||
input clock;
|
|
||||||
input [14:0] data;
|
|
||||||
input [7:0] rdaddress;
|
|
||||||
input [7:0] wraddress;
|
|
||||||
input wren;
|
|
||||||
output [14:0] q;
|
|
||||||
`ifndef ALTERA_RESERVED_QIS
|
|
||||||
// synopsys translate_off
|
|
||||||
`endif
|
|
||||||
tri1 clock;
|
|
||||||
tri0 wren;
|
|
||||||
`ifndef ALTERA_RESERVED_QIS
|
|
||||||
// synopsys translate_on
|
|
||||||
`endif
|
|
||||||
|
|
||||||
wire [14:0] sub_wire0;
|
|
||||||
wire [14:0] q = sub_wire0[14:0];
|
|
||||||
|
|
||||||
altsyncram altsyncram_component (
|
|
||||||
.address_a (wraddress),
|
|
||||||
.clock0 (clock),
|
|
||||||
.data_a (data),
|
|
||||||
.wren_a (wren),
|
|
||||||
.address_b (rdaddress),
|
|
||||||
.q_b (sub_wire0),
|
|
||||||
.aclr0 (1'b0),
|
|
||||||
.aclr1 (1'b0),
|
|
||||||
.addressstall_a (1'b0),
|
|
||||||
.addressstall_b (1'b0),
|
|
||||||
.byteena_a (1'b1),
|
|
||||||
.byteena_b (1'b1),
|
|
||||||
.clock1 (1'b1),
|
|
||||||
.clocken0 (1'b1),
|
|
||||||
.clocken1 (1'b1),
|
|
||||||
.clocken2 (1'b1),
|
|
||||||
.clocken3 (1'b1),
|
|
||||||
.data_b ({15{1'b1}}),
|
|
||||||
.eccstatus (),
|
|
||||||
.q_a (),
|
|
||||||
.rden_a (1'b1),
|
|
||||||
.rden_b (1'b1),
|
|
||||||
.wren_b (1'b0));
|
|
||||||
defparam
|
|
||||||
altsyncram_component.address_aclr_b = "NONE",
|
|
||||||
altsyncram_component.address_reg_b = "CLOCK0",
|
|
||||||
altsyncram_component.clock_enable_input_a = "BYPASS",
|
|
||||||
altsyncram_component.clock_enable_input_b = "BYPASS",
|
|
||||||
altsyncram_component.clock_enable_output_b = "BYPASS",
|
|
||||||
altsyncram_component.init_file = "src/video/mem/video_cram.mif",
|
|
||||||
altsyncram_component.intended_device_family = "Cyclone IV E",
|
|
||||||
altsyncram_component.lpm_type = "altsyncram",
|
|
||||||
altsyncram_component.numwords_a = 256,
|
|
||||||
altsyncram_component.numwords_b = 256,
|
|
||||||
altsyncram_component.operation_mode = "DUAL_PORT",
|
|
||||||
altsyncram_component.outdata_aclr_b = "NONE",
|
|
||||||
altsyncram_component.outdata_reg_b = "UNREGISTERED",
|
|
||||||
altsyncram_component.power_up_uninitialized = "FALSE",
|
|
||||||
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
|
|
||||||
altsyncram_component.widthad_a = 8,
|
|
||||||
altsyncram_component.widthad_b = 8,
|
|
||||||
altsyncram_component.width_a = 15,
|
|
||||||
altsyncram_component.width_b = 15,
|
|
||||||
altsyncram_component.width_byteena_a = 1;
|
|
||||||
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
// ============================================================
|
|
||||||
// CNX file retrieval info
|
|
||||||
// ============================================================
|
|
||||||
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
|
||||||
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: Clock NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: ECC NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
|
|
||||||
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
|
||||||
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
|
||||||
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "3840"
|
|
||||||
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: MIFfilename STRING "../rtl/ts/video/mem/video_cram.mif"
|
|
||||||
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
|
|
||||||
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
|
|
||||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
|
|
||||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
|
|
||||||
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGq NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
|
||||||
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "15"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "15"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "15"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "15"
|
|
||||||
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: enable NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: rden NUMERIC "0"
|
|
||||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
|
||||||
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
|
|
||||||
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
|
|
||||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
|
||||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
|
|
||||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
|
|
||||||
// Retrieval info: CONSTANT: INIT_FILE STRING "../rtl/ts/video/mem/video_cram.mif"
|
|
||||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
|
||||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
|
||||||
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
|
|
||||||
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
|
|
||||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
|
|
||||||
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
|
|
||||||
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
|
|
||||||
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
|
|
||||||
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
|
|
||||||
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
|
|
||||||
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
|
|
||||||
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "15"
|
|
||||||
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "15"
|
|
||||||
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
|
||||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
|
|
||||||
// Retrieval info: USED_PORT: data 0 0 15 0 INPUT NODEFVAL "data[14..0]"
|
|
||||||
// Retrieval info: USED_PORT: q 0 0 15 0 OUTPUT NODEFVAL "q[14..0]"
|
|
||||||
// Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]"
|
|
||||||
// Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]"
|
|
||||||
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
|
|
||||||
// Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0
|
|
||||||
// Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0
|
|
||||||
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
|
|
||||||
// Retrieval info: CONNECT: @data_a 0 0 15 0 data 0 0 15 0
|
|
||||||
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
|
|
||||||
// Retrieval info: CONNECT: q 0 0 15 0 @q_b 0 0 15 0
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_cram.v TRUE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_cram.inc FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_cram.cmp FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_cram.bsf FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_cram_inst.v FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_cram_bb.v FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_cram_waveforms.html FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_cram_wave*.jpg FALSE
|
|
||||||
// Retrieval info: LIB_FILE: altera_mf
|
|
@ -1,217 +0,0 @@
|
|||||||
// megafunction wizard: %RAM: 2-PORT%
|
|
||||||
// GENERATION: STANDARD
|
|
||||||
// VERSION: WM1.0
|
|
||||||
// MODULE: altsyncram
|
|
||||||
|
|
||||||
// ============================================================
|
|
||||||
// File Name: video_sfile.v
|
|
||||||
// Megafunction Name(s):
|
|
||||||
// altsyncram
|
|
||||||
//
|
|
||||||
// Simulation Library Files(s):
|
|
||||||
// altera_mf
|
|
||||||
// ============================================================
|
|
||||||
// ************************************************************
|
|
||||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
|
||||||
//
|
|
||||||
// 11.0 Build 208 07/03/2011 SP 1 SJ Full Version
|
|
||||||
// ************************************************************
|
|
||||||
|
|
||||||
|
|
||||||
//Copyright (C) 1991-2011 Altera Corporation
|
|
||||||
//Your use of Altera Corporation's design tools, logic functions
|
|
||||||
//and other software and tools, and its AMPP partner logic
|
|
||||||
//functions, and any output files from any of the foregoing
|
|
||||||
//(including device programming or simulation files), and any
|
|
||||||
//associated documentation or information are expressly subject
|
|
||||||
//to the terms and conditions of the Altera Program License
|
|
||||||
//Subscription Agreement, Altera MegaCore Function License
|
|
||||||
//Agreement, or other applicable license agreement, including,
|
|
||||||
//without limitation, that your use is for the sole purpose of
|
|
||||||
//programming logic devices manufactured by Altera and sold by
|
|
||||||
//Altera or its authorized distributors. Please refer to the
|
|
||||||
//applicable agreement for further details.
|
|
||||||
|
|
||||||
|
|
||||||
// synopsys translate_off
|
|
||||||
`timescale 1 ps / 1 ps
|
|
||||||
// synopsys translate_on
|
|
||||||
module video_sfile (
|
|
||||||
clock,
|
|
||||||
data,
|
|
||||||
rdaddress,
|
|
||||||
wraddress,
|
|
||||||
wren,
|
|
||||||
q);
|
|
||||||
|
|
||||||
input clock;
|
|
||||||
input [15:0] data;
|
|
||||||
input [7:0] rdaddress;
|
|
||||||
input [7:0] wraddress;
|
|
||||||
input wren;
|
|
||||||
output [15:0] q;
|
|
||||||
`ifndef ALTERA_RESERVED_QIS
|
|
||||||
// synopsys translate_off
|
|
||||||
`endif
|
|
||||||
tri1 clock;
|
|
||||||
tri0 wren;
|
|
||||||
`ifndef ALTERA_RESERVED_QIS
|
|
||||||
// synopsys translate_on
|
|
||||||
`endif
|
|
||||||
|
|
||||||
wire [15:0] sub_wire0;
|
|
||||||
wire [15:0] q = sub_wire0[15:0];
|
|
||||||
|
|
||||||
altsyncram altsyncram_component (
|
|
||||||
.address_a (wraddress),
|
|
||||||
.clock0 (clock),
|
|
||||||
.data_a (data),
|
|
||||||
.wren_a (wren),
|
|
||||||
.address_b (rdaddress),
|
|
||||||
.q_b (sub_wire0),
|
|
||||||
.aclr0 (1'b0),
|
|
||||||
.aclr1 (1'b0),
|
|
||||||
.addressstall_a (1'b0),
|
|
||||||
.addressstall_b (1'b0),
|
|
||||||
.byteena_a (1'b1),
|
|
||||||
.byteena_b (1'b1),
|
|
||||||
.clock1 (1'b1),
|
|
||||||
.clocken0 (1'b1),
|
|
||||||
.clocken1 (1'b1),
|
|
||||||
.clocken2 (1'b1),
|
|
||||||
.clocken3 (1'b1),
|
|
||||||
.data_b ({16{1'b1}}),
|
|
||||||
.eccstatus (),
|
|
||||||
.q_a (),
|
|
||||||
.rden_a (1'b1),
|
|
||||||
.rden_b (1'b1),
|
|
||||||
.wren_b (1'b0));
|
|
||||||
defparam
|
|
||||||
altsyncram_component.address_aclr_b = "NONE",
|
|
||||||
altsyncram_component.address_reg_b = "CLOCK0",
|
|
||||||
altsyncram_component.clock_enable_input_a = "BYPASS",
|
|
||||||
altsyncram_component.clock_enable_input_b = "BYPASS",
|
|
||||||
altsyncram_component.clock_enable_output_b = "BYPASS",
|
|
||||||
altsyncram_component.intended_device_family = "Cyclone IV E",
|
|
||||||
altsyncram_component.lpm_type = "altsyncram",
|
|
||||||
altsyncram_component.numwords_a = 256,
|
|
||||||
altsyncram_component.numwords_b = 256,
|
|
||||||
altsyncram_component.operation_mode = "DUAL_PORT",
|
|
||||||
altsyncram_component.outdata_aclr_b = "NONE",
|
|
||||||
altsyncram_component.outdata_reg_b = "CLOCK0",
|
|
||||||
altsyncram_component.power_up_uninitialized = "FALSE",
|
|
||||||
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
|
|
||||||
altsyncram_component.widthad_a = 8,
|
|
||||||
altsyncram_component.widthad_b = 8,
|
|
||||||
altsyncram_component.width_a = 16,
|
|
||||||
altsyncram_component.width_b = 16,
|
|
||||||
altsyncram_component.width_byteena_a = 1;
|
|
||||||
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
// ============================================================
|
|
||||||
// CNX file retrieval info
|
|
||||||
// ============================================================
|
|
||||||
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
|
||||||
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: Clock NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: ECC NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
|
|
||||||
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
|
||||||
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
|
||||||
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
|
|
||||||
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: MIFfilename STRING ""
|
|
||||||
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
|
|
||||||
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
|
|
||||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
|
|
||||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
|
|
||||||
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGq NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
|
||||||
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
|
|
||||||
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: enable NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: rden NUMERIC "0"
|
|
||||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
|
||||||
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
|
|
||||||
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
|
|
||||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
|
||||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
|
|
||||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
|
|
||||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
|
||||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
|
||||||
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
|
|
||||||
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
|
|
||||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
|
|
||||||
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
|
|
||||||
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
|
|
||||||
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
|
|
||||||
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
|
|
||||||
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
|
|
||||||
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
|
|
||||||
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
|
|
||||||
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
|
|
||||||
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
|
||||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
|
|
||||||
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
|
|
||||||
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
|
|
||||||
// Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]"
|
|
||||||
// Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]"
|
|
||||||
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
|
|
||||||
// Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0
|
|
||||||
// Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0
|
|
||||||
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
|
|
||||||
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
|
|
||||||
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
|
|
||||||
// Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_sfile.v TRUE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_sfile.inc FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_sfile.cmp FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_sfile.bsf FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_sfile_inst.v FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_sfile_bb.v FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_sfile_waveforms.html FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_sfile_wave*.jpg FALSE
|
|
||||||
// Retrieval info: LIB_FILE: altera_mf
|
|
@ -1,217 +0,0 @@
|
|||||||
// megafunction wizard: %RAM: 2-PORT%
|
|
||||||
// GENERATION: STANDARD
|
|
||||||
// VERSION: WM1.0
|
|
||||||
// MODULE: altsyncram
|
|
||||||
|
|
||||||
// ============================================================
|
|
||||||
// File Name: video_tmbuf.v
|
|
||||||
// Megafunction Name(s):
|
|
||||||
// altsyncram
|
|
||||||
//
|
|
||||||
// Simulation Library Files(s):
|
|
||||||
// altera_mf
|
|
||||||
// ============================================================
|
|
||||||
// ************************************************************
|
|
||||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
|
||||||
//
|
|
||||||
// 11.0 Build 208 07/03/2011 SP 1 SJ Full Version
|
|
||||||
// ************************************************************
|
|
||||||
|
|
||||||
|
|
||||||
//Copyright (C) 1991-2011 Altera Corporation
|
|
||||||
//Your use of Altera Corporation's design tools, logic functions
|
|
||||||
//and other software and tools, and its AMPP partner logic
|
|
||||||
//functions, and any output files from any of the foregoing
|
|
||||||
//(including device programming or simulation files), and any
|
|
||||||
//associated documentation or information are expressly subject
|
|
||||||
//to the terms and conditions of the Altera Program License
|
|
||||||
//Subscription Agreement, Altera MegaCore Function License
|
|
||||||
//Agreement, or other applicable license agreement, including,
|
|
||||||
//without limitation, that your use is for the sole purpose of
|
|
||||||
//programming logic devices manufactured by Altera and sold by
|
|
||||||
//Altera or its authorized distributors. Please refer to the
|
|
||||||
//applicable agreement for further details.
|
|
||||||
|
|
||||||
|
|
||||||
// synopsys translate_off
|
|
||||||
`timescale 1 ps / 1 ps
|
|
||||||
// synopsys translate_on
|
|
||||||
module video_tmbuf (
|
|
||||||
clock,
|
|
||||||
data,
|
|
||||||
rdaddress,
|
|
||||||
wraddress,
|
|
||||||
wren,
|
|
||||||
q);
|
|
||||||
|
|
||||||
input clock;
|
|
||||||
input [15:0] data;
|
|
||||||
input [8:0] rdaddress;
|
|
||||||
input [8:0] wraddress;
|
|
||||||
input wren;
|
|
||||||
output [15:0] q;
|
|
||||||
`ifndef ALTERA_RESERVED_QIS
|
|
||||||
// synopsys translate_off
|
|
||||||
`endif
|
|
||||||
tri1 clock;
|
|
||||||
tri0 wren;
|
|
||||||
`ifndef ALTERA_RESERVED_QIS
|
|
||||||
// synopsys translate_on
|
|
||||||
`endif
|
|
||||||
|
|
||||||
wire [15:0] sub_wire0;
|
|
||||||
wire [15:0] q = sub_wire0[15:0];
|
|
||||||
|
|
||||||
altsyncram altsyncram_component (
|
|
||||||
.address_a (wraddress),
|
|
||||||
.clock0 (clock),
|
|
||||||
.data_a (data),
|
|
||||||
.wren_a (wren),
|
|
||||||
.address_b (rdaddress),
|
|
||||||
.q_b (sub_wire0),
|
|
||||||
.aclr0 (1'b0),
|
|
||||||
.aclr1 (1'b0),
|
|
||||||
.addressstall_a (1'b0),
|
|
||||||
.addressstall_b (1'b0),
|
|
||||||
.byteena_a (1'b1),
|
|
||||||
.byteena_b (1'b1),
|
|
||||||
.clock1 (1'b1),
|
|
||||||
.clocken0 (1'b1),
|
|
||||||
.clocken1 (1'b1),
|
|
||||||
.clocken2 (1'b1),
|
|
||||||
.clocken3 (1'b1),
|
|
||||||
.data_b ({16{1'b1}}),
|
|
||||||
.eccstatus (),
|
|
||||||
.q_a (),
|
|
||||||
.rden_a (1'b1),
|
|
||||||
.rden_b (1'b1),
|
|
||||||
.wren_b (1'b0));
|
|
||||||
defparam
|
|
||||||
altsyncram_component.address_aclr_b = "NONE",
|
|
||||||
altsyncram_component.address_reg_b = "CLOCK0",
|
|
||||||
altsyncram_component.clock_enable_input_a = "BYPASS",
|
|
||||||
altsyncram_component.clock_enable_input_b = "BYPASS",
|
|
||||||
altsyncram_component.clock_enable_output_b = "BYPASS",
|
|
||||||
altsyncram_component.intended_device_family = "Cyclone IV E",
|
|
||||||
altsyncram_component.lpm_type = "altsyncram",
|
|
||||||
altsyncram_component.numwords_a = 512,
|
|
||||||
altsyncram_component.numwords_b = 512,
|
|
||||||
altsyncram_component.operation_mode = "DUAL_PORT",
|
|
||||||
altsyncram_component.outdata_aclr_b = "NONE",
|
|
||||||
altsyncram_component.outdata_reg_b = "CLOCK0",
|
|
||||||
altsyncram_component.power_up_uninitialized = "FALSE",
|
|
||||||
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
|
|
||||||
altsyncram_component.widthad_a = 9,
|
|
||||||
altsyncram_component.widthad_b = 9,
|
|
||||||
altsyncram_component.width_a = 16,
|
|
||||||
altsyncram_component.width_b = 16,
|
|
||||||
altsyncram_component.width_byteena_a = 1;
|
|
||||||
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
// ============================================================
|
|
||||||
// CNX file retrieval info
|
|
||||||
// ============================================================
|
|
||||||
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
|
||||||
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: Clock NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: ECC NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
|
|
||||||
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
|
||||||
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
|
||||||
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
|
|
||||||
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: MIFfilename STRING ""
|
|
||||||
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
|
|
||||||
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
|
|
||||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
|
|
||||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
|
|
||||||
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGq NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
|
||||||
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
|
|
||||||
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: enable NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: rden NUMERIC "0"
|
|
||||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
|
||||||
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
|
|
||||||
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
|
|
||||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
|
||||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
|
|
||||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
|
|
||||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
|
||||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
|
||||||
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
|
|
||||||
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
|
|
||||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
|
|
||||||
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
|
|
||||||
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
|
|
||||||
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
|
|
||||||
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
|
|
||||||
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
|
|
||||||
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
|
|
||||||
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
|
|
||||||
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
|
|
||||||
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
|
||||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
|
|
||||||
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
|
|
||||||
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
|
|
||||||
// Retrieval info: USED_PORT: rdaddress 0 0 9 0 INPUT NODEFVAL "rdaddress[8..0]"
|
|
||||||
// Retrieval info: USED_PORT: wraddress 0 0 9 0 INPUT NODEFVAL "wraddress[8..0]"
|
|
||||||
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
|
|
||||||
// Retrieval info: CONNECT: @address_a 0 0 9 0 wraddress 0 0 9 0
|
|
||||||
// Retrieval info: CONNECT: @address_b 0 0 9 0 rdaddress 0 0 9 0
|
|
||||||
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
|
|
||||||
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
|
|
||||||
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
|
|
||||||
// Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_tmbuf.v TRUE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_tmbuf.inc FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_tmbuf.cmp FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_tmbuf.bsf FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_tmbuf_inst.v FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_tmbuf_bb.v FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_tmbuf_waveforms.html FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_tmbuf_wave*.jpg FALSE
|
|
||||||
// Retrieval info: LIB_FILE: altera_mf
|
|
@ -1,216 +0,0 @@
|
|||||||
// megafunction wizard: %RAM: 2-PORT%
|
|
||||||
// GENERATION: STANDARD
|
|
||||||
// VERSION: WM1.0
|
|
||||||
// MODULE: altsyncram
|
|
||||||
|
|
||||||
// ============================================================
|
|
||||||
// File Name: video_tsline0.v
|
|
||||||
// Megafunction Name(s):
|
|
||||||
// altsyncram
|
|
||||||
//
|
|
||||||
// Simulation Library Files(s):
|
|
||||||
// altera_mf
|
|
||||||
// ============================================================
|
|
||||||
// ************************************************************
|
|
||||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
|
||||||
//
|
|
||||||
// 10.1 Build 153 11/29/2010 SJ Full Version
|
|
||||||
// ************************************************************
|
|
||||||
|
|
||||||
|
|
||||||
//Copyright (C) 1991-2010 Altera Corporation
|
|
||||||
//Your use of Altera Corporation's design tools, logic functions
|
|
||||||
//and other software and tools, and its AMPP partner logic
|
|
||||||
//functions, and any output files from any of the foregoing
|
|
||||||
//(including device programming or simulation files), and any
|
|
||||||
//associated documentation or information are expressly subject
|
|
||||||
//to the terms and conditions of the Altera Program License
|
|
||||||
//Subscription Agreement, Altera MegaCore Function License
|
|
||||||
//Agreement, or other applicable license agreement, including,
|
|
||||||
//without limitation, that your use is for the sole purpose of
|
|
||||||
//programming logic devices manufactured by Altera and sold by
|
|
||||||
//Altera or its authorized distributors. Please refer to the
|
|
||||||
//applicable agreement for further details.
|
|
||||||
|
|
||||||
|
|
||||||
// synopsys translate_off
|
|
||||||
`timescale 1 ps / 1 ps
|
|
||||||
// synopsys translate_on
|
|
||||||
module video_tsline0 (
|
|
||||||
clock,
|
|
||||||
data,
|
|
||||||
rdaddress,
|
|
||||||
wraddress,
|
|
||||||
wren,
|
|
||||||
q);
|
|
||||||
|
|
||||||
input clock;
|
|
||||||
input [7:0] data;
|
|
||||||
input [8:0] rdaddress;
|
|
||||||
input [8:0] wraddress;
|
|
||||||
input wren;
|
|
||||||
output [7:0] q;
|
|
||||||
`ifndef ALTERA_RESERVED_QIS
|
|
||||||
// synopsys translate_off
|
|
||||||
`endif
|
|
||||||
tri1 clock;
|
|
||||||
tri0 wren;
|
|
||||||
`ifndef ALTERA_RESERVED_QIS
|
|
||||||
// synopsys translate_on
|
|
||||||
`endif
|
|
||||||
|
|
||||||
wire [7:0] sub_wire0;
|
|
||||||
wire [7:0] q = sub_wire0[7:0];
|
|
||||||
|
|
||||||
altsyncram altsyncram_component (
|
|
||||||
.address_a (wraddress),
|
|
||||||
.clock0 (clock),
|
|
||||||
.data_a (data),
|
|
||||||
.wren_a (wren),
|
|
||||||
.address_b (rdaddress),
|
|
||||||
.q_b (sub_wire0),
|
|
||||||
.aclr0 (1'b0),
|
|
||||||
.aclr1 (1'b0),
|
|
||||||
.addressstall_a (1'b0),
|
|
||||||
.addressstall_b (1'b0),
|
|
||||||
.byteena_a (1'b1),
|
|
||||||
.byteena_b (1'b1),
|
|
||||||
.clock1 (1'b1),
|
|
||||||
.clocken0 (1'b1),
|
|
||||||
.clocken1 (1'b1),
|
|
||||||
.clocken2 (1'b1),
|
|
||||||
.clocken3 (1'b1),
|
|
||||||
.data_b ({8{1'b1}}),
|
|
||||||
.eccstatus (),
|
|
||||||
.q_a (),
|
|
||||||
.rden_a (1'b1),
|
|
||||||
.rden_b (1'b1),
|
|
||||||
.wren_b (1'b0));
|
|
||||||
defparam
|
|
||||||
altsyncram_component.address_aclr_b = "NONE",
|
|
||||||
altsyncram_component.address_reg_b = "CLOCK0",
|
|
||||||
altsyncram_component.clock_enable_input_a = "BYPASS",
|
|
||||||
altsyncram_component.clock_enable_input_b = "BYPASS",
|
|
||||||
altsyncram_component.clock_enable_output_b = "BYPASS",
|
|
||||||
altsyncram_component.intended_device_family = "Cyclone IV E",
|
|
||||||
altsyncram_component.lpm_type = "altsyncram",
|
|
||||||
altsyncram_component.numwords_a = 512,
|
|
||||||
altsyncram_component.numwords_b = 512,
|
|
||||||
altsyncram_component.operation_mode = "DUAL_PORT",
|
|
||||||
altsyncram_component.outdata_aclr_b = "NONE",
|
|
||||||
altsyncram_component.outdata_reg_b = "UNREGISTERED",
|
|
||||||
altsyncram_component.power_up_uninitialized = "FALSE",
|
|
||||||
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
|
|
||||||
altsyncram_component.widthad_a = 9,
|
|
||||||
altsyncram_component.widthad_b = 9,
|
|
||||||
altsyncram_component.width_a = 8,
|
|
||||||
altsyncram_component.width_b = 8,
|
|
||||||
altsyncram_component.width_byteena_a = 1;
|
|
||||||
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
// ============================================================
|
|
||||||
// CNX file retrieval info
|
|
||||||
// ============================================================
|
|
||||||
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
|
||||||
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: Clock NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: ECC NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
|
|
||||||
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
|
||||||
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
|
||||||
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
|
|
||||||
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: MIFfilename STRING ""
|
|
||||||
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
|
|
||||||
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
|
|
||||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
|
|
||||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
|
|
||||||
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGq NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
|
||||||
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
|
|
||||||
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: enable NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: rden NUMERIC "0"
|
|
||||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
|
||||||
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
|
|
||||||
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
|
|
||||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
|
||||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
|
|
||||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
|
|
||||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
|
||||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
|
||||||
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
|
|
||||||
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
|
|
||||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
|
|
||||||
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
|
|
||||||
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
|
|
||||||
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
|
|
||||||
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
|
|
||||||
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
|
|
||||||
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
|
|
||||||
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
|
|
||||||
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
|
|
||||||
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
|
||||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
|
|
||||||
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
|
|
||||||
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
|
|
||||||
// Retrieval info: USED_PORT: rdaddress 0 0 9 0 INPUT NODEFVAL "rdaddress[8..0]"
|
|
||||||
// Retrieval info: USED_PORT: wraddress 0 0 9 0 INPUT NODEFVAL "wraddress[8..0]"
|
|
||||||
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
|
|
||||||
// Retrieval info: CONNECT: @address_a 0 0 9 0 wraddress 0 0 9 0
|
|
||||||
// Retrieval info: CONNECT: @address_b 0 0 9 0 rdaddress 0 0 9 0
|
|
||||||
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
|
|
||||||
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
|
|
||||||
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
|
|
||||||
// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_tsline0.v TRUE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_tsline0.inc FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_tsline0.cmp FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_tsline0.bsf FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_tsline0_inst.v FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_tsline0_bb.v FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_tsline0_waveforms.html FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_tsline0_wave*.jpg FALSE
|
|
||||||
// Retrieval info: LIB_FILE: altera_mf
|
|
@ -1,216 +0,0 @@
|
|||||||
// megafunction wizard: %RAM: 2-PORT%
|
|
||||||
// GENERATION: STANDARD
|
|
||||||
// VERSION: WM1.0
|
|
||||||
// MODULE: altsyncram
|
|
||||||
|
|
||||||
// ============================================================
|
|
||||||
// File Name: video_tsline1.v
|
|
||||||
// Megafunction Name(s):
|
|
||||||
// altsyncram
|
|
||||||
//
|
|
||||||
// Simulation Library Files(s):
|
|
||||||
// altera_mf
|
|
||||||
// ============================================================
|
|
||||||
// ************************************************************
|
|
||||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
|
||||||
//
|
|
||||||
// 10.1 Build 153 11/29/2010 SJ Full Version
|
|
||||||
// ************************************************************
|
|
||||||
|
|
||||||
|
|
||||||
//Copyright (C) 1991-2010 Altera Corporation
|
|
||||||
//Your use of Altera Corporation's design tools, logic functions
|
|
||||||
//and other software and tools, and its AMPP partner logic
|
|
||||||
//functions, and any output files from any of the foregoing
|
|
||||||
//(including device programming or simulation files), and any
|
|
||||||
//associated documentation or information are expressly subject
|
|
||||||
//to the terms and conditions of the Altera Program License
|
|
||||||
//Subscription Agreement, Altera MegaCore Function License
|
|
||||||
//Agreement, or other applicable license agreement, including,
|
|
||||||
//without limitation, that your use is for the sole purpose of
|
|
||||||
//programming logic devices manufactured by Altera and sold by
|
|
||||||
//Altera or its authorized distributors. Please refer to the
|
|
||||||
//applicable agreement for further details.
|
|
||||||
|
|
||||||
|
|
||||||
// synopsys translate_off
|
|
||||||
`timescale 1 ps / 1 ps
|
|
||||||
// synopsys translate_on
|
|
||||||
module video_tsline1 (
|
|
||||||
clock,
|
|
||||||
data,
|
|
||||||
rdaddress,
|
|
||||||
wraddress,
|
|
||||||
wren,
|
|
||||||
q);
|
|
||||||
|
|
||||||
input clock;
|
|
||||||
input [7:0] data;
|
|
||||||
input [8:0] rdaddress;
|
|
||||||
input [8:0] wraddress;
|
|
||||||
input wren;
|
|
||||||
output [7:0] q;
|
|
||||||
`ifndef ALTERA_RESERVED_QIS
|
|
||||||
// synopsys translate_off
|
|
||||||
`endif
|
|
||||||
tri1 clock;
|
|
||||||
tri0 wren;
|
|
||||||
`ifndef ALTERA_RESERVED_QIS
|
|
||||||
// synopsys translate_on
|
|
||||||
`endif
|
|
||||||
|
|
||||||
wire [7:0] sub_wire0;
|
|
||||||
wire [7:0] q = sub_wire0[7:0];
|
|
||||||
|
|
||||||
altsyncram altsyncram_component (
|
|
||||||
.address_a (wraddress),
|
|
||||||
.clock0 (clock),
|
|
||||||
.data_a (data),
|
|
||||||
.wren_a (wren),
|
|
||||||
.address_b (rdaddress),
|
|
||||||
.q_b (sub_wire0),
|
|
||||||
.aclr0 (1'b0),
|
|
||||||
.aclr1 (1'b0),
|
|
||||||
.addressstall_a (1'b0),
|
|
||||||
.addressstall_b (1'b0),
|
|
||||||
.byteena_a (1'b1),
|
|
||||||
.byteena_b (1'b1),
|
|
||||||
.clock1 (1'b1),
|
|
||||||
.clocken0 (1'b1),
|
|
||||||
.clocken1 (1'b1),
|
|
||||||
.clocken2 (1'b1),
|
|
||||||
.clocken3 (1'b1),
|
|
||||||
.data_b ({8{1'b1}}),
|
|
||||||
.eccstatus (),
|
|
||||||
.q_a (),
|
|
||||||
.rden_a (1'b1),
|
|
||||||
.rden_b (1'b1),
|
|
||||||
.wren_b (1'b0));
|
|
||||||
defparam
|
|
||||||
altsyncram_component.address_aclr_b = "NONE",
|
|
||||||
altsyncram_component.address_reg_b = "CLOCK0",
|
|
||||||
altsyncram_component.clock_enable_input_a = "BYPASS",
|
|
||||||
altsyncram_component.clock_enable_input_b = "BYPASS",
|
|
||||||
altsyncram_component.clock_enable_output_b = "BYPASS",
|
|
||||||
altsyncram_component.intended_device_family = "Cyclone IV E",
|
|
||||||
altsyncram_component.lpm_type = "altsyncram",
|
|
||||||
altsyncram_component.numwords_a = 512,
|
|
||||||
altsyncram_component.numwords_b = 512,
|
|
||||||
altsyncram_component.operation_mode = "DUAL_PORT",
|
|
||||||
altsyncram_component.outdata_aclr_b = "NONE",
|
|
||||||
altsyncram_component.outdata_reg_b = "UNREGISTERED",
|
|
||||||
altsyncram_component.power_up_uninitialized = "FALSE",
|
|
||||||
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
|
|
||||||
altsyncram_component.widthad_a = 9,
|
|
||||||
altsyncram_component.widthad_b = 9,
|
|
||||||
altsyncram_component.width_a = 8,
|
|
||||||
altsyncram_component.width_b = 8,
|
|
||||||
altsyncram_component.width_byteena_a = 1;
|
|
||||||
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
// ============================================================
|
|
||||||
// CNX file retrieval info
|
|
||||||
// ============================================================
|
|
||||||
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
|
||||||
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: Clock NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: ECC NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
|
|
||||||
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
|
||||||
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
|
||||||
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
|
|
||||||
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: MIFfilename STRING ""
|
|
||||||
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
|
|
||||||
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
|
|
||||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
|
|
||||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
|
|
||||||
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGq NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
|
||||||
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
|
|
||||||
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: enable NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: rden NUMERIC "0"
|
|
||||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
|
||||||
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
|
|
||||||
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
|
|
||||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
|
||||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
|
|
||||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
|
|
||||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
|
||||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
|
||||||
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
|
|
||||||
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
|
|
||||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
|
|
||||||
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
|
|
||||||
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
|
|
||||||
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
|
|
||||||
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
|
|
||||||
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
|
|
||||||
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
|
|
||||||
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
|
|
||||||
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
|
|
||||||
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
|
||||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
|
|
||||||
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
|
|
||||||
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
|
|
||||||
// Retrieval info: USED_PORT: rdaddress 0 0 9 0 INPUT NODEFVAL "rdaddress[8..0]"
|
|
||||||
// Retrieval info: USED_PORT: wraddress 0 0 9 0 INPUT NODEFVAL "wraddress[8..0]"
|
|
||||||
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
|
|
||||||
// Retrieval info: CONNECT: @address_a 0 0 9 0 wraddress 0 0 9 0
|
|
||||||
// Retrieval info: CONNECT: @address_b 0 0 9 0 rdaddress 0 0 9 0
|
|
||||||
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
|
|
||||||
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
|
|
||||||
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
|
|
||||||
// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_tsline1.v TRUE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_tsline1.inc FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_tsline1.cmp FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_tsline1.bsf FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_tsline1_inst.v FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_tsline1_bb.v FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_tsline1_waveforms.html FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_tsline1_wave*.jpg FALSE
|
|
||||||
// Retrieval info: LIB_FILE: altera_mf
|
|
@ -1,3 +0,0 @@
|
|||||||
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
|
|
||||||
set_global_assignment -name IP_TOOL_VERSION "11.0"
|
|
||||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "video_vmem.v"]
|
|
@ -1,217 +0,0 @@
|
|||||||
// megafunction wizard: %RAM: 2-PORT%
|
|
||||||
// GENERATION: STANDARD
|
|
||||||
// VERSION: WM1.0
|
|
||||||
// MODULE: altsyncram
|
|
||||||
|
|
||||||
// ============================================================
|
|
||||||
// File Name: video_vmem.v
|
|
||||||
// Megafunction Name(s):
|
|
||||||
// altsyncram
|
|
||||||
//
|
|
||||||
// Simulation Library Files(s):
|
|
||||||
// altera_mf
|
|
||||||
// ============================================================
|
|
||||||
// ************************************************************
|
|
||||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
|
||||||
//
|
|
||||||
// 11.0 Build 157 04/27/2011 SJ Full Version
|
|
||||||
// ************************************************************
|
|
||||||
|
|
||||||
|
|
||||||
//Copyright (C) 1991-2011 Altera Corporation
|
|
||||||
//Your use of Altera Corporation's design tools, logic functions
|
|
||||||
//and other software and tools, and its AMPP partner logic
|
|
||||||
//functions, and any output files from any of the foregoing
|
|
||||||
//(including device programming or simulation files), and any
|
|
||||||
//associated documentation or information are expressly subject
|
|
||||||
//to the terms and conditions of the Altera Program License
|
|
||||||
//Subscription Agreement, Altera MegaCore Function License
|
|
||||||
//Agreement, or other applicable license agreement, including,
|
|
||||||
//without limitation, that your use is for the sole purpose of
|
|
||||||
//programming logic devices manufactured by Altera and sold by
|
|
||||||
//Altera or its authorized distributors. Please refer to the
|
|
||||||
//applicable agreement for further details.
|
|
||||||
|
|
||||||
|
|
||||||
// synopsys translate_off
|
|
||||||
`timescale 1 ps / 1 ps
|
|
||||||
// synopsys translate_on
|
|
||||||
module video_vmem (
|
|
||||||
clock,
|
|
||||||
data,
|
|
||||||
rdaddress,
|
|
||||||
wraddress,
|
|
||||||
wren,
|
|
||||||
q);
|
|
||||||
|
|
||||||
input clock;
|
|
||||||
input [7:0] data;
|
|
||||||
input [9:0] rdaddress;
|
|
||||||
input [9:0] wraddress;
|
|
||||||
input wren;
|
|
||||||
output [7:0] q;
|
|
||||||
`ifndef ALTERA_RESERVED_QIS
|
|
||||||
// synopsys translate_off
|
|
||||||
`endif
|
|
||||||
tri1 clock;
|
|
||||||
tri0 wren;
|
|
||||||
`ifndef ALTERA_RESERVED_QIS
|
|
||||||
// synopsys translate_on
|
|
||||||
`endif
|
|
||||||
|
|
||||||
wire [7:0] sub_wire0;
|
|
||||||
wire [7:0] q = sub_wire0[7:0];
|
|
||||||
|
|
||||||
altsyncram altsyncram_component (
|
|
||||||
.address_a (wraddress),
|
|
||||||
.clock0 (clock),
|
|
||||||
.data_a (data),
|
|
||||||
.wren_a (wren),
|
|
||||||
.address_b (rdaddress),
|
|
||||||
.q_b (sub_wire0),
|
|
||||||
.aclr0 (1'b0),
|
|
||||||
.aclr1 (1'b0),
|
|
||||||
.addressstall_a (1'b0),
|
|
||||||
.addressstall_b (1'b0),
|
|
||||||
.byteena_a (1'b1),
|
|
||||||
.byteena_b (1'b1),
|
|
||||||
.clock1 (1'b1),
|
|
||||||
.clocken0 (1'b1),
|
|
||||||
.clocken1 (1'b1),
|
|
||||||
.clocken2 (1'b1),
|
|
||||||
.clocken3 (1'b1),
|
|
||||||
.data_b ({8{1'b1}}),
|
|
||||||
.eccstatus (),
|
|
||||||
.q_a (),
|
|
||||||
.rden_a (1'b1),
|
|
||||||
.rden_b (1'b1),
|
|
||||||
.wren_b (1'b0));
|
|
||||||
defparam
|
|
||||||
altsyncram_component.address_aclr_b = "NONE",
|
|
||||||
altsyncram_component.address_reg_b = "CLOCK0",
|
|
||||||
altsyncram_component.clock_enable_input_a = "BYPASS",
|
|
||||||
altsyncram_component.clock_enable_input_b = "BYPASS",
|
|
||||||
altsyncram_component.clock_enable_output_b = "BYPASS",
|
|
||||||
altsyncram_component.intended_device_family = "Cyclone IV E",
|
|
||||||
altsyncram_component.lpm_type = "altsyncram",
|
|
||||||
altsyncram_component.numwords_a = 1024,
|
|
||||||
altsyncram_component.numwords_b = 1024,
|
|
||||||
altsyncram_component.operation_mode = "DUAL_PORT",
|
|
||||||
altsyncram_component.outdata_aclr_b = "NONE",
|
|
||||||
altsyncram_component.outdata_reg_b = "CLOCK0",
|
|
||||||
altsyncram_component.power_up_uninitialized = "FALSE",
|
|
||||||
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
|
|
||||||
altsyncram_component.widthad_a = 10,
|
|
||||||
altsyncram_component.widthad_b = 10,
|
|
||||||
altsyncram_component.width_a = 8,
|
|
||||||
altsyncram_component.width_b = 8,
|
|
||||||
altsyncram_component.width_byteena_a = 1;
|
|
||||||
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
// ============================================================
|
|
||||||
// CNX file retrieval info
|
|
||||||
// ============================================================
|
|
||||||
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
|
||||||
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: Clock NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: ECC NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
|
|
||||||
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
|
||||||
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
|
||||||
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
|
|
||||||
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: MIFfilename STRING ""
|
|
||||||
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
|
|
||||||
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
|
|
||||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
|
|
||||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
|
|
||||||
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGq NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
|
||||||
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
|
|
||||||
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
|
|
||||||
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
|
|
||||||
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: enable NUMERIC "0"
|
|
||||||
// Retrieval info: PRIVATE: rden NUMERIC "0"
|
|
||||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
|
||||||
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
|
|
||||||
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
|
|
||||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
|
||||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
|
|
||||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
|
|
||||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
|
||||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
|
||||||
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
|
|
||||||
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
|
|
||||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
|
|
||||||
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
|
|
||||||
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
|
|
||||||
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
|
|
||||||
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
|
|
||||||
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
|
|
||||||
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
|
|
||||||
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
|
|
||||||
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
|
|
||||||
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
|
||||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
|
|
||||||
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
|
|
||||||
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
|
|
||||||
// Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL "rdaddress[9..0]"
|
|
||||||
// Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL "wraddress[9..0]"
|
|
||||||
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
|
|
||||||
// Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0
|
|
||||||
// Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0
|
|
||||||
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
|
|
||||||
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
|
|
||||||
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
|
|
||||||
// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_vmem.v TRUE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_vmem.inc FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_vmem.cmp FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_vmem.bsf FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_vmem_inst.v FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_vmem_bb.v FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_vmem_waveforms.html FALSE
|
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL video_vmem_wave*.jpg FALSE
|
|
||||||
// Retrieval info: LIB_FILE: altera_mf
|
|
@ -52,13 +52,14 @@ module video_out (
|
|||||||
// CRAM =====================================================================
|
// CRAM =====================================================================
|
||||||
wire [14:0] vpixel;
|
wire [14:0] vpixel;
|
||||||
|
|
||||||
video_cram video_cram(
|
dpram #(.DATAWIDTH(15), .ADDRWIDTH(8), .MEM_INIT_FILE("src/video/video_cram.mif")) video_cram
|
||||||
|
(
|
||||||
.clock (clk),
|
.clock (clk),
|
||||||
.wraddress(cram_addr_in),
|
.address_a(cram_addr_in),
|
||||||
.data (cram_data_in),
|
.data_a (cram_data_in),
|
||||||
.wren (cram_we),
|
.wren_a (cram_we),
|
||||||
.rdaddress(vdata), //-<INPUT
|
.address_b(vdata), //-<INPUT
|
||||||
.q (vpixel)
|
.q_b (vpixel)
|
||||||
);
|
);
|
||||||
|
|
||||||
//=============VPIXEL=================================
|
//=============VPIXEL=================================
|
||||||
|
@ -92,8 +92,6 @@ module video_top
|
|||||||
output wire [3:0] tst
|
output wire [3:0] tst
|
||||||
);
|
);
|
||||||
|
|
||||||
// wire [2:0] tst;
|
|
||||||
|
|
||||||
|
|
||||||
assign ts_z80_lp = tsconf[4];
|
assign ts_z80_lp = tsconf[4];
|
||||||
|
|
||||||
@ -234,7 +232,6 @@ module video_top
|
|||||||
.palsel (palsel),
|
.palsel (palsel),
|
||||||
.hint_beg (hint_beg),
|
.hint_beg (hint_beg),
|
||||||
.vint_beg (vint_beg),
|
.vint_beg (vint_beg),
|
||||||
// .int_start (int_start), // uncomment to enable VSINT auto-increment
|
|
||||||
.tsconf (tsconf),
|
.tsconf (tsconf),
|
||||||
.tmpage (tmpage),
|
.tmpage (tmpage),
|
||||||
.t0gpage (t0gpage),
|
.t0gpage (t0gpage),
|
||||||
@ -339,7 +336,6 @@ module video_top
|
|||||||
.fetch_temp (fetch_temp),
|
.fetch_temp (fetch_temp),
|
||||||
.video_strobe (video_strobe),
|
.video_strobe (video_strobe),
|
||||||
.video_data (dram_rdata)
|
.video_data (dram_rdata)
|
||||||
//.video_data (16'b0000111100001111) //-OK
|
|
||||||
);
|
);
|
||||||
|
|
||||||
video_ts video_ts (
|
video_ts video_ts (
|
||||||
@ -466,34 +462,36 @@ assign vblank = vga_on ? vga_vblank : tv_vblank;
|
|||||||
wire [7:0] ts_rdata = tl_act0 ? ts_rdata0 : ts_rdata1;
|
wire [7:0] ts_rdata = tl_act0 ? ts_rdata0 : ts_rdata1;
|
||||||
wire [7:0] ts_rdata0, ts_rdata1;
|
wire [7:0] ts_rdata0, ts_rdata1;
|
||||||
|
|
||||||
|
dpram #(.ADDRWIDTH(9)) video_tsline0
|
||||||
video_tsline0 video_tsline0 (
|
(
|
||||||
.clock (clk),
|
.clock (clk),
|
||||||
.wraddress (ts_waddr0),
|
.address_a (ts_waddr0),
|
||||||
.data (ts_wdata0),
|
.data_a (ts_wdata0),
|
||||||
.wren (ts_we0),
|
.wren_a (ts_we0),
|
||||||
.rdaddress (ts_raddr),
|
.address_b (ts_raddr),
|
||||||
.q (ts_rdata0)
|
.q_b (ts_rdata0)
|
||||||
);
|
|
||||||
video_tsline1 video_tsline1 (
|
|
||||||
.clock (clk),
|
|
||||||
.wraddress (ts_waddr1),
|
|
||||||
.data (ts_wdata1),
|
|
||||||
.wren (ts_we1),
|
|
||||||
.rdaddress (ts_raddr),
|
|
||||||
.q (ts_rdata1)
|
|
||||||
);
|
);
|
||||||
|
|
||||||
|
dpram #(.ADDRWIDTH(9)) video_tsline1
|
||||||
|
(
|
||||||
|
.clock (clk),
|
||||||
|
.address_a (ts_waddr1),
|
||||||
|
.data_a (ts_wdata1),
|
||||||
|
.wren_a (ts_we1),
|
||||||
|
.address_b (ts_raddr),
|
||||||
|
.q_b (ts_rdata1)
|
||||||
|
);
|
||||||
|
|
||||||
// 2 lines * 512 pix * 8 bit (10x8) - used for VGA doubler
|
// 2 lines * 512 pix * 8 bit (10x8) - used for VGA doubler
|
||||||
// (1 altdpram)
|
// (1 altdpram)
|
||||||
video_vmem video_vmem(
|
dpram #(.ADDRWIDTH(10)) video_vmem
|
||||||
|
(
|
||||||
.clock (clk),
|
.clock (clk),
|
||||||
.wraddress (vga_cnt_in),
|
.address_a (vga_cnt_in),
|
||||||
.data (vplex),
|
.data_a (vplex),
|
||||||
.wren (c3),
|
.wren_a (c3),
|
||||||
.rdaddress (vga_cnt_out),
|
.address_b (vga_cnt_out),
|
||||||
.q (vgaplex)
|
.q_b (vgaplex)
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
||||||
|
@ -13,7 +13,8 @@
|
|||||||
// 6:0 word within line - 128 words = 512 pixels
|
// 6:0 word within line - 128 words = 512 pixels
|
||||||
|
|
||||||
|
|
||||||
module video_ts (
|
module video_ts
|
||||||
|
(
|
||||||
|
|
||||||
// clocks
|
// clocks
|
||||||
input wire clk,
|
input wire clk,
|
||||||
@ -375,29 +376,27 @@ module video_ts (
|
|||||||
|
|
||||||
// SFile
|
// SFile
|
||||||
wire [15:0] sfile_rdata;
|
wire [15:0] sfile_rdata;
|
||||||
|
dpram #(.DATAWIDTH(16), .ADDRWIDTH(8)) video_sfile
|
||||||
video_sfile video_sfile (
|
(
|
||||||
.clock (!clk), // MVV 18.10.2014
|
.clock (clk),
|
||||||
.wraddress (sfile_addr_in),
|
.address_a (sfile_addr_in),
|
||||||
.data (sfile_data_in),
|
.data_a (sfile_data_in),
|
||||||
.wren (sfile_we),
|
.wren_a (sfile_we),
|
||||||
.rdaddress (sreg),
|
.address_b (sreg),
|
||||||
.q (sfile_rdata)
|
.q_b (sfile_rdata)
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
||||||
// 4 buffers * 2 tile-planes * 64 tiles * 16 bits (9x16) - used to prefetch tiles
|
// 4 buffers * 2 tile-planes * 64 tiles * 16 bits (9x16) - used to prefetch tiles
|
||||||
// (2 altdprams)
|
// (2 altdprams)
|
||||||
wire [15:0] tmb_rdata;
|
wire [15:0] tmb_rdata;
|
||||||
|
dpram #(.DATAWIDTH(16), .ADDRWIDTH(9)) video_tmbuf
|
||||||
video_tmbuf video_tmbuf (
|
(
|
||||||
.clock (!clk), // MVV 18.10.2014
|
.clock (clk),
|
||||||
.data (dram_rdata),
|
.address_a (tmb_waddr),
|
||||||
// .data (0),
|
.data_a (dram_rdata),
|
||||||
.wraddress (tmb_waddr),
|
.wren_a (tm_next),
|
||||||
.wren (tm_next),
|
.address_b (tmb_raddr),
|
||||||
.rdaddress (tmb_raddr),
|
.q_b (tmb_rdata)
|
||||||
.q (tmb_rdata)
|
|
||||||
);
|
);
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
Reference in New Issue
Block a user