mirror of
https://github.com/UzixLS/TSConf_MiST.git
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77 lines
1.9 KiB
Verilog
77 lines
1.9 KiB
Verilog
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// This module generates video for DAC
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// MVV corrected 24bpp 24.08.2014
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module video_out (
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// clocks
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input wire clk, f0, c3,
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// video controls
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input wire vga_on,
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input wire tv_blank,
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input wire vga_blank,
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input wire [1:0] plex_sel_in,
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// mode controls
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input wire tv_hires,
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input wire vga_hires,
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input wire [3:0] palsel,
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// Z80 pins
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input wire [14:0] cram_data_in,
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input wire [7:0] cram_addr_in,
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input wire cram_we,
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// video data
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input wire [7:0] vplex_in, //<====== INPUT
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input wire [7:0] vgaplex, //<====== INPUT VGA
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output wire [7:0] vred,
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output wire [7:0] vgrn,
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output wire [7:0] vblu,
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//---------------------
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output wire [3:0] tst
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);
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assign tst[0] = clk; ////phase[0];
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assign tst[1] = cram_we; //phase[1];
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assign tst[2] = cram_addr_in[0]; //
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assign tst[3] = cram_data_in[0]; //pwm[3][{phase, 1'b0}]; //!pwm[igrn][{phase, 1'b1}];
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// TV/VGA mux
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reg [7:0] vplex;
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always @(posedge clk) if (c3) vplex <= vplex_in;
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wire [7:0] plex = vga_on ? vgaplex : vplex;
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wire plex_sel = vga_on ? plex_sel_in[0] : plex_sel_in[1];
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wire hires = vga_on ? vga_hires : tv_hires;
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wire [7:0] vdata = hires ? {palsel, plex_sel ? plex[3:0] : plex[7:4]} : plex;
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// CRAM =====================================================================
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wire [14:0] vpixel;
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dpram #(.DATAWIDTH(15), .ADDRWIDTH(8), .MEM_INIT_FILE("src/video/video_cram.mif")) video_cram
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(
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.clock (clk),
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.address_a(cram_addr_in),
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.data_a (cram_data_in),
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.wren_a (cram_we),
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.address_b(vdata), //-<INPUT
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.q_b (vpixel)
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);
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//=============VPIXEL=================================
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reg blank;
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always @(posedge clk) blank <= vga_on ? vga_blank : tv_blank;
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wire [14:0] vpix = blank ? 15'b0 : vpixel; //OK for Spectrum mode // 5 bits for every color
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assign vred = {vpix[14:10], vpix[14:12]};
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assign vgrn = {vpix[ 9: 5], vpix[ 9: 7]};
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assign vblu = {vpix[ 4: 0], vpix[ 4: 2]};
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endmodule
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