uzix/TSConf_MiST
1
0
Fork 0
mirror of https://github.com/UzixLS/TSConf_MiST.git synced 2025-07-18 14:51:25 +03:00
Code Issues Packages Projects Releases Wiki Activity

Support for external boot.rom.

Browse Source
This commit is contained in:
sorgelig
2018-08-21 17:57:50 +08:00
parent 0754af7de8
commit 72e80b6421
2 changed files with 43 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
TSConf.sv
View File

@ -97,7 +97,7 @@ module emu
output SDRAM_nWE
);
assign LED_USER = vsd_sel & sd_act;
assign LED_USER = (vsd_sel & sd_act) | ioctl_download;
assign LED_DISK = {1'b1, ~vsd_sel & sd_act};
assign LED_POWER = 0;
@ -148,7 +148,6 @@ assign CMOSCfg[27:25]= status[27:25] + 3'd2;
//////////////////// CLOCKS ///////////////////
wire locked;
wire clk_mem;
wire clk_sys;
@ -191,6 +190,12 @@ wire [63:0] img_size;
wire sd_ack_conf;
wire [64:0] RTC;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
wire ioctl_download;
wire [7:0] ioctl_index;
hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io
(
.clk_sys(clk_sys),
@ -225,9 +230,20 @@ hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io
.img_readonly(img_readonly),
.img_size(img_size),
.ioctl_wait(0)
.ioctl_wr(ioctl_wr),
.ioctl_addr(ioctl_addr),
.ioctl_dout(ioctl_dout),
.ioctl_download(ioctl_download),
.ioctl_index(ioctl_index)
);
reg [2:0] loader_wr;
always @(posedge clk_sys) begin
if(ioctl_wr && ioctl_download && !ioctl_index && !ioctl_addr[24:16]) loader_wr <= '1;
else loader_wr <= loader_wr << 1;
end
//////////////////// MAIN //////////////////////
wire [7:0] R,G,B;
wire HBlank,VBlank;
wire VSync, HSync;
@ -283,7 +299,11 @@ tsconf tsconf
.PS2_KEY(ps2_key),
.PS2_MOUSE(ps2_mouse),
.joystick(joy_0[5:0] | joy_1[5:0])
.joystick(joy_0[5:0] | joy_1[5:0]),
.loader_addr(ioctl_addr[15:0]),
.loader_data(ioctl_dout),
.loader_wr(loader_wr[2])
);
assign DDRAM_CLK = clk_mem;
@ -308,7 +328,6 @@ end
ddram ddram
(
.*,
.addr(gs_mem_addr),
.dout(gs_mem_dout),
.din(gs_mem_din),
@ -344,7 +363,6 @@ video_mixer video_mixer
////////////////// SD ///////////////////
wire sdclk;
wire sdmosi;
wire sdmiso = vsd_sel ? vsdmiso : SD_MISO;

29
src/tsconf.v
View File

@ -53,11 +53,12 @@
POSSIBILITY OF SUCH DAMAGE.
*/
module tsconf(
module tsconf
(
// Clocks
input clk_84mhz,
input clk_28mhz,
// SDRAM (32MB 16x16bit)
inout [15:0] SDRAM_DQ,
output [12:0] SDRAM_A,
@ -69,7 +70,7 @@ module tsconf(
output SDRAM_RAS_N,
output SDRAM_CKE,
output SDRAM_CS_N,
// VGA
output [7:0] VGA_R,
output [7:0] VGA_G,
@ -79,13 +80,13 @@ module tsconf(
output VGA_HBLANK,
output VGA_VBLANK,
output VGA_CEPIX,
// SD/MMC Memory Card
input SD_SO,
output SD_SI,
output SD_CLK,
output SD_CS_N,
// General Sound
output [20:0] GS_ADDR,
output [7:0] GS_DI,
@ -93,22 +94,26 @@ module tsconf(
output GS_RD,
output GS_WR,
input GS_WAIT,
// Audio
output [15:0] SOUND_L,
output [15:0] SOUND_R,
// External I/O
input COLD_RESET,
input WARM_RESET,
output RESET_OUT,
input [64:0] RTC,
input [31:0] CMOSCfg,
// PS/2 Keyboard
input [10:0] PS2_KEY,
input [24:0] PS2_MOUSE,
input [5:0] joystick
input [5:0] joystick,
input [15:0] loader_addr,
input [7:0] loader_data,
input loader_wr
);
@ -701,7 +706,11 @@ dpram #(.ADDRWIDTH(16), .MEM_INIT_FILE("tsbios.mif")) BIOS
(
.clock(clk_28mhz),
.address_a({cpu_addr_20[14:0],cpu_wrbsel}),
.q_a(bios_do_bus)
.q_a(bios_do_bus),
.address_b(loader_addr),
.data_b(loader_data),
.wren_b(loader_wr)
);
// SDRAM Controller