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fix covox output to the left channel only

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This commit is contained in:
Eugene Lozovoy
2024-10-05 19:51:57 +03:00
parent 5022d16b77
commit 66c4af17e4
3 changed files with 48 additions and 54 deletions
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2
files.qip
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@ -13,10 +13,10 @@ set_global_assignment -name VERILOG_FILE rtl/periph/vdac.v
set_global_assignment -name VERILOG_FILE rtl/periph/zifi.v set_global_assignment -name VERILOG_FILE rtl/periph/zifi.v
set_global_assignment -name VERILOG_FILE rtl/periph/uart_tx.v set_global_assignment -name VERILOG_FILE rtl/periph/uart_tx.v
set_global_assignment -name VERILOG_FILE rtl/periph/uart_rx.v set_global_assignment -name VERILOG_FILE rtl/periph/uart_rx.v
set_global_assignment -name VHDL_FILE rtl/sound/soundrive.vhd
set_global_assignment -name QIP_FILE rtl/sound/jt12/jt03.qip set_global_assignment -name QIP_FILE rtl/sound/jt12/jt03.qip
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sound/turbosound.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/sound/turbosound.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sound/saa1099.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/sound/saa1099.sv
set_global_assignment -name VERILOG_FILE rtl/sound/soundrive.v
set_global_assignment -name VERILOG_FILE rtl/sound/gs.v set_global_assignment -name VERILOG_FILE rtl/sound/gs.v
set_global_assignment -name VERILOG_FILE rtl/sound/gs_top.v set_global_assignment -name VERILOG_FILE rtl/sound/gs_top.v
set_global_assignment -name VERILOG_FILE rtl/sound/compressor.v set_global_assignment -name VERILOG_FILE rtl/sound/compressor.v

47
rtl/sound/soundrive.v Normal file
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@ -0,0 +1,47 @@
// SOUNDRIVE 1.05 PORTS mode 1
// #0F = left channel A (stereo covox channel 1)
// #1F = left channel B
// #4F = right channel C (stereo covox channel 2)
// #5F = right channel D
// #FB = right channel D + left channel B
module soundrive
(
input reset,
input clk,
input cs,
input [7:0] a,
input [7:0] di,
input wr_n,
input iorq_n,
input dos,
output reg [7:0] outa,
output reg [7:0] outb,
output reg [7:0] outc,
output reg [7:0] outd
);
always @(posedge clk) begin
if (reset || !cs) begin
outa <= 0;
outb <= 0;
outc <= 0;
outd <= 0;
end
else begin
if (!iorq_n && !wr_n && !dos) begin
case (a)
8'h0F: outa <= di;
8'h1F: outb <= di;
8'h4F: outc <= di;
8'h5F: outd <= di;
8'hFB: begin outd <= di; outb <= di; end
endcase
end
end
end
endmodule

53
rtl/sound/soundrive.vhd
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@ -1,53 +0,0 @@
-------------------------------------------------------------------[27.10.2011]
-- Soundrive 1.05
-------------------------------------------------------------------------------
-- V0.1 05.10.2011 <09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
-- SOUNDRIVE 1.05 PORTS mode 1
-- #0F = left channel A (stereo covox channel 1)
-- #1F = left channel B
-- #4F = right channel C (stereo covox channel 2)
-- #5F = right channel D
-- #FB = right channel D
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity soundrive is
Port (
RESET : in std_logic;
CLK : in std_logic;
CS : in std_logic;
A : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
WR_n : in std_logic;
IORQ_n: in std_logic;
DOS : in std_logic;
OUTA : out std_logic_vector(7 downto 0);
OUTB : out std_logic_vector(7 downto 0);
OUTC : out std_logic_vector(7 downto 0);
OUTD : out std_logic_vector(7 downto 0));
end soundrive;
architecture soundrive_unit of soundrive is
begin
process (CLK, RESET, CS)
begin
if RESET = '1' or CS = '0' then
outa <= (others => '0');
outb <= (others => '0');
outc <= (others => '0');
outd <= (others => '0');
elsif rising_edge(CLK) then
if A = X"0F" and IORQ_n = '0' and WR_n = '0' and DOS = '0' then outa <= DI;
elsif A = X"1F" and IORQ_n = '0' and WR_n = '0' and DOS = '0' then outb <= DI;
elsif A = X"4F" and IORQ_n = '0' and WR_n = '0' and DOS = '0' then outc <= DI;
elsif A = X"5F" and IORQ_n = '0' and WR_n = '0' and DOS = '0' then outd <= DI;
elsif A = X"FB" and IORQ_n = '0' and WR_n = '0' and DOS = '0' then outd <= DI;
end if;
end if;
end process;
end soundrive_unit;