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https://github.com/UzixLS/TSConf_MiST.git
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53 lines
1.6 KiB
VHDL
53 lines
1.6 KiB
VHDL
-------------------------------------------------------------------[27.10.2011]
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-- Soundrive 1.05
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-------------------------------------------------------------------------------
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-- V0.1 05.10.2011 <09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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-- SOUNDRIVE 1.05 PORTS mode 1
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-- #0F = left channel A (stereo covox channel 1)
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-- #1F = left channel B
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-- #4F = right channel C (stereo covox channel 2)
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-- #5F = right channel D
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-- #FB = right channel D
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity soundrive is
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Port (
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RESET : in std_logic;
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CLK : in std_logic;
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CS : in std_logic;
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A : in std_logic_vector(7 downto 0);
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DI : in std_logic_vector(7 downto 0);
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WR_n : in std_logic;
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IORQ_n: in std_logic;
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DOS : in std_logic;
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OUTA : out std_logic_vector(7 downto 0);
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OUTB : out std_logic_vector(7 downto 0);
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OUTC : out std_logic_vector(7 downto 0);
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OUTD : out std_logic_vector(7 downto 0));
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end soundrive;
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architecture soundrive_unit of soundrive is
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begin
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process (CLK, RESET, CS)
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begin
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if RESET = '1' or CS = '0' then
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outa <= (others => '0');
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outb <= (others => '0');
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outc <= (others => '0');
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outd <= (others => '0');
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elsif rising_edge(CLK) then
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if A = X"0F" and IORQ_n = '0' and WR_n = '0' and DOS = '0' then outa <= DI;
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elsif A = X"1F" and IORQ_n = '0' and WR_n = '0' and DOS = '0' then outb <= DI;
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elsif A = X"4F" and IORQ_n = '0' and WR_n = '0' and DOS = '0' then outc <= DI;
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elsif A = X"5F" and IORQ_n = '0' and WR_n = '0' and DOS = '0' then outd <= DI;
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elsif A = X"FB" and IORQ_n = '0' and WR_n = '0' and DOS = '0' then outd <= DI;
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end if;
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end if;
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end process;
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end soundrive_unit; |