uzix/TSConf_MiST
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cleanup some warnings

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This commit is contained in:
Eugene Lozovoy
2024-09-18 19:47:15 +03:00
parent 8909ef759b
commit 4c87bedf94
4 changed files with 27 additions and 49 deletions
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18
rtl/common/clock.v
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@ -2,16 +2,16 @@
// This module receives 28 MHz as input clock
// and makes strobes for all clocked parts
// clk |<EFBFBD>__<EFBFBD><EFBFBD>__<EFBFBD><EFBFBD>__<EFBFBD><EFBFBD>__<EFBFBD>| period = 28 duty = 50% phase = 0
// clk |‾__‾‾__‾‾__‾‾__‾| period = 28 duty = 50% phase = 0
// cnt |< 0>< 1>< 2>< 3>|
// f0 |<EFBFBD><EFBFBD><EFBFBD><EFBFBD>____<EFBFBD><EFBFBD><EFBFBD><EFBFBD>____| period = 14 duty = 50% phase = 0
// f1 |____<EFBFBD><EFBFBD><EFBFBD><EFBFBD>____<EFBFBD><EFBFBD><EFBFBD><EFBFBD>| period = 14 duty = 50% phase = 180
// h0 |<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>________| period = 7 duty = 50% phase = 0
// h1 |________<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>| period = 7 duty = 50% phase = 180
// c0 |<EFBFBD><EFBFBD><EFBFBD><EFBFBD>____________| period = 7 duty = 25% phase = 0
// c1 |____<EFBFBD><EFBFBD><EFBFBD><EFBFBD>________| period = 7 duty = 25% phase = 90
// c2 |________<EFBFBD><EFBFBD><EFBFBD><EFBFBD>____| period = 7 duty = 25% phase = 180
// c3 |____________<EFBFBD><EFBFBD><EFBFBD><EFBFBD>| period = 7 duty = 25% phase = 270
// f0 |‾‾‾‾____‾‾‾‾____| period = 14 duty = 50% phase = 0
// f1 |____‾‾‾‾____‾‾‾‾| period = 14 duty = 50% phase = 180
// h0 |‾‾‾‾‾‾‾‾________| period = 7 duty = 50% phase = 0
// h1 |________‾‾‾‾‾‾‾‾| period = 7 duty = 50% phase = 180
// c0 |‾‾‾‾____________| period = 7 duty = 25% phase = 0
// c1 |____‾‾‾‾________| period = 7 duty = 25% phase = 90
// c2 |________‾‾‾‾____| period = 7 duty = 25% phase = 180
// c3 |____________‾‾‾‾| period = 7 duty = 25% phase = 270
`include "tune.v"

2
rtl/dram/sdram.v
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@ -89,7 +89,7 @@ reg rd1, rd2 = 0;
always @(posedge clk) begin
sdr_cmd <= SdrCmd_xx;
data <= SDRAM_DQ;
SDRAM_DQ <= 16'bZ;
SDRAM_DQ <= {16{1'bZ}};
state <= state + 1'd1;
port2_ack <= 1'b0;

4
rtl/video/video_ports.v
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@ -60,14 +60,14 @@ module video_ports
output reg [7:0] sgpage = 0
);
reg [7:0] vpage_r = 0;
reg [7:0] vpage_r = 8'h05;
reg [7:0] vconf_r = 0;
reg [7:0] t0gpage_r = 0;
reg [7:0] t1gpage_r = 0;
reg [8:0] gx_offs_r = 0;
reg [8:0] t0x_offs_r = 0;
reg [8:0] t1x_offs_r = 0;
reg [7:0] palsel_r = 0;
reg [7:0] palsel_r = 8'h0F;
reg [3:0] vint_inc = 0;
wire [8:0] vint_beg_inc = vint_beg + vint_inc;