From 4c87bedf947fdc2e8f2c62d672b35a6d6e570831 Mon Sep 17 00:00:00 2001 From: Eugene Lozovoy Date: Wed, 18 Sep 2024 19:47:15 +0300 Subject: [PATCH] cleanup some warnings --- TSConf.srf | 52 ++++++++++++----------------------------- rtl/common/clock.v | 18 +++++++------- rtl/dram/sdram.v | 2 +- rtl/video/video_ports.v | 4 ++-- 4 files changed, 27 insertions(+), 49 deletions(-) diff --git a/TSConf.srf b/TSConf.srf index 0e1df68..9347723 100644 --- a/TSConf.srf +++ b/TSConf.srf @@ -1,18 +1,14 @@ -{ "" "" "" "Vip.Mixer: The MixerII register map changed in ACDS v16.0. Please refer to the VIP User Guide for details." { } { } 0 12251 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Vip.Reset_Source.reset_sys: Associated reset sinks not declared" { } { } 0 12251 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Vip.Reset_Source.reset_warm: Associated reset sinks not declared" { } { } 0 12251 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Vip.Reset_Source.reset_cold: Associated reset sinks not declared" { } { } 0 12251 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Vip.Video_Output.control: Interrupt sender control.av_mm_control_interrupt is not connected to an interrupt receiver" { } { } 0 12251 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Vip.Video_Output: Interrupt sender Video_Output.status_update_irq is not connected to an interrupt receiver" { } { } 0 12251 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Vip.: You have exported the interface HPS.f2h_sdram1_data but not its associated reset interface. Export the driver(s) of HPS.h2f_reset" { } { } 0 12251 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Vip.: You have exported the interface HPS.f2h_sdram2_data but not its associated reset interface. Export the driver(s) of HPS.h2f_reset" { } { } 0 12251 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Port \"extclk\" on the entity instantiation of \"cyclonev_pll\" is connected to a signal of width 1. The formal width of the signal in the module is 2. The extra bits will be left dangling without any fan-out logic." { } { } 0 12030 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Port \"trs\" on the entity instantiation of \"statemachine\" is connected to a signal of width 2. The formal width of the signal in the module is 1. The extra bits will be ignored." { } { } 0 12020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Port \"reset_value\" on the entity instantiation of \"h_counter\" is connected to a signal of width 32. The formal width of the signal in the module is 16. The extra bits will be ignored." { } { } 0 12020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at user_io.v(271): object \"kbd_out_data_available\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at tsconf.v(111): object \"cfg_tape_sound\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at tsconf.v(132): object \"zclk\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at video_out.v(83): object \"red0\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at video_out.v(84): object \"grn0\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at video_out.v(85): object \"blu0\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at video_out.v(86): object \"red1\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at video_out.v(87): object \"grn1\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at video_out.v(88): object \"blu1\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at zports.v(417): object \"portxt_rd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL assignment warning at zports.v(572): truncated value with size 8 to match size of target (2)" { } { } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""} { "" "" "" "Net \"lut.data_a\" at jt49_exp.v(37) has no driver or initial value, using a default initial value '0'" { } { } 0 10030 "" 0 0 "Quartus II" 0 -1 0 ""} { "" "" "" "Net \"lut.waddr_a\" at jt49_exp.v(37) has no driver or initial value, using a default initial value '0'" { } { } 0 10030 "" 0 0 "Quartus II" 0 -1 0 ""} { "" "" "" "Net \"lut.we_a\" at jt49_exp.v(37) has no driver or initial value, using a default initial value '0'" { } { } 0 10030 "" 0 0 "Quartus II" 0 -1 0 ""} @@ -22,25 +18,7 @@ { "" "" "" "Net \"lfo_sh2_lut.waddr_a\" at jt12_pm.v(39) has no driver or initial value, using a default initial value '0'" { } { } 0 10030 "" 0 0 "Quartus II" 0 -1 0 ""} { "" "" "" "Net \"lfo_sh1_lut.we_a\" at jt12_pm.v(38) has no driver or initial value, using a default initial value '0'" { } { } 0 10030 "" 0 0 "Quartus II" 0 -1 0 ""} { "" "" "" "Net \"lfo_sh2_lut.we_a\" at jt12_pm.v(39) has no driver or initial value, using a default initial value '0'" { } { } 0 10030 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at video_out.v(83): object \"red0\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at video_out.v(84): object \"grn0\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at video_out.v(85): object \"blu0\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at video_out.v(86): object \"red1\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at video_out.v(87): object \"grn1\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at video_out.v(88): object \"blu1\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL assignment warning at zports.v(572): truncated value with size 8 to match size of target (2)" { } { } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 292013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Vip.vip: Module dependency loop involving: \"HPS\"" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_mode_banks.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_pll.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_cyclonev_pll.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_pll_reconfig_core.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "mode_banks" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "RST port on the PLL is not properly connected" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL information at jt12_reg_ch.v(104): always construct contains both blocking and non-blocking assignments" { } { } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "PCI-clamp diode is not supported in this mode. The following 1 pins must meet the Altera requirements for 3.3V, 3.0V, and 2.5V interfaces if they are connected to devices other than the supported configuration devices. In these cases, Altera recommends termination method as specified in the Application Note 447." { } { } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "26 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { } { } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/rtl/common/clock.v b/rtl/common/clock.v index 998eb04..2ecdd5f 100644 --- a/rtl/common/clock.v +++ b/rtl/common/clock.v @@ -2,16 +2,16 @@ // This module receives 28 MHz as input clock // and makes strobes for all clocked parts -// clk |—__——__——__——__—| period = 28 duty = 50% phase = 0 +// clk |‾__‾‾__‾‾__‾‾__‾| period = 28 duty = 50% phase = 0 // cnt |< 0>< 1>< 2>< 3>| -// f0 |————____————____| period = 14 duty = 50% phase = 0 -// f1 |____————____————| period = 14 duty = 50% phase = 180 -// h0 |————————________| period = 7 duty = 50% phase = 0 -// h1 |________————————| period = 7 duty = 50% phase = 180 -// c0 |————____________| period = 7 duty = 25% phase = 0 -// c1 |____————________| period = 7 duty = 25% phase = 90 -// c2 |________————____| period = 7 duty = 25% phase = 180 -// c3 |____________————| period = 7 duty = 25% phase = 270 +// f0 |‾‾‾‾____‾‾‾‾____| period = 14 duty = 50% phase = 0 +// f1 |____‾‾‾‾____‾‾‾‾| period = 14 duty = 50% phase = 180 +// h0 |‾‾‾‾‾‾‾‾________| period = 7 duty = 50% phase = 0 +// h1 |________‾‾‾‾‾‾‾‾| period = 7 duty = 50% phase = 180 +// c0 |‾‾‾‾____________| period = 7 duty = 25% phase = 0 +// c1 |____‾‾‾‾________| period = 7 duty = 25% phase = 90 +// c2 |________‾‾‾‾____| period = 7 duty = 25% phase = 180 +// c3 |____________‾‾‾‾| period = 7 duty = 25% phase = 270 `include "tune.v" diff --git a/rtl/dram/sdram.v b/rtl/dram/sdram.v index 46bd3d2..f06c43b 100644 --- a/rtl/dram/sdram.v +++ b/rtl/dram/sdram.v @@ -89,7 +89,7 @@ reg rd1, rd2 = 0; always @(posedge clk) begin sdr_cmd <= SdrCmd_xx; data <= SDRAM_DQ; - SDRAM_DQ <= 16'bZ; + SDRAM_DQ <= {16{1'bZ}}; state <= state + 1'd1; port2_ack <= 1'b0; diff --git a/rtl/video/video_ports.v b/rtl/video/video_ports.v index 08c20bb..640d5ea 100644 --- a/rtl/video/video_ports.v +++ b/rtl/video/video_ports.v @@ -60,14 +60,14 @@ module video_ports output reg [7:0] sgpage = 0 ); - reg [7:0] vpage_r = 0; + reg [7:0] vpage_r = 8'h05; reg [7:0] vconf_r = 0; reg [7:0] t0gpage_r = 0; reg [7:0] t1gpage_r = 0; reg [8:0] gx_offs_r = 0; reg [8:0] t0x_offs_r = 0; reg [8:0] t1x_offs_r = 0; - reg [7:0] palsel_r = 0; + reg [7:0] palsel_r = 8'h0F; reg [3:0] vint_inc = 0; wire [8:0] vint_beg_inc = vint_beg + vint_inc;