mirror of
https://github.com/UzixLS/TSConf_MiST.git
synced 2025-07-18 14:51:25 +03:00
Some fixes and improvements.
This commit is contained in:
sorgelig
@ -15,6 +15,9 @@
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{ "" "" "" "Verilog HDL or VHDL warning at sys_top.v(601): object \"VSET\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Verilog HDL or VHDL warning at altera_pll_reconfig_core.v(208): object \"dps_start_assert\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
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||||
{ "" "" "" "Port \"extclk\" on the entity instantiation of \"cyclonev_pll\" is connected to a signal of width 1. The formal width of the signal in the module is 2. The extra bits will be left dangling without any fan-out logic." { } { } 0 12030 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Inferred RAM node \"emu:emu\|tsconf:tsconf\|T80s:z80_unit\|T80:u0\|T80_Reg:Regs\|RegsH_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Inferred RAM node \"emu:emu\|tsconf:tsconf\|T80s:z80_unit\|T80:u0\|T80_Reg:Regs\|RegsL_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
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||||
{ "" "" "" "*" { } { } 0 21074 "" 0 0 "Design Software" 0 -1 0 ""}
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||||
{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "sysmem_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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||||
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@ -1,257 +0,0 @@
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2092
src/loader_fat32/loader.mif
Normal file
2092
src/loader_fat32/loader.mif
Normal file
File diff suppressed because it is too large
Load Diff
@ -62,7 +62,7 @@ BEGIN
|
||||
address_aclr_a => "NONE",
|
||||
clock_enable_input_a => "BYPASS",
|
||||
clock_enable_output_a => "BYPASS",
|
||||
init_file => "./loader_fat32/loader.hex",
|
||||
init_file => "./loader_fat32/loader.mif",
|
||||
intended_device_family => "Cyclone IV E",
|
||||
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
|
||||
lpm_type => "altsyncram",
|
||||
@ -104,7 +104,7 @@ END SYN;
|
||||
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: MIFfilename STRING "./src/loader_fat32/loader.hex"
|
||||
-- Retrieval info: PRIVATE: MIFfilename STRING "./src/loader_fat32/loader.mif"
|
||||
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
|
||||
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
|
||||
@ -119,7 +119,7 @@ END SYN;
|
||||
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: INIT_FILE STRING "./src/loader_fat32/loader.hex"
|
||||
-- Retrieval info: CONSTANT: INIT_FILE STRING "./src/loader_fat32/loader.mif"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
||||
|
||||
@ -1,9 +0,0 @@
|
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|
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|
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|
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|
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|
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|
||||
:2000C000FFFFFFFFFFFFFFFFFFFFFFFFFFFF000042088410C61808214A298C31CE392104ED
|
||||
:2000E000630CA514E71C29256B2DAD35EF3D6BA200000000000000000000000000000000D4
|
||||
:00000001FF
|
||||
71
src/rtc/CMOS.mif
Normal file
71
src/rtc/CMOS.mif
Normal file
@ -0,0 +1,71 @@
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
-- Quartus Prime generated Memory Initialization File (.mif)
|
||||
|
||||
WIDTH=8;
|
||||
DEPTH=256;
|
||||
|
||||
ADDRESS_RADIX=HEX;
|
||||
DATA_RADIX=HEX;
|
||||
|
||||
CONTENT BEGIN
|
||||
[000..010] : 00;
|
||||
011 : AA;
|
||||
[012..0B0] : 00;
|
||||
0B1 : 01;
|
||||
0B2 : 00;
|
||||
0B3 : 01;
|
||||
0B4 : 03;
|
||||
[0B5..0B7] : 00;
|
||||
0B8 : 01;
|
||||
[0B9..0BA] : 00;
|
||||
0BB : 02;
|
||||
[0BC..0CD] : FF;
|
||||
[0CE..0CF] : 00;
|
||||
0D0 : 42;
|
||||
0D1 : 08;
|
||||
0D2 : 84;
|
||||
0D3 : 10;
|
||||
0D4 : C6;
|
||||
0D5 : 18;
|
||||
0D6 : 08;
|
||||
0D7 : 21;
|
||||
0D8 : 4A;
|
||||
0D9 : 29;
|
||||
0DA : 8C;
|
||||
0DB : 31;
|
||||
0DC : CE;
|
||||
0DD : 39;
|
||||
0DE : 21;
|
||||
0DF : 04;
|
||||
0E0 : 63;
|
||||
0E1 : 0C;
|
||||
0E2 : A5;
|
||||
0E3 : 14;
|
||||
0E4 : E7;
|
||||
0E5 : 1C;
|
||||
0E6 : 29;
|
||||
0E7 : 25;
|
||||
0E8 : 6B;
|
||||
0E9 : 2D;
|
||||
0EA : AD;
|
||||
0EB : 35;
|
||||
0EC : EF;
|
||||
0ED : 3D;
|
||||
0EE : 6B;
|
||||
0EF : A2;
|
||||
[0F0..0FF] : 00;
|
||||
END;
|
||||
@ -101,7 +101,7 @@ BEGIN
|
||||
clock_enable_input_a => "BYPASS",
|
||||
clock_enable_input_b => "BYPASS",
|
||||
clock_enable_output_b => "BYPASS",
|
||||
init_file => "src/rtc/CMOS.hex",
|
||||
init_file => "src/rtc/CMOS.mif",
|
||||
intended_device_family => "Cyclone IV E",
|
||||
lpm_type => "altsyncram",
|
||||
numwords_a => 256,
|
||||
@ -167,7 +167,7 @@ END SYN;
|
||||
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048"
|
||||
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: MIFfilename STRING "../rtl/rtc/CMOS.hex"
|
||||
-- Retrieval info: PRIVATE: MIFfilename STRING "./src/rtc/CMOS.mif"
|
||||
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
|
||||
@ -200,7 +200,7 @@ END SYN;
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: INIT_FILE STRING "../rtl/rtc/CMOS.hex"
|
||||
-- Retrieval info: CONSTANT: INIT_FILE STRING "./src/rtc/CMOS.mif"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
||||
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
|
||||
|
||||
@ -185,7 +185,7 @@ architecture rtl of T80_MCode is
|
||||
|
||||
begin
|
||||
|
||||
process (IR, ISet, MCycle, F, NMICycle, IntCycle)
|
||||
process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State)
|
||||
variable DDD : std_logic_vector(2 downto 0);
|
||||
variable SSS : std_logic_vector(2 downto 0);
|
||||
variable DPair : std_logic_vector(1 downto 0);
|
||||
|
||||
@ -68,7 +68,6 @@ port
|
||||
SDRAM_DQ : inout std_logic_vector(15 downto 0);
|
||||
SDRAM_A : out std_logic_vector(12 downto 0);
|
||||
SDRAM_BA : out std_logic_vector(1 downto 0);
|
||||
SDRAM_CLK : out std_logic;
|
||||
SDRAM_DQML : out std_logic;
|
||||
SDRAM_DQMH : out std_logic;
|
||||
SDRAM_WE_N : out std_logic;
|
||||
@ -344,9 +343,6 @@ signal key : std_logic_vector(4 downto 0) := "00000";
|
||||
signal clk_hdmi : std_logic;
|
||||
signal csync_ts : std_logic;
|
||||
signal hdmi_d1_sig : std_logic;
|
||||
-- I2C
|
||||
signal i2c_do_bus : std_logic_vector(7 downto 0);
|
||||
signal i2c_wr : std_logic;
|
||||
|
||||
signal mouse_do : std_logic_vector(7 downto 0);
|
||||
-------------------------------------------------------------------------------
|
||||
@ -1269,8 +1265,6 @@ port map (
|
||||
CLK => clk_84mhz,
|
||||
clk_28MHz=> clk_28mhz,
|
||||
c0 => c0,
|
||||
c1 => c1,
|
||||
c2 => c2,
|
||||
c3 => c3,
|
||||
curr_cpu => curr_cpu, -- from arbiter for luch DO_cpu
|
||||
loader => loader, -- loader = 1: wr to ROM
|
||||
@ -1281,22 +1275,16 @@ port map (
|
||||
DO_cpu => sdr2cpu_do_bus_16,
|
||||
REQ => dram_req,
|
||||
RNW => dram_rnw,
|
||||
RFSH => not cpu_rfsh_n,
|
||||
RFSHREQ => open,
|
||||
IDLE => open,
|
||||
CK => SDRAM_CLK,
|
||||
CKE => open,
|
||||
CKE => SDRAM_CKE,
|
||||
RAS_n => SDRAM_RAS_N,
|
||||
CAS_n => SDRAM_CAS_N,
|
||||
WE_n => SDRAM_WE_N,
|
||||
BA1 => SDRAM_BA(1),
|
||||
BA0 => SDRAM_BA(0),
|
||||
CS_n => SDRAM_CS_N,
|
||||
BA => SDRAM_BA,
|
||||
MA => SDRAM_A,
|
||||
DQ => SDRAM_DQ(15 downto 0),
|
||||
DQML => SDRAM_DQML,
|
||||
DQMH => SDRAM_DQMH,
|
||||
dram_stb => open,
|
||||
TST => open);
|
||||
DQMH => SDRAM_DQMH);
|
||||
|
||||
SE5: entity work.keyboard
|
||||
port map(
|
||||
@ -1367,22 +1355,6 @@ port map (
|
||||
CN1_B => ssg_cn1_b,
|
||||
CN1_C => ssg_cn1_c);
|
||||
|
||||
-- I2C Controller
|
||||
--U12: entity work.i2c
|
||||
--port map (
|
||||
-- RESET => reset,
|
||||
-- CLK => clk_28mhz,
|
||||
-- ENA => ena_0_4375mhz,
|
||||
-- A => cpu_a_bus(4),
|
||||
-- DI => cpu_do_bus,
|
||||
-- DO => i2c_do_bus,
|
||||
-- WR => i2c_wr,
|
||||
-- I2C_SCL => SCL,
|
||||
-- I2C_SDA => SDA);
|
||||
|
||||
SDRAM_CKE <= '1'; -- pullup
|
||||
SDRAM_CS_N <= '0'; -- pulldown
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
-- Global
|
||||
-------------------------------------------------------------------------------
|
||||
@ -1414,7 +1386,7 @@ cpu_di_bus <= rom_do_bus when (loader = '1' and cpu_mreq_n = '0' and cpu_rd_n =
|
||||
ssg_cn0_bus when (cpu_iorq_n = '0' and cpu_rd_n = '0' and cpu_a_bus = "1111111111111101" and ssg_sel = '0') else -- TurboSound
|
||||
ssg_cn1_bus when (cpu_iorq_n = '0' and cpu_rd_n = '0' and cpu_a_bus = "1111111111111101" and ssg_sel = '1') else
|
||||
key_scancode when (cpu_iorq_n = '0' and cpu_rd_n = '0' and cpu_a_bus = X"0001") else
|
||||
i2c_do_bus when (cpu_iorq_n = '0' and cpu_rd_n = '0' and cpu_a_bus( 7 downto 5) = "100" and cpu_a_bus(3 downto 0) = "1100") else -- RTC
|
||||
X"FF" when (cpu_iorq_n = '0' and cpu_rd_n = '0' and cpu_a_bus( 7 downto 5) = "100" and cpu_a_bus(3 downto 0) = "1100") else -- RTC
|
||||
dout_ports when ena_ports = '1' else
|
||||
"11111111";
|
||||
|
||||
@ -1465,8 +1437,6 @@ port_bff7 <= '1' when (cpu_iorq_n = '0' and cpu_a_bus = X"BFF7" and cpu_m1_n = '
|
||||
--SD_CS_N <= sdcs_n_TS or loader;
|
||||
SD_CS_N <= sdcs_n_TS;
|
||||
|
||||
-- I2C
|
||||
i2c_wr <= '1' when (cpu_a_bus(7 downto 5) = "100" and cpu_a_bus(3 downto 0) = "1100" and cpu_wr_n = '0' and cpu_iorq_n = '0') else '0'; -- Port xx8C/xx9C[xxxxxxxx_100n1100]
|
||||
|
||||
SOUND_L <= ("000" & port_xxfe_reg(4) & "0000000") + ("000" & ssg_cn0_a) + ("000" & ssg_cn0_b) + ("000" & ssg_cn1_a) + ("000" & ssg_cn1_b) + ("000" & covox_a) + ("000" & covox_b);
|
||||
SOUND_R <= ("000" & port_xxfe_reg(4) & "0000000") + ("000" & ssg_cn0_c) + ("000" & ssg_cn0_b) + ("000" & ssg_cn1_c) + ("000" & ssg_cn1_b) + ("000" & covox_c) + ("000" & covox_d);
|
||||
|
||||
@ -14,7 +14,7 @@
|
||||
|
||||
-- Quartus II generated Memory Initialization File (.mif)
|
||||
|
||||
WIDTH=16;
|
||||
WIDTH=15;
|
||||
DEPTH=256;
|
||||
|
||||
ADDRESS_RADIX=HEX;
|
||||
|
||||
30
sys/pll.qip
30
sys/pll.qip
@ -43,9 +43,9 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::ODQuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MjY=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::Mzc3OTU3MTEzNQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MTY=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MjM=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MjIzMzM4Mjk5NA==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MTQ=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
|
||||
@ -55,21 +55,21 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::ODQuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MjY=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::Mzc3OTU3MTEzNQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MTY=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MjM=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MjIzMzM4Mjk5NA==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MTQ=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::LTQyMDA=::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::LTQzNTA=::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MTgwLjA=::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::NTYuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MjY=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::Mzc3OTU3MTEzNQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MjQ=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MjM=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MjIzMzM4Mjk5NA==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MjE=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
|
||||
@ -79,9 +79,9 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MjguMA==::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MjY=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::Mzc3OTU3MTEzNQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::NDg=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MjM=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MjIzMzM4Mjk5NA==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::NDI=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
|
||||
@ -260,7 +260,7 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::ODQuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::LTQxODUgcHM=::cGhhc2Vfc2hpZnQx"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::LTQzNTcgcHM=::cGhhc2Vfc2hpZnQx"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::NTYuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
|
||||
@ -318,7 +318,7 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::MTMsMTMsMjU2LDI1NixmYWxzZSx0cnVlLGZhbHNlLGZhbHNlLDgsOCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSw4LDgsMTEsMyxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDEyLDEyLDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDI0LDI0LDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDEsMjAsNDAwMCwxMzQzLjk5OTk5OSBNSHosMzc3OTU3MTEzNSxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::MTIsMTEsMjU2LDI1NixmYWxzZSx0cnVlLHRydWUsZmFsc2UsNyw3LDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDcsNyw5LDcscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxMSwxMCwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDIxLDIxLDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDEsMjAsNDAwMCwxMTc2LjAgTUh6LDIyMzMzODI5OTQsbm9uZSxnbGIsbV9jbnQscGhfbXV4X2Nsayx0cnVl::UGFyYW1ldGVyIFZhbHVlcw=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
|
||||
|
||||
@ -85,7 +85,7 @@ endmodule
|
||||
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift1" value="-4200" />
|
||||
// Retrieval info: <generic name="gui_phase_shift1" value="-4350" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg1" value="180.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
|
||||
|
||||
@ -32,7 +32,7 @@ module pll_0002(
|
||||
.phase_shift0("0 ps"),
|
||||
.duty_cycle0(50),
|
||||
.output_clock_frequency1("84.000000 MHz"),
|
||||
.phase_shift1("-4185 ps"),
|
||||
.phase_shift1("-4357 ps"),
|
||||
.duty_cycle1(50),
|
||||
.output_clock_frequency2("56.000000 MHz"),
|
||||
.phase_shift2("0 ps"),
|
||||
|
||||
@ -16,7 +16,7 @@ create_generated_clock -source [get_pins -compatibility_mode {pll_hdmi|pll_hdmi_
|
||||
create_generated_clock -source [get_pins { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
|
||||
-name VID_CLK -divide_by 2 -duty_cycle 50 [get_nets {vip|output_inst|vid_clk}]
|
||||
|
||||
create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] \
|
||||
create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] \
|
||||
-name ZCLK -divide_by 2 -duty_cycle 50 [get_nets {emu:emu|tsconf:tsconf|zclock:TS02|zclk_o}]
|
||||
|
||||
derive_clock_uncertainty
|
||||
|
||||
Reference in New Issue
Block a user