Add General Sound (384KB).

TSConf-lite.qsf

@@ -374,6 +374,7 @@ set_global_assignment -name VHDL_FILE src/rtc/mc146818a.vhd
 set_global_assignment -name VHDL_FILE src/sound/soundrive.vhd
 set_global_assignment -name VHDL_FILE src/sound/turbosound.vhd
 set_global_assignment -name VHDL_FILE src/sound/ay8910.vhd
+set_global_assignment -name VHDL_FILE src/sound/gs.vhd
 set_global_assignment -name VERILOG_FILE src/memory/dma.v
 set_global_assignment -name VERILOG_FILE src/memory/arbiter.v
 set_global_assignment -name VERILOG_FILE src/video/video_ts_render.v
@@ -391,7 +392,8 @@ set_global_assignment -name VERILOG_FILE src/video/mem/video_tmbuf.v
 set_global_assignment -name VERILOG_FILE src/video/mem/video_sfile.v
 set_global_assignment -name VERILOG_FILE src/video/mem/video_cram.v
 set_global_assignment -name VERILOG_FILE src/video/video_top.v
-set_global_assignment -name VHDL_FILE src/rom.vhd
+set_global_assignment -name VHDL_FILE src/gen_rom.vhd
+set_global_assignment -name VHDL_FILE src/gen_ram.vhd
 set_global_assignment -name VHDL_FILE src/keyboard.vhd
 set_global_assignment -name VERILOG_FILE src/kempston_mouse.v
 set_global_assignment -name VERILOG_FILE src/spi.v

TSConf.qsf

@@ -380,6 +380,7 @@ set_global_assignment -name VHDL_FILE src/rtc/mc146818a.vhd
 set_global_assignment -name VHDL_FILE src/sound/soundrive.vhd
 set_global_assignment -name VHDL_FILE src/sound/turbosound.vhd
 set_global_assignment -name VHDL_FILE src/sound/ay8910.vhd
+set_global_assignment -name VHDL_FILE src/sound/gs.vhd
 set_global_assignment -name VERILOG_FILE src/memory/dma.v
 set_global_assignment -name VERILOG_FILE src/memory/arbiter.v
 set_global_assignment -name VERILOG_FILE src/video/video_ts_render.v
@@ -397,7 +398,8 @@ set_global_assignment -name VERILOG_FILE src/video/mem/video_tmbuf.v
 set_global_assignment -name VERILOG_FILE src/video/mem/video_sfile.v
 set_global_assignment -name VERILOG_FILE src/video/mem/video_cram.v
 set_global_assignment -name VERILOG_FILE src/video/video_top.v
-set_global_assignment -name VHDL_FILE src/rom.vhd
+set_global_assignment -name VHDL_FILE src/gen_rom.vhd
+set_global_assignment -name VHDL_FILE src/gen_ram.vhd
 set_global_assignment -name VHDL_FILE src/keyboard.vhd
 set_global_assignment -name VERILOG_FILE src/kempston_mouse.v
 set_global_assignment -name VERILOG_FILE src/spi.v

TSConf.sv

@@ -112,12 +112,12 @@ localparam CONF_STR = {
 	"O5,Aspect ratio,4:3,16:9;",
 	"O12,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
 	"O34,Stereo mix,None,25%,50%,100%;",
+	"OS,General Sound,Enabled,Disabled;",
 	"-;",
 	"O67,CPU Speed,3.5MHz,7MHz,14MHz;",
 	"O8,CPU Cache,On,Off;",
 	"O9A,#7FFD span,128K,128K Auto,1024K,512K;",
 	"OLN,ZX Palette,Default,B.black,Light,Pale,Dark,Grayscale,Custom;",
-	"OO,NGS Reset,Off,On;",
 	"OPR,INT Offset,2,3,4,5,6,7,0,1;",
 	"-;",
 	"OBD,F11 Reset,boot.$C,sys.rom,ROM #00,ROM #04,RAM #F8;",
@@ -142,7 +142,7 @@ assign CMOSCfg[15:14]= status[15:14];
 assign CMOSCfg[18:16]= status[18:16];
 assign CMOSCfg[20:19]= status[20:19] + 2'd2;
 assign CMOSCfg[23:21]= status[23:21];
-assign CMOSCfg[24]   = status[24];
+assign CMOSCfg[24]   = 0;
 assign CMOSCfg[27:25]= status[27:25] + 3'd2;
 
 
@@ -152,6 +152,7 @@ wire locked;
 wire clk_mem;
 wire clk_sys;
 wire clk_28m;
+wire clk_21m;
 
 pll pll
 (
@@ -161,6 +162,7 @@ pll pll
 	.outclk_1(SDRAM_CLK),
 	.outclk_2(clk_sys),
 	.outclk_3(clk_28m),
+	.outclk_4(clk_21m),
 	.locked(locked)
 );
 
@@ -232,14 +234,13 @@ wire HBlank,VBlank;
 wire VSync, HSync;
 wire ce_vid;
 
-wire [10:0] laudio, raudio;
-
 wire reset;
 
 tsconf tsconf
 (
 	.clk_84mhz(clk_mem),
 	.clk_28mhz(clk_28m),
+	.clk_21mhz(clk_21m),
 
 	.SDRAM_DQ(SDRAM_DQ),
 	.SDRAM_A(SDRAM_A),
@@ -266,8 +267,9 @@ tsconf tsconf
 	.SD_CLK(sdclk),
 	.SD_CS_N(sdss),
 
-	.SOUND_L(laudio),
+	.GS_ENA(~status[28]),
-	.SOUND_R(raudio),
+	.SOUND_L(AUDIO_L),
+	.SOUND_R(AUDIO_R),
 	
 	.COLD_RESET(RESET | status[0]),
 	.WARM_RESET(buttons[1]),
@@ -281,8 +283,6 @@ tsconf tsconf
 	.joystick(joy_0[5:0] | joy_1[5:0])
 );
 
-assign AUDIO_R = {raudio, 5'd0};
-assign AUDIO_L = {laudio, 5'd0};
 assign AUDIO_S = 0;
 assign AUDIO_MIX = status[4:3];
 

src/gen_ram.vhd

@@ -0,0 +1,84 @@
+-- -----------------------------------------------------------------------
+--
+-- Syntiac's generic VHDL support files.
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+--
+-- Modified April 2016 by Dar (darfpga@aol.fr) 
+-- http://darfpga.blogspot.fr
+--   Remove address register when writing
+--
+-- -----------------------------------------------------------------------
+--
+-- gen_rwram.vhd
+--
+-- -----------------------------------------------------------------------
+--
+-- generic ram.
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+entity gen_ram is
+	generic (
+		dWidth : integer := 8;
+		aWidth : integer := 10
+	);
+	port (
+		clk : in std_logic;
+		we : in std_logic;
+		addr : in std_logic_vector((aWidth-1) downto 0);
+		d : in std_logic_vector((dWidth-1) downto 0);
+		q : out std_logic_vector((dWidth-1) downto 0)
+	);
+end entity;
+
+-- -----------------------------------------------------------------------
+
+architecture rtl of gen_ram is
+	subtype addressRange is integer range 0 to ((2**aWidth)-1);
+	type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
+	signal ram: ramDef;
+
+	signal rAddrReg : std_logic_vector((aWidth-1) downto 0);
+	signal qReg : std_logic_vector((dWidth-1) downto 0);
+begin
+-- -----------------------------------------------------------------------
+-- Signals to entity interface
+-- -----------------------------------------------------------------------
+--	q <= qReg;
+
+-- -----------------------------------------------------------------------
+-- Memory write
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if we = '1' then
+				ram(to_integer(unsigned(addr))) <= d;
+			end if;
+		end if;
+	end process;
+	
+-- -----------------------------------------------------------------------
+-- Memory read
+-- -----------------------------------------------------------------------
+process(clk)
+	begin
+		if rising_edge(clk) then
+--			qReg <= ram(to_integer(unsigned(rAddrReg)));
+--			rAddrReg <= addr;
+----			qReg <= ram(to_integer(unsigned(addr)));
+      q <= ram(to_integer(unsigned(addr)));
+		end if;
+	end process;
+--q <= ram(to_integer(unsigned(addr)));
+end architecture;
+

src/gen_rom.vhd

@@ -0,0 +1,65 @@
+-- altera message_off 10306
+
+library ieee;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.ALL;
+use IEEE.numeric_std.all;
+
+entity gen_rom is
+
+	generic 
+	(
+		INIT_FILE  : string  := "";
+		ADDR_WIDTH : natural := 14;
+		DATA_WIDTH : natural := 8
+	);
+
+	port 
+	(
+		wrclock   : in  std_logic;
+		wraddress : in  std_logic_vector((ADDR_WIDTH - 1) downto 0) := (others => '0');
+		data	    : in  std_logic_vector((DATA_WIDTH - 1) downto 0) := (others => '0');
+		wren      : in  std_logic := '0';
+
+		rdclock   : in  std_logic;
+		rdaddress : in  std_logic_vector((ADDR_WIDTH - 1) downto 0);
+		q         : out std_logic_vector((DATA_WIDTH - 1) downto 0);
+		cs        : in  std_logic := '1'
+	);
+
+end gen_rom;
+
+architecture rtl of gen_rom is
+
+	subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
+	type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;
+
+	shared variable ram : memory_t;
+	
+	attribute ram_init_file : string;
+	attribute ram_init_file of ram : variable is INIT_FILE;
+	
+	signal q0 : std_logic_vector((DATA_WIDTH - 1) downto 0);
+	
+
+begin
+
+	q<= q0 when cs = '1' else (others => '1');
+
+	-- WR Port
+	process(wrclock) begin
+		if(rising_edge(wrclock)) then 
+			if(wren = '1') then
+				ram(to_integer(unsigned(wraddress))) := data;
+			end if;
+		end if;
+	end process;
+
+	-- RD Port
+	process(rdclock) begin
+		if(rising_edge(rdclock)) then 
+			 q0 <= ram(to_integer(unsigned(rdaddress)));
+		end if;
+	end process;
+
+end rtl;

src/rom.vhd

@@ -1,144 +0,0 @@
--- megafunction wizard: %ROM: 1-PORT%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altsyncram 
-
--- ============================================================
--- File Name: rom.vhd
--- Megafunction Name(s):
--- 			altsyncram
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 17.0.1 Build 598 06/07/2017 SJ Standard Edition
--- ************************************************************
-
-
---Copyright (C) 2017  Intel Corporation. All rights reserved.
---Your use of Intel Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Intel Program License 
---Subscription Agreement, the Intel Quartus Prime License Agreement,
---the Intel MegaCore Function License Agreement, or other 
---applicable license agreement, including, without limitation, 
---that your use is for the sole purpose of programming logic 
---devices manufactured by Intel and sold by Intel or its 
---authorized distributors.  Please refer to the applicable 
---agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY rom IS
-	PORT
-	(
-		address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
-		clock		: IN STD_LOGIC  := '1';
-		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
-	);
-END rom;
-
-
-ARCHITECTURE SYN OF rom IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
-
-BEGIN
-	q    <= sub_wire0(7 DOWNTO 0);
-
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		address_aclr_a => "NONE",
-		clock_enable_input_a => "BYPASS",
-		clock_enable_output_a => "BYPASS",
-		init_file => "./loader_fat32/loader.mif",
-		intended_device_family => "Cyclone IV E",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 8192,
-		operation_mode => "ROM",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		widthad_a => 13,
-		width_a => 8,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => address,
-		clock0 => clock,
-		q_a => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
--- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
--- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
--- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
--- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
--- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
--- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
--- Retrieval info: PRIVATE: Clken NUMERIC "0"
--- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
--- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
--- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
--- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
--- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
--- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
--- Retrieval info: PRIVATE: MIFfilename STRING "./src/loader_fat32/loader.mif"
--- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
--- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
--- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
--- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
--- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
--- Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
--- Retrieval info: PRIVATE: WidthData NUMERIC "8"
--- Retrieval info: PRIVATE: rden NUMERIC "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
--- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
--- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
--- Retrieval info: CONSTANT: INIT_FILE STRING "./src/loader_fat32/loader.mif"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
--- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
--- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
--- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
--- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
--- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
--- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
--- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
--- Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]"
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
--- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
--- Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
--- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
--- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL rom.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL rom.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL rom.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL rom.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL rom_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf

src/sound/gs.vhd

@@ -0,0 +1,330 @@
+-------------------------------------------------------------------[04.10.2015]
+-- General Sound
+-------------------------------------------------------------------------------
+-- 01.11.2011	первая версия
+-- 19.12.2011	CPU @ 84MHz, подтверждение INT#
+-- 10.05.2013	исправлен bit7_flag, bit0_flag
+-- 29.05.2013	добавлена громкость каналов, CPU @ 21MHz
+-- 21.07.2013	исправлен int_n
+
+-- CPU: Z80
+-- ROM: 32K
+-- RAM: 384K
+-- INT: 37.5KHz
+
+-- #xxBB Command register - регистр команд, доступный для записи
+-- #xxBB Status register - регистр состояния, доступный для чтения
+--		bit 7 флаг данных
+--		bit <6:1> Не определен
+--		bit 0 флаг команд. Этот регистр позволяет определить состояние GS, в частности можно ли прочитать или записать очередной байт данных, или подать очередную команду, и т.п.
+-- #xxB3 Data register - регистр данных, доступный для записи. В этот регистр Спектрум записывает данные, например, это могут быть аргументы команд.
+-- #xxB3 Output register - регистр вывода, доступный для чтения. Из этого регистра Спектрум читает данные, идущие от GS
+
+-- Внутренние порта:
+-- #xx00 "расширенная память" - регистр доступный для записи
+--		bit <3:0> переключают страницы по 32Kb, страница 0 - ПЗУ
+--		bit <7:0> не используются
+
+-- порты 1 - 5 "обеспечивают связь с SPECTRUM'ом"
+-- #xx01 чтение команды General Sound'ом
+--		bit <7:0> код команды
+-- #xx02 чтение данных General Sound'ом
+--		bit <7:0> данные
+-- #xx03 запись данных General Sound'ом для SPECTRUM'a
+--		bit <7:0> данные
+-- #xx04 чтение слова состояния General Sound'ом
+--		bit 0 флаг команд
+--		bit 7 флаг данных
+-- #xx05 сбрасывает бит D0 (флаг команд) слова состояния
+
+-- порты 6 - 9 "регулировка громкости" в каналах 1 - 4
+-- #xx06 "регулировка громкости" в канале 1
+--		bit <5:0> громкость
+--		bit <7:6> не используются
+-- #xx07 "регулировка громкости" в канале 2
+--		bit <5:0> громкость
+--		bit <7:6> не используются
+-- #xx08 "регулировка громкости" в канале 3
+--		bit <5:0> громкость
+--		bit <7:6> не используются
+-- #xx09 "регулировка громкости" в канале 4
+--		bit <5:0> громкость
+--		bit <7:6> не используются
+
+-- #xx0A устанавливает бит 7 слова состояния не равным биту 0 порта #xx00
+-- #xx0B устанавливает бит 0 слова состояния равным биту 5 порта #xx06
+
+--Распределение памяти
+--#0000 - #3FFF  -  первые 16Kb ПЗУ
+--#4000 - #7FFF  -  первые 16Kb первой страницы ОЗУ
+--#8000 - #FFFF  -  листаемые страницы по 32Kb
+--                  страница 0  - ПЗУ,
+--                  страница 1  - первая страница ОЗУ
+--                  страницы 2... ОЗУ
+
+--Данные в каналы заносятся при чтении процессором ОЗУ по адресам  #6000 - #7FFF автоматически.
+
+library IEEE; 
+use IEEE.std_logic_1164.all; 
+use IEEE.std_logic_unsigned.all;
+use IEEE.numeric_std.all;
+use IEEE.STD_LOGIC_ARITH.all;
+
+entity gs is
+Port (
+	RESET		: in  std_logic;
+	CLK		: in  std_logic;
+	CLKGS		: in  std_logic;
+	A			: in  std_logic_vector(15 downto 0);
+	DI			: in  std_logic_vector(7 downto 0);
+	DO			: out std_logic_vector(7 downto 0);
+	WR_n		: in  std_logic;
+	RD_n		: in  std_logic;
+	IORQ_n	: in  std_logic;
+	M1_n		: in  std_logic;
+	OUTA		: out std_logic_vector(13 downto 0);
+	OUTB		: out std_logic_vector(13 downto 0);
+	OUTC		: out std_logic_vector(13 downto 0);
+	OUTD		: out std_logic_vector(13 downto 0)
+);
+end gs;
+
+architecture gs_unit of gs is
+	signal port_xxbb_reg	: std_logic_vector(7 downto 0);
+	signal port_xxb3_reg : std_logic_vector(7 downto 0);
+	signal port_xx00_reg : std_logic_vector(7 downto 0);
+	signal port_xx03_reg : std_logic_vector(7 downto 0);
+	signal port_xx06_reg : std_logic_vector(5 downto 0);
+	signal port_xx07_reg : std_logic_vector(5 downto 0);
+	signal port_xx08_reg : std_logic_vector(5 downto 0);
+	signal port_xx09_reg : std_logic_vector(5 downto 0);
+	signal ch_a_reg 		: std_logic_vector(7 downto 0);
+	signal ch_b_reg 		: std_logic_vector(7 downto 0);
+	signal ch_c_reg 		: std_logic_vector(7 downto 0);
+	signal ch_d_reg 		: std_logic_vector(7 downto 0);
+	signal bit7_flag		: std_logic;
+	signal bit0_flag		: std_logic;
+	signal cnt				: std_logic_vector(9 downto 0);
+	signal int_n			: std_logic;
+	signal out_a			: std_logic_vector(13 downto 0);
+	signal out_b			: std_logic_vector(13 downto 0);
+	signal out_c			: std_logic_vector(13 downto 0);
+	signal out_d			: std_logic_vector(13 downto 0);
+
+	-- CPU
+	signal cpu_m1_n		: std_logic;
+	signal cpu_mreq_n		: std_logic;
+	signal cpu_iorq_n		: std_logic;
+	signal cpu_rd_n		: std_logic;
+	signal cpu_wr_n		: std_logic;
+	signal cpu_a_bus		: std_logic_vector(15 downto 0);
+	signal cpu_di_bus		: std_logic_vector(7 downto 0);
+	signal cpu_do_bus		: std_logic_vector(7 downto 0);
+
+	signal ram_we			: std_logic;
+	signal ram_en			: std_logic;
+	signal rom_do			: std_logic_vector(7 downto 0);
+	signal ram1_do			: std_logic_vector(7 downto 0);
+	signal ram2_do			: std_logic_vector(7 downto 0);
+	signal mem_do			: std_logic_vector(7 downto 0);
+	signal ram_addr		: std_logic_vector(18 downto 0);
+begin
+
+z80_unit: entity work.T80s
+generic map (
+	Mode			=> 0,	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+	T2Write		=> 1,	-- 0 => WR_n active in T3, 1 => WR_n active in T2
+	IOWait		=> 1)	-- 0 => Single cycle I/O, 1 => Std I/O cycle
+port map (
+	RESET_n		=> not RESET,
+	CLK_n			=> not CLKGS,
+	WAIT_n		=> '1',
+	INT_n			=> int_n,
+	NMI_n			=> '1',
+	BUSRQ_n		=> '1',
+	M1_n			=> cpu_m1_n,
+	MREQ_n		=> cpu_mreq_n,
+	IORQ_n		=> cpu_iorq_n,
+	RD_n			=> cpu_rd_n,
+	WR_n			=> cpu_wr_n,
+	RFSH_n		=> open,
+	HALT_n		=> open,
+	BUSAK_n		=> open,
+	A				=> cpu_a_bus,
+	DI				=> cpu_di_bus,
+	DO				=> cpu_do_bus,
+	SavePC      => open,
+	SaveINT     => open,
+	RestorePC   => (others => '1'),
+	RestoreINT  => (others => '1'),
+	RestorePC_n => '1');
+
+	
+process (CLKGS, cnt)
+begin
+	if CLKGS'event and CLKGS = '1' then
+		cnt <= cnt + 1;
+		if cnt = "1000110000" then	-- 21MHz / 560 = 0.0375MHz = 37.5kHz
+			cnt <= (others => '0');
+		end if;
+	end if;
+end process;
+
+-- INT#
+process (CLKGS, cpu_iorq_n, cpu_m1_n, cnt)
+begin
+	if cpu_iorq_n = '0' and cpu_m1_n = '0' then
+		int_n <= '1';
+	elsif CLKGS'event and CLKGS = '1' then
+		if cnt = "1000110000" then
+			int_n <= '0';
+		end if;
+	end if;
+end process;
+
+process (CLKGS, cpu_iorq_n, cpu_m1_n, cpu_a_bus, IORQ_n, RD_n, A, WR_n)
+begin
+	if (cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"2") or (IORQ_n = '0' and RD_n = '0' and A(7 downto 0) = X"B3") then
+		bit7_flag <= '0';
+	elsif (cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"3") or (IORQ_n = '0' and WR_n = '0' and A(7 downto 0) = X"B3") then
+		bit7_flag <= '1';
+	elsif CLKGS'event and CLKGS = '1' then
+		if (cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"A") then
+			bit7_flag <= not port_xx00_reg(0);
+		end if;
+	end if;
+end process;
+
+process (CLKGS, cpu_iorq_n, cpu_m1_n, cpu_a_bus, IORQ_n, RD_n, A, WR_n)
+begin
+	if cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"5" then
+		bit0_flag <= '0';
+	elsif IORQ_n = '0' and WR_n = '0' and A(7 downto 0) = X"BB" then
+		bit0_flag <= '1';
+	elsif CLKGS'event and CLKGS = '1' then
+		if (cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"B") then
+			bit0_flag <= port_xx06_reg(5);
+		end if;
+	end if;
+end process;
+
+process (CLK, A, IORQ_n, WR_n, RESET)
+begin
+	-- запись со стороны спектрума
+ 	if RESET = '1' then
+		port_xxbb_reg <= (others => '0');
+		port_xxb3_reg <= (others => '0');
+	elsif CLK'event and CLK = '1' then
+		if IORQ_n = '0' and WR_n = '0' and A(7 downto 0) = X"BB" then port_xxbb_reg <= DI; end if;
+		if IORQ_n = '0' and WR_n = '0' and A(7 downto 0) = X"B3" then port_xxb3_reg <= DI; end if;
+	end if;
+end process;
+
+process (A, bit7_flag, bit0_flag, port_xx03_reg)
+begin	
+	-- чтение со стороны спектрума
+	if A(3) = '1' then	-- port #xxBB
+		DO <= bit7_flag & "111111" & bit0_flag;
+	else				-- port #xxB3
+		DO <= port_xx03_reg;
+	end if;
+end process;
+
+process (CLKGS, RESET, cpu_a_bus, cpu_m1_n, port_xx00_reg)
+begin
+	if RESET = '1' then
+		port_xx00_reg <= (others => '0');
+		port_xx03_reg <= (others => '0');
+		port_xx06_reg <= (others => '0');
+		port_xx07_reg <= (others => '0');
+		port_xx08_reg <= (others => '0');
+		port_xx09_reg <= (others => '0');
+		ch_a_reg <= (others => '0');
+		ch_b_reg <= (others => '0');
+		ch_c_reg <= (others => '0');
+		ch_d_reg <= (others => '0');
+		
+	elsif CLKGS'event and CLKGS = '1' then
+		if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"0" then port_xx00_reg <= cpu_do_bus; end if;
+		if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"3" then port_xx03_reg <= cpu_do_bus; end if;
+		if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"6" then port_xx06_reg <= cpu_do_bus(5 downto 0); end if;
+		if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"7" then port_xx07_reg <= cpu_do_bus(5 downto 0); end if;
+		if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"8" then port_xx08_reg <= cpu_do_bus(5 downto 0); end if;
+		if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"9" then port_xx09_reg <= cpu_do_bus(5 downto 0); end if;
+		
+		if cpu_mreq_n = '0' and cpu_rd_n = '0' and cpu_a_bus(15 downto 13) = "011" and cpu_a_bus(9 downto 8) = "00" then ch_a_reg <= ram1_do; end if;
+		if cpu_mreq_n = '0' and cpu_rd_n = '0' and cpu_a_bus(15 downto 13) = "011" and cpu_a_bus(9 downto 8) = "01" then ch_b_reg <= ram1_do; end if;
+		if cpu_mreq_n = '0' and cpu_rd_n = '0' and cpu_a_bus(15 downto 13) = "011" and cpu_a_bus(9 downto 8) = "10" then ch_c_reg <= ram1_do; end if;
+		if cpu_mreq_n = '0' and cpu_rd_n = '0' and cpu_a_bus(15 downto 13) = "011" and cpu_a_bus(9 downto 8) = "11" then ch_d_reg <= ram1_do; end if;
+	end if;
+end process;
+
+-- Шина данных CPU
+cpu_di_bus <=
+	mem_do when (cpu_mreq_n = '0' and cpu_rd_n = '0') else
+	bit7_flag & "111111" & bit0_flag when (cpu_iorq_n = '0' and cpu_rd_n = '0' and cpu_a_bus(3 downto 0) = X"4") else
+	port_xxbb_reg when (cpu_iorq_n = '0' and cpu_rd_n = '0' and cpu_a_bus(3 downto 0) = X"1") else
+	port_xxb3_reg when (cpu_iorq_n = '0' and cpu_rd_n = '0' and cpu_a_bus(3 downto 0) = X"2") else
+	"11111111";
+
+OUTA <= ch_a_reg * port_xx06_reg;
+OUTB <= ch_b_reg * port_xx07_reg;
+OUTC <= ch_c_reg * port_xx08_reg;
+OUTD <= ch_d_reg * port_xx09_reg;
+
+ram_en <= '1' when cpu_a_bus(15 downto 14) = "01" or (cpu_a_bus(15) = '1' and port_xx00_reg(3 downto 0) /= "0000") else '0';
+ram_we <= not cpu_wr_n and not cpu_mreq_n and ram_en;
+
+ram_addr <=
+	"00000" & cpu_a_bus(13 downto 0) when cpu_a_bus(15) = '0' else
+	(port_xx00_reg(3 downto 0) - "0001") & cpu_a_bus(14 downto 0);
+
+mem_do <= 
+	rom_do when ram_en = '0' else
+	ram1_do when cpu_a_bus(15 downto 14) = "01" or (cpu_a_bus(15) = '1' and port_xx00_reg(3 downto 0) /= "0000" and ram_addr(18) = '0') else
+	ram2_do when cpu_a_bus(15) = '1' and port_xx00_reg(3 downto 0) /= "0000" and ram_addr(18 downto 17) = "10" else
+	x"FF";
+
+ROM: entity work.gen_rom
+generic map
+(
+	INIT_FILE  => "src/sound/gs105a.mif ",
+	ADDR_WIDTH => 15
+)
+port map
+(
+	wrclock   => CLKGS,
+	rdclock   => CLKGS,
+	rdaddress => cpu_a_bus(14 downto 0),
+	q         => rom_do
+);
+
+-- 256KB
+RAM1: entity work.gen_ram
+generic map (
+	aWidth => 18
+)
+port map
+(
+	clk => CLKGS,
+	we  => ram_we and not ram_addr(18),
+	addr => ram_addr(17 downto 0),
+	d => cpu_do_bus,
+	q => ram1_do
+);
+
+-- 128KB
+RAM2: entity work.gen_ram
+generic map (
+	aWidth => 17
+)
+port map
+(
+	clk => CLKGS,
+	we  => ram_we and ram_addr(18) and not ram_addr(17),
+	addr => ram_addr(16 downto 0),
+	d => cpu_do_bus,
+	q => ram2_do
+);
+
+end gs_unit;

src/tsconf.vhd

@@ -60,9 +60,10 @@ use IEEE.numeric_std.all;
 entity tsconf is
 port
 (
-	-- Clock (24MHz)
+	-- Clocks
 	clk_84mhz	: in  std_logic;
 	clk_28mhz	: in  std_logic;
+	clk_21mhz	: in  std_logic;
 
 	-- SDRAM (32MB 16x16bit)
 	SDRAM_DQ		: inout std_logic_vector(15 downto 0);
@@ -92,15 +93,16 @@ port
 	SD_CLK		: out std_logic;
 	SD_CS_N		: out std_logic;
 
-	-- External I/O
+	-- Audio
-	SOUND_L		: out std_logic_vector(10 downto 0);
+	GS_ENA		: in  std_logic;
-	SOUND_R		: out std_logic_vector(10 downto 0);
+	SOUND_L		: out std_logic_vector(15 downto 0);
+	SOUND_R		: out std_logic_vector(15 downto 0);
 
+	-- External I/O
 	COLD_RESET	: in  std_logic;
 	WARM_RESET	: in  std_logic;
 	RESET_OUT	: out std_logic;
 	RTC         : in  std_logic_vector(64 downto 0);
-
 	CMOSCfg		: in  std_logic_vector(31 downto 0);
 
 	-- PS/2 Keyboard
@@ -343,6 +345,14 @@ signal csync_ts		: std_logic;
 signal hdmi_d1_sig	: std_logic;
 
 signal mouse_do		: std_logic_vector(7 downto 0);
+
+-- General Sound
+signal gs_a				: std_logic_vector(13 downto 0);
+signal gs_b				: std_logic_vector(13 downto 0);
+signal gs_c				: std_logic_vector(13 downto 0);
+signal gs_d				: std_logic_vector(13 downto 0);
+signal gs_do_bus		: std_logic_vector(7 downto 0);
+
 -------------------------------------------------------------------------------
 -- COMPONENTS TS Lab
 -------------------------------------------------------------------------------
@@ -1251,12 +1261,20 @@ port map (
 	int_n			=> cpu_int_n_TS);
 	 
 -- ROM
-SE1: entity work.rom
+SE1: entity work.gen_rom
-port map (
+generic map
-	address	=> cpu_a_bus(12 downto 0),
+(
-	clock	 	=> clk_28mhz,
+	INIT_FILE  => "src/loader_fat32/loader.mif",
-	q	 		=> rom_do_bus);
+	ADDR_WIDTH => 13
-
+)
+port map
+(
+	wrclock   => clk_28mhz,
+	rdclock   => clk_28mhz,
+	rdaddress => cpu_a_bus(12 downto 0),
+	q         => rom_do_bus
+);
+	
 -- SDRAM Controller
 SE4: entity work.sdram
 port map (
@@ -1353,6 +1371,23 @@ port map (
 	CN1_B		=> ssg_cn1_b,
 	CN1_C		=> ssg_cn1_c);
 
+U15: entity work.gs
+port map (
+	RESET		=> reset or not GS_ENA,
+	CLK		=> clk_28mhz,
+	CLKGS		=> clk_21mhz,
+	A			=> cpu_a_bus,
+	DI			=> cpu_do_bus,
+	DO			=> gs_do_bus,
+	WR_n		=> cpu_wr_n,
+	RD_n		=> cpu_rd_n,
+	IORQ_n	=> cpu_iorq_n,
+	M1_n		=> cpu_m1_n,
+	OUTA		=> gs_a,
+	OUTB		=> gs_b,
+	OUTC		=> gs_c,
+	OUTD		=> gs_d);
+
 -------------------------------------------------------------------------------
 -- Global
 -------------------------------------------------------------------------------
@@ -1380,6 +1415,7 @@ cpu_di_bus <=
 		sdr_do_bus when (cpu_mreq_n = '0' and cpu_rd_n = '0') else 	-- SDRAM
 		im2vect	when intack = '1' else
 		mc146818a_do_bus when (cpu_iorq_n = '0' and cpu_rd_n = '0' and port_bff7 = '1' and port_eff7_reg(7) = '1') else -- MC146818A
+		gs_do_bus when (GS_ENA = '1' and cpu_iorq_n = '0' and cpu_rd_n = '0' and cpu_a_bus(7 downto 4) = "1011" and cpu_a_bus(2 downto 0) = "011") else -- General Sound
 		ssg_cn0_bus when (cpu_iorq_n = '0' and cpu_rd_n = '0' and cpu_a_bus = "1111111111111101" and ssg_sel = '0') else -- TurboSound
 		ssg_cn1_bus when (cpu_iorq_n = '0' and cpu_rd_n = '0' and cpu_a_bus = "1111111111111101" and ssg_sel = '1') else
 		key_scancode when (cpu_iorq_n = '0' and cpu_rd_n = '0' and cpu_a_bus = X"0001") else
@@ -1420,7 +1456,7 @@ port_bff7 <= '1' when (cpu_iorq_n = '0' and cpu_a_bus = X"BFF7" and cpu_m1_n = '
 -- Z-Controller
 SD_CS_N <= sdcs_n_TS;
 
-SOUND_L <= ("000" & port_xxfe_reg(4) & "0000000") + ("000" & ssg_cn0_a) + ("000" & ssg_cn0_b) + ("000" & ssg_cn1_a) + ("000" & ssg_cn1_b) + ("000" & covox_a) + ("000" & covox_b);
+SOUND_L <= ("0000" & port_xxfe_reg(4) & "0000000000") + ("0000" & ssg_cn0_a & "000") + ("0000" & ssg_cn0_b & "000") + ("0000" & ssg_cn1_a & "000") + ("0000" & ssg_cn1_b & "000") + ("0000" & covox_a & "000") + ("0000" & covox_b & "000") + ("00" & gs_a) + ("00" & gs_b); -- + ("0000" & saa_out_l & "000");
-SOUND_R <= ("000" & port_xxfe_reg(4) & "0000000") + ("000" & ssg_cn0_c) + ("000" & ssg_cn0_b) + ("000" & ssg_cn1_c) + ("000" & ssg_cn1_b) + ("000" & covox_c) + ("000" & covox_d);
+SOUND_R <= ("0000" & port_xxfe_reg(4) & "0000000000") + ("0000" & ssg_cn0_c & "000") + ("0000" & ssg_cn0_b & "000") + ("0000" & ssg_cn1_c & "000") + ("0000" & ssg_cn1_b & "000") + ("0000" & covox_c & "000") + ("0000" & covox_d & "000") + ("00" & gs_c) + ("00" & gs_d); -- + ("0000" & saa_out_r & "000");
 
 end rtl;

sys/pll.qip

@@ -35,8 +35,8 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::NA==::TnVtYmVyIE9mIENsb2Nrcw=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::NQ==::TnVtYmVyIE9mIENsb2Nrcw=="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::NA==::bnVtYmVyX29mX2Nsb2Nrcw=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::NQ==::bnVtYmVyX29mX2Nsb2Nrcw=="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
@@ -89,11 +89,11 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::My41Nzk1NDU=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MjEuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MjM=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MjIzMzM4Mjk5NA==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::NTY=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
@@ -268,7 +268,7 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MjguMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MjEuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
@@ -317,8 +317,8 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTQgSGkgRGl2aWRlLEMtQ291bnRlci00IExvdyBEaXZpZGUsQy1Db3VudGVyLTQgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci00IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTQgSW5wdXQgU291cmNlLEMtQ291bnRlci00IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTQgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::MTIsMTEsMjU2LDI1NixmYWxzZSx0cnVlLHRydWUsZmFsc2UsNyw3LDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDcsNyw5LDcscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxMSwxMCwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDIxLDIxLDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDEsMjAsNDAwMCwxMTc2LjAgTUh6LDIyMzMzODI5OTQsbm9uZSxnbGIsbV9jbnQscGhfbXV4X2Nsayx0cnVl::UGFyYW1ldGVyIFZhbHVlcw=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::MTIsMTEsMjU2LDI1NixmYWxzZSx0cnVlLHRydWUsZmFsc2UsNyw3LDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDcsNyw5LDcscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxMSwxMCwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDIxLDIxLDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDI4LDI4LDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDEsMjAsNDAwMCwxMTc2LjAgTUh6LDIyMzMzODI5OTQsbm9uZSxnbGIsbV9jbnQscGhfbXV4X2Nsayx0cnVl::UGFyYW1ldGVyIFZhbHVlcw=="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"

sys/pll.v

@@ -12,6 +12,7 @@ module pll (
 		output wire  outclk_1, // outclk1.clk
 		output wire  outclk_2, // outclk2.clk
 		output wire  outclk_3, // outclk3.clk
+		output wire  outclk_4, // outclk4.clk
 		output wire  locked    //  locked.export
 	);
 
@@ -22,6 +23,7 @@ module pll (
 		.outclk_1 (outclk_1), // outclk1.clk
 		.outclk_2 (outclk_2), // outclk2.clk
 		.outclk_3 (outclk_3), // outclk3.clk
+		.outclk_4 (outclk_4), // outclk4.clk
 		.locked   (locked)    //  locked.export
 	);
 
@@ -67,7 +69,7 @@ endmodule
 // Retrieval info: 	<generic name="gui_dsm_out_sel" value="1st_order" />
 // Retrieval info: 	<generic name="gui_use_locked" value="true" />
 // Retrieval info: 	<generic name="gui_en_adv_params" value="false" />
-// Retrieval info: 	<generic name="gui_number_of_clocks" value="4" />
+// Retrieval info: 	<generic name="gui_number_of_clocks" value="5" />
 // Retrieval info: 	<generic name="gui_multiply_factor" value="1" />
 // Retrieval info: 	<generic name="gui_frac_multiply_factor" value="1" />
 // Retrieval info: 	<generic name="gui_divide_factor_n" value="1" />
@@ -108,7 +110,7 @@ endmodule
 // Retrieval info: 	<generic name="gui_actual_phase_shift3" value="0" />
 // Retrieval info: 	<generic name="gui_duty_cycle3" value="50" />
 // Retrieval info: 	<generic name="gui_cascade_counter4" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency4" value="3.579545" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency4" value="21.0" />
 // Retrieval info: 	<generic name="gui_divide_factor_c4" value="1" />
 // Retrieval info: 	<generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
 // Retrieval info: 	<generic name="gui_ps_units4" value="ps" />

sys/pll/pll_0002.v

@@ -19,6 +19,9 @@ module  pll_0002(
 	// interface 'outclk3'
 	output wire outclk_3,
 
+	// interface 'outclk4'
+	output wire outclk_4,
+
 	// interface 'locked'
 	output wire locked
 );
@@ -27,7 +30,7 @@ module  pll_0002(
 		.fractional_vco_multiplier("true"),
 		.reference_clock_frequency("50.0 MHz"),
 		.operation_mode("direct"),
-		.number_of_clocks(4),
+		.number_of_clocks(5),
 		.output_clock_frequency0("84.000000 MHz"),
 		.phase_shift0("0 ps"),
 		.duty_cycle0(50),
@@ -40,7 +43,7 @@ module  pll_0002(
 		.output_clock_frequency3("28.000000 MHz"),
 		.phase_shift3("0 ps"),
 		.duty_cycle3(50),
-		.output_clock_frequency4("0 MHz"),
+		.output_clock_frequency4("21.000000 MHz"),
 		.phase_shift4("0 ps"),
 		.duty_cycle4(50),
 		.output_clock_frequency5("0 MHz"),
@@ -86,7 +89,7 @@ module  pll_0002(
 		.pll_subtype("General")
 	) altera_pll_i (
 		.rst	(rst),
-		.outclk	({outclk_3, outclk_2, outclk_1, outclk_0}),
+		.outclk	({outclk_4, outclk_3, outclk_2, outclk_1, outclk_0}),
 		.locked	(locked),
 		.fboutclk	( ),
 		.fbclk	(1'b0),