mirror of
https://github.com/UzixLS/zxkit1-vga-scandoubler-firmware.git
synced 2025-07-18 14:51:19 +03:00
138 lines
3.2 KiB
Verilog
138 lines
3.2 KiB
Verilog
module scandoubler(
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input R_IN,
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input G_IN,
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input B_IN,
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input I_IN,
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input KSI_IN,
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input SSI_IN,
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input F14,
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input F14_2,
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output F28o,
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input F28,
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input INVERSE_RGBI,
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input INVERSE_KSI,
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input INVERSE_SSI,
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input INVERSE_F14MHZ,
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input VGA_SCART,
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input SET_FK_IN,
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input SET_FK_OUT,
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output reg R_VGA,
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output reg G_VGA,
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output reg B_VGA,
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output reg [2:0] I_VGA,
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output reg VSYNC_VGA,
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output reg HSYNC_VGA,
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output R_VIDEO,
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output G_VIDEO,
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output B_VIDEO,
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output [2:0] I_VIDEO,
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// output SYNC_VIDEO,
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output A17,
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output reg [16:0] A,
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output reg WE,
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output reg UB,
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output reg LB,
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output OE,
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inout [15:0] D
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);
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assign F28o = F14 ^ F14_2 ^ INVERSE_F14MHZ;
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reg ssi = 0, ksi0 = 0;
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wire ksi = ksi0 ^ ~KSI_IN;
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reg [7:0] ssi_cnt = 0;
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reg [7:0] ssi_len = 0;
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always @(posedge F28) begin
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if (SSI_IN == ksi0) begin
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ssi_cnt <= ssi_cnt + 1'b1;
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if (&ssi_cnt)
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ksi0 <= ~ksi0;
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ssi <= 1'b0;
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end
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else if (|ssi_cnt) begin
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ssi_len <= ssi_cnt;
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ssi_cnt <= 0;
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ssi <= 1'b1;
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end
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else begin
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ssi <= 1'b0;
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end
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end
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reg [11:0] hcnt_in = 0;
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reg [11:0] hlen = 0;
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reg even_line = 0;
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always @(posedge F28) begin
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if (ssi) begin
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even_line <= !even_line;
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hlen <= hcnt_in;
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hcnt_in <= 0;
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end
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else begin
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hcnt_in <= hcnt_in + 1'b1;
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end
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end
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reg [10:0] hcnt_vga = 0;
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always @(posedge F28) begin
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if (hcnt_vga == hlen[11:1] || ssi)
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hcnt_vga <= 0;
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else
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hcnt_vga <= hcnt_vga + 1'b1;
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end
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assign A17 = 1'b0;
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assign OE = 1'b0;
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wire write_pixel = ~hcnt_in[0];
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reg [3:0] ibgr_reg1, ibgr_reg2, ibgr_in;
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always @(posedge F28) begin
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WE <= ~write_pixel;
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LB <= write_pixel? hcnt_in[1] : 1'b0;
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UB <= write_pixel? ~hcnt_in[1] : 1'b0;
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A[16:0] <= write_pixel?
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{{6{1'b0}}, ~even_line, hcnt_in[11:2]} :
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{{6{1'b0}}, even_line, hcnt_vga[10:1]} ;
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ibgr_in = {4{~INVERSE_RGBI}} ^ {I_IN, B_IN, G_IN, R_IN};
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if (write_pixel) begin
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ibgr_reg1 <= D[3:0];
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ibgr_reg2 <= D[11:8];
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end
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else begin
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ibgr_reg1 <= ibgr_reg2;
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end
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end
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assign D[15:0] = !write_pixel?
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{{4{1'b0}}, ibgr_in, {4{1'b0}}, ibgr_in} :
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{16{1'bz}} ;
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wire HBLANK_VGA = (hcnt_vga < (ssi_len[7:1]+ssi_len[7:2]));
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always @(posedge F28) begin
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VSYNC_VGA <= ~INVERSE_KSI ^ ksi;
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HSYNC_VGA <= ~INVERSE_SSI ^ (hcnt_vga < ssi_len[7:1]);
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R_VGA <= !HBLANK_VGA && (ibgr_reg1[0] );
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G_VGA <= !HBLANK_VGA && (ibgr_reg1[1] );
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// G_VGA <= !HBLANK_VGA && hcnt_vga[1];
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B_VGA <= !HBLANK_VGA && (ibgr_reg1[2] );
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I_VGA[0] <= !HBLANK_VGA && (ibgr_reg1[0] & ibgr_reg1[3]);
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I_VGA[1] <= !HBLANK_VGA && (ibgr_reg1[1] & ibgr_reg1[3]);
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I_VGA[2] <= !HBLANK_VGA && (ibgr_reg1[2] & ibgr_reg1[3]);
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end
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assign R_VIDEO = R_IN ^ ~INVERSE_RGBI;
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assign G_VIDEO = G_IN ^ ~INVERSE_RGBI;
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assign B_VIDEO = B_IN ^ ~INVERSE_RGBI;
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assign I_VIDEO[0] = I_IN ^ ~INVERSE_RGBI;
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assign I_VIDEO[1] = I_IN ^ ~INVERSE_RGBI;
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assign I_VIDEO[2] = I_IN ^ ~INVERSE_RGBI;
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// assign SYNC_VIDEO = ~((SSI_IN ^ ~INVERSE_SSI) ^ (KSI_IN ^ ~INVERSE_KSI));
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endmodule
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