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https://github.com/UzixLS/zx-tsid.git
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61 lines
1.8 KiB
Plaintext
61 lines
1.8 KiB
Plaintext
#PACE: Start of Constraints generated by PACE
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#PACE: Start of PACE I/O Pin Assignments
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NET "a<0>" LOC = "p40" ;
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NET "a<10>" LOC = "p61" ;
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NET "a<11>" LOC = "p60" ;
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NET "a<12>" LOC = "p33" ;
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NET "a<14>" LOC = "p31" ;
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NET "a<15>" LOC = "p32" ;
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NET "a<1>" LOC = "p42" ;
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NET "a<2>" LOC = "p43" ;
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NET "a<3>" LOC = "p51" ;
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NET "a<4>" LOC = "p39" ;
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NET "a<5>" LOC = "p35" ;
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NET "a<6>" LOC = "p36" ;
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NET "a<7>" LOC = "p34" ;
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NET "a<8>" LOC = "p57" ;
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NET "a<9>" LOC = "p59" ;
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NET "cfg" LOC = "p27" ;
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NET "clk32" LOC = "p17" ;
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NET "clkcpu" LOC = "p15" ;
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NET "d<0>" LOC = "p44" ;
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NET "d<1>" LOC = "p45" ;
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NET "d<2>" LOC = "p46" ;
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NET "d<3>" LOC = "p49" ;
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NET "d<4>" LOC = "p58" ;
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NET "d<5>" LOC = "p48" ;
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NET "d<6>" LOC = "p47" ;
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NET "d<7>" LOC = "p38" ;
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NET "n_iorq" LOC = "p50" ;
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NET "n_iorqge" LOC = "p52" ;
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NET "n_rd" LOC = "p62" ;
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NET "n_wait" LOC = "p56" ;
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NET "n_wr" LOC = "p63" ;
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NET "rst_n" LOC = "p64" ;
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NET "sid_a<0>" LOC = "p8" ;
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NET "sid_a<1>" LOC = "p7" ;
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NET "sid_a<2>" LOC = "p4" ;
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NET "sid_a<3>" LOC = "p5" ;
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NET "sid_a<4>" LOC = "p2" ;
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NET "sid_clk" LOC = "p1" ;
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NET "sid_cs" LOC = "p6" ;
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NET "sid_d<0>" LOC = "p16" ;
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NET "sid_d<1>" LOC = "p9" ;
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NET "sid_d<2>" LOC = "p12" ;
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NET "sid_d<3>" LOC = "p19" ;
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NET "sid_d<4>" LOC = "p18" ;
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NET "sid_d<5>" LOC = "p20" ;
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NET "sid_d<6>" LOC = "p10" ;
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NET "sid_d<7>" LOC = "p11" ;
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NET "sid_rst" LOC = "p23" ;
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NET "sid_wr" LOC = "p13" ;
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#PACE: Start of PACE Area Constraints
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#PACE: Start of PACE Prohibit Constraints
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#PACE: End of Constraints generated by PACE
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#Created by Constraints Editor (xc9572xl-vq64-10) - 2020/12/09
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NET "clk32" TNM_NET = clk32;
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TIMESPEC TS_clk32 = PERIOD "clk32" 32 MHz HIGH 50%;
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NET "clkcpu" TNM_NET = clkcpu;
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TIMESPEC TS_clkcpu = PERIOD "clkcpu" 7 MHz HIGH 50%;
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