mirror of
https://github.com/UzixLS/zx-tsid.git
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86 lines
3.9 KiB
Plaintext
86 lines
3.9 KiB
Plaintext
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2013 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
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# Date created = 13:37:37 May 16, 2020
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# zx-tsid_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY MAX3000A
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set_global_assignment -name DEVICE "EPM3064ATC44-10"
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set_global_assignment -name TOP_LEVEL_ENTITY top
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:37:37 MAY 16, 2020"
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set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 44
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name SDC_FILE clocks.sdc
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set_global_assignment -name VERILOG_FILE top.v
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set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
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set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
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set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
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set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
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set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_location_assignment PIN_8 -to a[0]
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set_location_assignment PIN_10 -to d[7]
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set_location_assignment PIN_12 -to a15
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set_location_assignment PIN_13 -to a14
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set_location_assignment PIN_14 -to d[0]
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set_location_assignment PIN_15 -to d[1]
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set_location_assignment PIN_18 -to d[2]
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set_location_assignment PIN_19 -to dac
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set_location_assignment PIN_20 -to sid_clk
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set_location_assignment PIN_21 -to sid_cs
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set_location_assignment PIN_22 -to ay_clk
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set_location_assignment PIN_37 -to clk
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set_location_assignment PIN_23 -to ay_bdir
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set_location_assignment PIN_25 -to ay_bc1
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set_location_assignment PIN_27 -to n_m1
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set_location_assignment PIN_28 -to a[4]
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set_location_assignment PIN_31 -to a[5]
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set_location_assignment PIN_33 -to a[6]
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set_location_assignment PIN_34 -to a[7]
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set_location_assignment PIN_35 -to n_iorqge
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set_location_assignment PIN_38 -to n_wr
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set_location_assignment PIN_40 -to n_iorq
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set_location_assignment PIN_2 -to a[2]
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set_location_assignment PIN_3 -to d[5]
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set_location_assignment PIN_5 -to a[1]
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set_location_assignment PIN_6 -to d[6]
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set_location_assignment PIN_42 -to d[4]
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set_location_assignment PIN_43 -to a[3]
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set_location_assignment PIN_44 -to d[3]
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set_location_assignment PIN_39 -to n_rst |