# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
# Date created = 13:37:37  May 16, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		zx-tsid_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY MAX3000A
set_global_assignment -name DEVICE "EPM3064ATC44-10"
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:37:37  MAY 16, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 44
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name SDC_FILE clocks.sdc
set_global_assignment -name VERILOG_FILE top.v
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_8 -to a[0]
set_location_assignment PIN_10 -to d[7]
set_location_assignment PIN_12 -to a15
set_location_assignment PIN_13 -to a14
set_location_assignment PIN_14 -to d[0]
set_location_assignment PIN_15 -to d[1]
set_location_assignment PIN_18 -to d[2]
set_location_assignment PIN_19 -to dac
set_location_assignment PIN_20 -to sid_clk
set_location_assignment PIN_21 -to sid_cs
set_location_assignment PIN_22 -to ay_clk
set_location_assignment PIN_37 -to clk
set_location_assignment PIN_23 -to ay_bdir
set_location_assignment PIN_25 -to ay_bc1
set_location_assignment PIN_27 -to n_m1
set_location_assignment PIN_28 -to a[4]
set_location_assignment PIN_31 -to a[5]
set_location_assignment PIN_33 -to a[6]
set_location_assignment PIN_34 -to a[7]
set_location_assignment PIN_35 -to n_iorqge
set_location_assignment PIN_38 -to n_wr
set_location_assignment PIN_40 -to n_iorq
set_location_assignment PIN_2 -to a[2]
set_location_assignment PIN_3 -to d[5]
set_location_assignment PIN_5 -to a[1]
set_location_assignment PIN_6 -to d[6]
set_location_assignment PIN_42 -to d[4]
set_location_assignment PIN_43 -to a[3]
set_location_assignment PIN_44 -to d[3]
set_location_assignment PIN_39 -to n_rst