uzix/zx-tsid
1
0
Fork 0
mirror of https://github.com/UzixLS/zx-tsid.git synced 2025-07-19 07:11:16 +03:00
Code Issues Projects Releases Wiki Activity

cpld: fix ay

Browse Source
This commit is contained in:
UzixLS
2020-06-20 13:06:35 +03:00
parent 15ff6cea5b
commit 9af3c559fe
1 changed files with 19 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

43
cpld/top.v
View File

@ -1,8 +1,7 @@
`define AY_ENABLE `define AY_ENABLE
`define AY_TURBOSOUND_MODE
`define SID_ENABLE `define SID_ENABLE
`define DAC_ENABLE `define DAC_ENABLE
`define BEEPER_ENABLE //`define BEEPER_ENABLE
module top( module top(
input n_rst, input n_rst,
@ -30,12 +29,12 @@ wire ioreq = n_iorq == 0 && n_m1 == 1'b1;
/* SID */ /* SID */
`ifdef SID_ENABLE `ifdef SID_ENABLE
wire port_cf = a == 8'hCF; wire port_cf = a == 8'hCF;
always @(posedge clk) always @(negedge clk)
sid_cs <= ioreq && port_cf; sid_cs <= ioreq && port_cf;
reg [1:0] sid_clk0; reg [1:0] sid_clk0;
assign sid_clk = sid_clk0[1]; assign sid_clk = sid_clk0[1];
always @(posedge clk or negedge n_rst) begin always @(negedge clk or negedge n_rst) begin
if (!n_rst) if (!n_rst)
sid_clk0 <= 0; sid_clk0 <= 0;
else else
@ -52,29 +51,25 @@ always @* sid_cs <= 0;
/* AY */ /* AY */
`ifdef AY_ENABLE `ifdef AY_ENABLE
wire port_fffd = a15 == 1'b1 && a[1] == 0 ; wire port_bffd = a15 == 1'b1 && a[1] == 0 ;
wire port_bffd = a15 == 1'b1 && a14 == 1'b1 && a[1] == 0; wire port_fffd = a15 == 1'b1 && a14 == 1'b1 && a[1] == 0;
reg ay_sel; reg ay_sel;
always @(posedge clk or negedge n_rst) begin always @(negedge clk or negedge n_rst) begin
if (!n_rst) begin if (!n_rst) begin
ay_bc1 <= 0; ay_bc1 <= 0;
ay_bdir <= 0; ay_bdir <= 0;
`ifdef AY_TURBOSOUND_MODE ay_sel <= 1'b1;
ay_sel <= 0;
`else
ay_sel <= 1'b1;
`endif
end end
else begin else begin
ay_bc1 <= ioreq && port_bffd; if (ay_sel) begin
ay_bdir <= ioreq && port_fffd && n_wr == 1'b0; ay_bc1 <= ioreq && port_fffd;
`ifdef AY_TURBOSOUND_MODE ay_bdir <= ioreq && port_bffd && n_wr == 1'b0;
if (ioreq && port_fffd && n_wr == 1'b0 && d[7:3] == 5'b11111) end
ay_sel <= d[2:0] == 3'b001; if (ioreq && port_fffd && n_wr == 1'b0 && d[7:1] == 7'b1111111)
`endif ay_sel <= d[0] == 1'b0;
end end
end end
always @(posedge clk or negedge n_rst) begin always @(negedge clk or negedge n_rst) begin
if (!n_rst) if (!n_rst)
ay_clk <= 0; ay_clk <= 0;
else else
@ -95,7 +90,7 @@ always @* ay_bdir <= 0;
`ifdef BEEPER_ENABLE `ifdef BEEPER_ENABLE
wire port_fe = a[0] == 0; wire port_fe = a[0] == 0;
reg beeper, tape_out; reg beeper, tape_out;
always @(posedge clk or negedge n_rst) begin always @(negedge clk or negedge n_rst) begin
if (!n_rst) begin if (!n_rst) begin
beeper <= 1'b0; beeper <= 1'b0;
tape_out <= 1'b0; tape_out <= 1'b0;
@ -117,17 +112,17 @@ wire tape_out = 0;
/* COVOX */ /* COVOX */
reg [7:0] covox_data; reg [7:0] covox_data;
wire port_fb = a == 8'hFB; wire port_fb = a == 8'hFB;
always @(posedge clk or negedge n_rst) begin always @(negedge clk or negedge n_rst) begin
if (!n_rst) if (!n_rst)
covox_data <= 0; covox_data <= 0;
else if (ioreq && port_fb && n_wr == 0) else if (ioreq && port_fb && n_wr == 1'b0)
covox_data <= d; covox_data <= d;
end end
reg [8:0] dac_acc; reg [8:0] dac_acc;
assign dac = dac_acc[8]; assign dac = dac_acc[8];
wire [8:0] dac_acc_next = covox_data + {1'b0, beeper, tape_out, 5'b00000}; wire [8:0] dac_acc_next = covox_data + {1'b0, beeper, tape_out, 5'b00000};
always @(posedge clk or negedge n_rst) begin always @(negedge clk or negedge n_rst) begin
if (!n_rst) if (!n_rst)
dac_acc <= 0; dac_acc <= 0;
else else
@ -136,7 +131,7 @@ end
`else /* DAC_ENABLE */ `else /* DAC_ENABLE */
wire port_fb = 0; wire port_fb = 0;
assign dac <= 1'bz; assign dac = 1'bz;
`endif /* DAC_ENABLE */ `endif /* DAC_ENABLE */