fix compatibility with original ZX Spectrum 48K

cpld/rev.D/top.v

@@ -7,8 +7,8 @@ module top(
     input n_rd,
     input n_wr,
     input n_iorq,
-    output reg n_iorqge,
+    output n_iorqge,
-    output reg n_wait,
+    output reg n_wait = 1'bz,
 
     input cfg,
 
@@ -16,8 +16,8 @@ module top(
     inout [7:0] sid_d,
     output sid_clk,
     output sid_rst,
-    output reg sid_cs,
+    output reg sid_cs = 1'b1,
-    output reg sid_wr
+    output reg sid_wr = 1'b1
 );
 
 assign sid_rst = rst_n;
@@ -113,10 +113,9 @@ end
 
 assign sid_d = (sid_wr == 1'b0)? sid_d_latch : 8'bzzzzzzzz;
 
-always @(negedge clkcpu)
+assign d = (port_cf && n_iorq == 1'b0 && n_rd == 1'b0 && n_wr == 1'b1)? sid_d_latch : 8'bzzzzzzzz;
-    n_iorqge <= (port_cf)? 1'b1 : 1'bz;
 
-assign d = (port_cf && n_iorq == 1'b0 && n_rd == 1'b0)? sid_d_latch : 8'bzzzzzzzz;
+assign n_iorqge = 1'bz;
 
 
 endmodule

cpld/rev.D/zx-tsid.xise

@@ -75,7 +75,7 @@
     <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
     <property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
     <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
-    <property xil_pn:name="I/O Pin Termination" xil_pn:value="Keeper" xil_pn:valueState="default"/>
+    <property xil_pn:name="I/O Pin Termination" xil_pn:value="Float" xil_pn:valueState="non-default"/>
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
     <property xil_pn:name="Implementation Top" xil_pn:value="Module|top" xil_pn:valueState="non-default"/>