uzix/zx-tsid
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fix compatibility with original ZX Spectrum 48K

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UzixLS
2021-07-24 12:11:51 +03:00
parent d2a15630f7
commit 3b100a4f68
4 changed files with 1928 additions and 1929 deletions
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13
cpld/rev.D/top.v
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@ -7,8 +7,8 @@ module top(
input n_rd,
input n_wr,
input n_iorq,
output reg n_iorqge,
output reg n_wait,
output n_iorqge,
output reg n_wait = 1'bz,
input cfg,
@ -16,8 +16,8 @@ module top(
inout [7:0] sid_d,
output sid_clk,
output sid_rst,
output reg sid_cs,
output reg sid_wr
output reg sid_cs = 1'b1,
output reg sid_wr = 1'b1
);
assign sid_rst = rst_n;
@ -113,10 +113,9 @@ end
assign sid_d = (sid_wr == 1'b0)? sid_d_latch : 8'bzzzzzzzz;
always @(negedge clkcpu)
n_iorqge <= (port_cf)? 1'b1 : 1'bz;
assign d = (port_cf && n_iorq == 1'b0 && n_rd == 1'b0 && n_wr == 1'b1)? sid_d_latch : 8'bzzzzzzzz;
assign d = (port_cf && n_iorq == 1'b0 && n_rd == 1'b0)? sid_d_latch : 8'bzzzzzzzz;
assign n_iorqge = 1'bz;
endmodule