From 1d2a73b91d6fe890c762e4d004a6cc4da3ff81c2 Mon Sep 17 00:00:00 2001 From: UzixLS Date: Tue, 16 Mar 2021 22:19:08 +0300 Subject: [PATCH] add cpld firmware for pcb rev.C --- cpld/.gitignore | 70 +++++++ cpld/rev.C/top.ucf | 59 ++++++ cpld/rev.C/top.v | 45 ++++ cpld/rev.C/zx-tsid.xise | 240 ++++++++++++++++++++++ out/{zx-tsid.rev.A.pof => cpld.rev.A.pof} | Bin 5 files changed, 414 insertions(+) create mode 100644 cpld/.gitignore create mode 100644 cpld/rev.C/top.ucf create mode 100644 cpld/rev.C/top.v create mode 100644 cpld/rev.C/zx-tsid.xise rename out/{zx-tsid.rev.A.pof => cpld.rev.A.pof} (100%) diff --git a/cpld/.gitignore b/cpld/.gitignore new file mode 100644 index 0000000..4aad693 --- /dev/null +++ b/cpld/.gitignore @@ -0,0 +1,70 @@ +# intermediate build files +*.bgn +*.bit +*.bld +*.cmd_log +*.drc +*.ll +*.lso +*.msd +*.msk +*.ncd +*.ngc +*.ngd +*.ngr +*.pad +*.par +*.pcf +*.prj +*.ptwx +*.rbb +*.rbd +*.stx +*.syr +*.twr +*.twx +*.unroutes +*.ut +*.xpi +*.xst +*_bitgen.xwbt +*_envsettings.html +*_map.map +*_map.mrp +*_map.ngm +*_map.xrpt +*_ngdbuild.xrpt +*_pad.csv +*_pad.txt +*_par.xrpt +*_summary.html +*_summary.xml +*_usage.xml +*_xst.xrpt + +# iMPACT generated files +_impactbatch.log +impact.xsl +impact_impact.xwbt +ise_impact.cmd +webtalk_impact.xml +_impact.cmd +_impact.log + +# Core Generator generated files +xaw2verilog.log + +# project-wide generated files +*.gise +par_usage_statistics.html +usage_statistics_webtalk.html +webtalk.log +webtalk_pn.xml + +# generated folders +iseconfig/ +xlnx_auto_0_xdb/ +xst/ +_ngo/ +_xmsgs/ +work/ diff --git a/cpld/rev.C/top.ucf b/cpld/rev.C/top.ucf new file mode 100644 index 0000000..8c30430 --- /dev/null +++ b/cpld/rev.C/top.ucf @@ -0,0 +1,59 @@ +#PACE: Start of Constraints generated by PACE +#PACE: Start of PACE I/O Pin Assignments +NET "a<0>" LOC = "p40" ; +NET "a<10>" LOC = "p61" ; +NET "a<11>" LOC = "p60" ; +NET "a<12>" LOC = "p33" ; +NET "a<14>" LOC = "p31" ; +NET "a<15>" LOC = "p32" ; +NET "a<1>" LOC = "p42" ; +NET "a<2>" LOC = "p43" ; +NET "a<3>" LOC = "p51" ; +NET "a<4>" LOC = "p39" ; +NET "a<5>" LOC = "p35" ; +NET "a<6>" LOC = "p36" ; +NET "a<7>" LOC = "p34" ; +NET "a<8>" LOC = "p57" ; +NET "a<9>" LOC = "p59" ; +NET "cfg" LOC = "p27" ; +NET "clk32" LOC = "p17" ; +NET "clkcpu" LOC = "p15" ; +NET "d<0>" LOC = "p44" ; +NET "d<1>" LOC = "p45" ; +NET "d<2>" LOC = "p46" ; +NET "d<3>" LOC = "p49" ; +NET "d<4>" LOC = "p58" ; +NET "d<5>" LOC = "p48" ; +NET "d<6>" LOC = "p47" ; +NET "d<7>" LOC = "p38" ; +NET "n_iorq" LOC = "p50" ; +NET "n_iorqge" LOC = "p52" ; +NET "n_rd" LOC = "p62" ; +NET "n_wr" LOC = "p63" ; +NET "rst_n" LOC = "p64" ; +NET "sid_a<0>" LOC = "p8" ; +NET "sid_a<1>" LOC = "p7" ; +NET "sid_a<2>" LOC = "p4" ; +NET "sid_a<3>" LOC = "p5" ; +NET "sid_a<4>" LOC = "p2" ; +NET "sid_clk" LOC = "p1" ; +NET "sid_cs" LOC = "p6" ; +NET "sid_d<0>" LOC = "p16" ; +NET "sid_d<1>" LOC = "p9" ; +NET "sid_d<2>" LOC = "p12" ; +NET "sid_d<3>" LOC = "p19" ; +NET "sid_d<4>" LOC = "p18" ; +NET "sid_d<5>" LOC = "p20" ; +NET "sid_d<6>" LOC = "p10" ; +NET "sid_d<7>" LOC = "p11" ; +NET "sid_rst" LOC = "p23" ; +NET "sid_wr" LOC = "p13" ; + +#PACE: Start of PACE Area Constraints +#PACE: Start of PACE Prohibit Constraints +#PACE: End of Constraints generated by PACE +#Created by Constraints Editor (xc9572xl-vq64-10) - 2020/12/09 +NET "clk32" TNM_NET = clk32; +TIMESPEC TS_clk32 = PERIOD "clk32" 32 MHz HIGH 50%; +NET "clkcpu" TNM_NET = clkcpu; +TIMESPEC TS_clkcpu = PERIOD "clkcpu" 7 MHz HIGH 50%; diff --git a/cpld/rev.C/top.v b/cpld/rev.C/top.v new file mode 100644 index 0000000..43f57b6 --- /dev/null +++ b/cpld/rev.C/top.v @@ -0,0 +1,45 @@ +module top( + input rst_n, + input clkcpu, + input clk32, + input [15:0] a, + inout [7:0] d, + input n_rd, + input n_wr, + input n_iorq, + output reg n_iorqge, + + input cfg, + + output reg [4:0] sid_a, + inout [7:0] sid_d, + output sid_clk, + output sid_rst, + output reg sid_cs, + output reg sid_wr +); + +wire port_cf = a[7:0] == 8'hCF; +always @(negedge clkcpu) begin + sid_cs <= (n_iorq == 1'b0 && port_cf && (n_wr == 1'b0 || n_rd == 1'b0))? 1'b0 : 1'b1; + sid_wr <= (n_iorq == 1'b0 && port_cf && n_wr == 1'b0)? 1'b0 : 1'b1; + if (port_cf) + sid_a <= a[12:8]; +end +assign sid_d = (sid_wr == 1'b0)? d : 8'bzzzzzzzz; + +assign sid_rst = rst_n; + +reg [4:0] sid_clk_cnt; +assign sid_clk = sid_clk_cnt[4]; +always @(posedge clk32) + sid_clk_cnt <= sid_clk_cnt + 1'b1; + + +always @(posedge clkcpu) + n_iorqge <= (port_cf)? 1'b1 : 1'bz; + +assign d = (port_cf && n_iorq == 1'b0 && n_rd == 1'b0)? sid_d : 8'bzzzzzzzz; + + +endmodule diff --git a/cpld/rev.C/zx-tsid.xise b/cpld/rev.C/zx-tsid.xise new file mode 100644 index 0000000..1ca880d --- /dev/null +++ b/cpld/rev.C/zx-tsid.xise @@ -0,0 +1,240 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/out/zx-tsid.rev.A.pof b/out/cpld.rev.A.pof similarity index 100% rename from out/zx-tsid.rev.A.pof rename to out/cpld.rev.A.pof