#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "a<0>"  LOC = "p40"  ;
NET "a<10>"  LOC = "p61"  ;
NET "a<11>"  LOC = "p60"  ;
NET "a<12>"  LOC = "p33"  ;
NET "a<14>"  LOC = "p31"  ;
NET "a<15>"  LOC = "p32"  ;
NET "a<1>"  LOC = "p42"  ;
NET "a<2>"  LOC = "p43"  ;
NET "a<3>"  LOC = "p51"  ;
NET "a<4>"  LOC = "p39"  ;
NET "a<5>"  LOC = "p35"  ;
NET "a<6>"  LOC = "p36"  ;
NET "a<7>"  LOC = "p34"  ;
NET "a<8>"  LOC = "p57"  ;
NET "a<9>"  LOC = "p59"  ;
NET "cfg"  LOC = "p27"  ;
NET "clk32"  LOC = "p17"  ;
NET "clkcpu"  LOC = "p15"  ;
NET "d<0>"  LOC = "p44"  ;
NET "d<1>"  LOC = "p45"  ;
NET "d<2>"  LOC = "p46"  ;
NET "d<3>"  LOC = "p49"  ;
NET "d<4>"  LOC = "p58"  ;
NET "d<5>"  LOC = "p48"  ;
NET "d<6>"  LOC = "p47"  ;
NET "d<7>"  LOC = "p38"  ;
NET "n_iorq"  LOC = "p50"  ;
NET "n_iorqge"  LOC = "p52"  ;
NET "n_rd"  LOC = "p63"  ;
NET "n_wait" LOC = "p56" ;
NET "n_wr"  LOC = "p62"  ;
NET "rst_n"  LOC = "p64"  ;
NET "sid_a<0>"  LOC = "p8"  ;
NET "sid_a<1>"  LOC = "p7"  ;
NET "sid_a<2>"  LOC = "p4"  ;
NET "sid_a<3>"  LOC = "p5"  ;
NET "sid_a<4>"  LOC = "p2"  ;
NET "sid_clk"  LOC = "p1"  ;
NET "sid_cs"  LOC = "p6"  ;
NET "sid_d<0>"  LOC = "p16"  ;
NET "sid_d<1>"  LOC = "p9"  ;
NET "sid_d<2>"  LOC = "p12"  ;
NET "sid_d<3>"  LOC = "p19"  ;
NET "sid_d<4>"  LOC = "p18"  ;
NET "sid_d<5>"  LOC = "p20"  ;
NET "sid_d<6>"  LOC = "p10"  ;
NET "sid_d<7>"  LOC = "p11"  ;
NET "sid_rst"  LOC = "p23"  ;
NET "sid_wr"  LOC = "p13"  ;

#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
#Created by Constraints Editor (xc9572xl-vq64-10) - 2020/12/09
NET "clk32" TNM_NET = clk32;
TIMESPEC TS_clk32 = PERIOD "clk32" 32 MHz HIGH 50%;
NET "clkcpu" TNM_NET = clkcpu;
TIMESPEC TS_clkcpu = PERIOD "clkcpu" 7 MHz HIGH 50%;
