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https://github.com/UzixLS/zx-sizif-xxs.git
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e33bd97a7e
New one is borrowed from Speccy 2010 project. It's have a much, much better output quality in price of increased FPGA resources usage.
11 lines
503 B
Tcl
Executable File
11 lines
503 B
Tcl
Executable File
create_clock -period 28MHz -name {clk28} [get_ports {clk_in}]
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create_generated_clock -name {clkcpu} -divide_by 2 -source [get_ports {clk_in}] [get_registers {cpucontrol:cpucontrol0|clkcpu}]
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create_generated_clock -name {hc0[1]} -divide_by 4 -source [get_ports {clk_in}] [get_registers {screen:screen0|hc0[1]}]
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derive_pll_clocks
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derive_clocks -period 14MHz
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set_multicycle_path -from {vencode:*|*} -to {vencode:*|*} -setup 4
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set_multicycle_path -from {vencode:*|*} -to {vencode:*|*} -hold 3
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