uzix/zx-sizif-xxs
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zx-sizif-xxs/fpga
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UzixLS cbe3e50b55 disable +3 ports by default to improve compatibility
2021-05-07 13:11:10 +03:00
..
rtl
disable +3 ports by default to improve compatibility
2021-05-07 13:11:10 +03:00
syn
add testbench
2021-05-06 13:08:06 +03:00
tb
minor testbench update
2021-05-06 18:57:36 +03:00