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zx-sizif-xxs/fpga/rtl/common.sv
Eugene Lozovoy c8d83ac5c1 refactor memory controller
Also this commit fixes ula+ io contention for classic timings. This
affects ham256.tap.
2024-01-08 20:15:34 +03:00

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484 B
Systemverilog
Executable File

package common;
typedef enum { MACHINE_S48, MACHINE_S128, MACHINE_S3, MACHINE_PENT } machine_t;
typedef enum { TURBO_NONE, TURBO_4, TURBO_5, TURBO_7, TURBO_14 } turbo_t;
typedef enum { PANNING_MONO, PANNING_ABC, PANNING_ACB } panning_t;
endpackage
interface cpu_bus();
reg [15:0] a_raw;
reg [15:0] a;
reg [7:0] d;
reg iorq;
reg mreq;
reg m1;
reg rfsh;
reg rd;
reg wr;
reg ioreq;
reg memreq;
reg memreq_rise;
endinterface