uzix/zx-sizif-xxs
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c4b3ef2ae9f4c7e559c9a6d6427d24da194eca69
zx-sizif-xxs/fpga/syn
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Eugene Lozovoy c4b3ef2ae9 add pcb zero rev.A
2022-07-01 21:36:17 +03:00
..
ip
replace composite video output implementation
2021-11-15 22:57:36 +03:00
clocks.sdc
replace composite video output implementation
2021-11-15 22:57:36 +03:00
Makefile
fix fpga makefile report target
2022-06-26 19:51:37 +03:00
rev_A.qsf
[minor] refactor fpga project
2021-11-18 20:38:14 +03:00
rev_B.qsf
add pcb rev.B
2022-02-19 20:10:56 +03:00
rev_zero_A.qsf
add pcb zero rev.A
2022-07-01 21:36:17 +03:00
sof2jic.cof
fpga: wip
2021-05-03 21:31:30 +03:00
zx_ula.qpf
add pcb zero rev.A
2022-07-01 21:36:17 +03:00