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https://github.com/UzixLS/zx-sizif-xxs.git
synced 2025-07-19 07:11:28 +03:00
524 lines
11 KiB
Systemverilog
Executable File
524 lines
11 KiB
Systemverilog
Executable File
import common::*;
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module zx_ula(
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input clk_in,
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output reg n_rstcpu,
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output reg clkcpu,
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inout [18:0] va,
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inout [7:0] vd,
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input [15:13] a,
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output n_vrd,
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output n_vwr,
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input n_rd,
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input n_wr,
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input n_mreq,
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input n_iorq,
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input n_m1,
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input n_rfsh,
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output reg n_int,
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output n_nmi,
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output [7:0] composite,
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input [1:0] reserv,
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output snd_l,
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output snd_r,
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input ps2_clk,
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input ps2_dat,
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input sd_cd,
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input sd_miso_tape_in,
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output sd_mosi_tape_out,
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output reg sd_sck,
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output reg sd_cs
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);
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/* CLOCK */
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wire clk28 = clk_in;
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wire clk168;
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wire rst_n;
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pll pll0(.inclk0(clk_in), .c0(clk168), .locked(rst_n));
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reg [1:0] clk168_en42_cnt = 0;
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reg clk168_en42;
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always @(posedge clk168) begin
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clk168_en42 <= clk168_en42_cnt == 2'b00;
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clk168_en42_cnt <= clk168_en42_cnt + 1'b1;
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end
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/* SHARED DEFINITIONS */
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machine_t machine;
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turbo_t turbo;
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wire ps2_key_reset, ps2_key_pause;
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wire [2:0] border;
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wire magic_reboot, magic_beeper;
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wire up_active;
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wire clkwait;
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wire [2:0] rampage128;
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wire div_wait;
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wire init_done;
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wire screen_fetch, screen_fetch_next;
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/* CPU BUS */
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cpu_bus bus();
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reg bus_memreq, bus_ioreq;
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always @(posedge clk28 or negedge rst_n) begin
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if (!rst_n) begin
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bus_ioreq <= 0;
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bus_memreq <= 0;
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end
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else if (!screen_fetch && !screen_fetch_next) begin
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bus.a_reg <= bus.a;
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bus.d_reg <= bus.d;
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bus_ioreq <= n_iorq == 1'b0 && n_m1 == 1'b1;
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bus_memreq <= n_mreq == 1'b0;
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end
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else begin
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if (n_iorq)
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bus_ioreq <= 0;
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if (n_mreq)
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bus_memreq <= 0;
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end
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end
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assign bus.a = {a[15:13], va[12:0]};
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assign bus.d = vd;
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assign bus.iorq = ~n_iorq;
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assign bus.mreq = ~n_mreq;
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assign bus.m1 = ~n_m1;
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assign bus.rfsh = ~n_rfsh;
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assign bus.rd = ~n_rd;
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assign bus.wr = ~n_wr;
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assign bus.ioreq = bus_ioreq & ~n_iorq;
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assign bus.memreq = bus_memreq & ~n_mreq;
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/* RESET */
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reg usrrst_n = 0;
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always @(posedge clk28) begin
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usrrst_n <= (!rst_n || ps2_key_reset || magic_reboot)? 1'b0 : 1'b1;
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end
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/* SCREEN CONTROLLER */
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wire blink;
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wire [2:0] screen_border = {border[2] ^ ~sd_cs, border[1] ^ magic_beeper, border[0]};
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wire [5:0] r, g, b;
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wire hsync, vsync, csync0;
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wire screen_contention, port_ff_active;
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wire [14:0] screen_addr;
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wire [5:0] up_ink_addr, up_paper_addr;
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wire [7:0] up_ink, up_paper;
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wire [8:0] vc, hc;
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wire [7:0] port_ff_data;
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wire clk14, clk7, clk35, ck14, ck7, ck35;
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screen screen0(
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.rst_n(usrrst_n),
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.clk28(clk28),
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.machine(machine),
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.border(screen_border),
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.r(r),
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.g(g),
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.b(b),
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.csync(csync0),
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.vsync(vsync),
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.hsync(hsync),
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.fetch_allow((!bus.iorq && !bus.mreq && !bus.m1) || bus.rfsh || clkwait),
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.fetch(screen_fetch),
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.addr(screen_addr),
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.fetch_next(screen_fetch_next),
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.fetch_data(bus.d),
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.up_en(up_active),
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.up_ink_addr(up_ink_addr),
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.up_paper_addr(up_paper_addr),
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.up_ink(up_ink),
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.up_paper(up_paper),
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.contention(screen_contention),
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.blink(blink),
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.port_ff_active(port_ff_active),
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.port_ff_data(port_ff_data),
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.vc_out(vc),
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.hc_out(hc),
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.clk14(clk14),
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.clk7(clk7),
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.clk35(clk35),
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.ck14(ck14),
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.ck7(ck7),
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.ck35(ck35)
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);
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/* VIDEO OUTPUT */
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vencode vencode(
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.clk(clk168),
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.clk_en(clk168_en42),
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.videoR(r),
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.videoG(g),
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.videoB(b),
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.videoHS_n(hsync),
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.videoVS_n(vsync),
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.videoPS_n(csync0),
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.videoV(composite)
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);
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/* PS/2 KEYBOARD */
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wire [4:0] ps2_kd;
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wire ps2_key_magic;
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wire ps2_joy_up, ps2_joy_down, ps2_joy_left, ps2_joy_right, ps2_joy_fire;
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ps2 #(.CLK_FREQ(28_000_000)) ps2_0(
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.rst_n(rst_n),
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.clk(clk28),
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.ps2_clk_in(ps2_clk),
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.ps2_dat_in(ps2_dat),
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.zxkb_addr(bus.a_reg[15:8]),
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.zxkb_data(ps2_kd),
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.key_magic(ps2_key_magic),
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.key_reset(ps2_key_reset),
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.key_pause(ps2_key_pause),
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.joy_up(ps2_joy_up),
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.joy_down(ps2_joy_down),
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.joy_left(ps2_joy_left),
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.joy_right(ps2_joy_right),
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.joy_fire(ps2_joy_fire)
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);
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/* CPU CONTROLLER */
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wire n_int_next, clkcpu_ck, snow;
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cpucontrol cpucontrol0(
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.rst_n(usrrst_n),
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.clk28(clk28),
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.clk14(clk14),
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.clk7(clk7),
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.clk35(clk35),
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.ck14(ck14),
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.ck7(ck7),
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.bus(bus),
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.vc(vc),
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.hc(hc),
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.rampage128(rampage128),
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.machine(machine),
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.screen_contention(screen_contention),
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.turbo(turbo),
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.ext_wait_cycle(div_wait || up_active),
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.init_done_in(init_done),
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.n_rstcpu(n_rstcpu),
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.clkcpu(clkcpu),
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.clkcpu_ck(clkcpu_ck),
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.clkwait(clkwait),
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.n_int(n_int),
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.n_int_next(n_int_next),
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.snow(snow)
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);
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/* MAGIC */
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wire div_automap;
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wire [7:0] magic_dout;
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wire magic_dout_active;
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wire magic_mode, magic_map;
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wire joy_sinclair, up_en, ay_en, covox_en, soundrive_en;
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panning_t panning;
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divmmc_t divmmc_en;
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magic magic0(
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.rst_n(n_rstcpu),
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.clk28(clk28),
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.bus(bus),
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.d_out(magic_dout),
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.d_out_active(magic_dout_active),
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.n_int(n_int),
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.n_int_next(n_int_next),
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.n_nmi(n_nmi),
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.magic_button(ps2_key_magic),
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.pause_button(ps2_key_pause),
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.sd_cd(sd_cd),
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.div_automap(div_automap),
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.magic_mode(magic_mode),
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.magic_map(magic_map),
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.magic_reboot(magic_reboot),
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.magic_beeper(magic_beeper),
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.machine(machine),
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.turbo(turbo),
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.joy_sinclair(joy_sinclair),
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.panning(panning),
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.divmmc_en(divmmc_en),
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.ulaplus_en(up_en),
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.ay_en(ay_en),
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.covox_en(covox_en),
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.soundrive_en(soundrive_en)
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);
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/* PORTS */
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wire [7:0] ports_dout;
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wire ports_dout_active;
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wire beeper, tape_out;
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wire screenpage;
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wire rompage128;
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wire [2:0] rampage_ext;
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wire [2:0] port_1ffd;
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wire [4:0] port_dffd;
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ports ports0 (
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.rst_n(n_rstcpu),
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.clk28(clk28),
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.bus(bus),
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.d_out(ports_dout),
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.d_out_active(ports_dout_active),
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.en_kempston(!joy_sinclair),
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.en_sinclair(joy_sinclair),
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.machine(machine),
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.port_ff_active(port_ff_active),
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.port_ff_data(port_ff_data),
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.kd(ps2_kd),
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.kempston_data({3'b000, ps2_joy_fire, ps2_joy_up, ps2_joy_down, ps2_joy_left, ps2_joy_right}),
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.magic_map(magic_map),
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.tape_in(sd_miso_tape_in),
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.tape_out(tape_out),
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.beeper(beeper),
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.border(border),
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.screenpage(screenpage),
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.rompage128(rompage128),
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.rampage128(rampage128),
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.rampage_ext(rampage_ext),
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.port_1ffd(port_1ffd),
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.port_dffd(port_dffd)
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);
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/* AY TURBOSOUND */
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wire turbosound_dout_active;
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wire [7:0] turbosound_dout;
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wire [7:0] ay_a0, ay_b0, ay_c0, ay_a1, ay_b1, ay_c1;
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turbosound turbosound0(
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.rst_n(n_rstcpu),
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.clk28(clk28),
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.ck35(ck35),
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.en(ay_en),
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.en_ts(1'b1),
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.bus(bus),
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.d_out(turbosound_dout),
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.d_out_active(turbosound_dout_active),
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.ay_a0(ay_a0),
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.ay_b0(ay_b0),
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.ay_c0(ay_c0),
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.ay_a1(ay_a1),
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.ay_b1(ay_b1),
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.ay_c1(ay_c1)
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);
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/* COVOX & SOUNDRIVE */
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wire [7:0] soundrive_l0, soundrive_l1, soundrive_r0, soundrive_r1;
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soundrive soundrive0(
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.rst_n(usrrst_n),
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.clk28(clk28),
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.en_covox(covox_en),
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.en_soundrive(soundrive_en),
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.bus(bus),
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.ch_l0(soundrive_l0),
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.ch_l1(soundrive_l1),
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.ch_r0(soundrive_r0),
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.ch_r1(soundrive_r1)
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);
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/* SOUND MIXER */
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mixer mixer0(
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.rst_n(usrrst_n),
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.clk28(clk28),
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.beeper(beeper ^ magic_beeper),
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.tape_out(tape_out),
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.tape_in(sd_miso_tape_in),
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.ay_a0(ay_a0),
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.ay_b0(ay_b0),
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.ay_c0(ay_c0),
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.ay_a1(ay_a1),
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.ay_b1(ay_b1),
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.ay_c1(ay_c1),
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.sd_l0(soundrive_l0),
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.sd_l1(soundrive_l1),
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.sd_r0(soundrive_r0),
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.sd_r1(soundrive_r1),
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.ay_acb(panning == PANNING_ACB),
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.mono(panning == PANNING_MONO),
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.dac_l(snd_l),
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.dac_r(snd_r)
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);
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/* DIVMMC */
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wire div_map, div_ram, div_ramwr_mask, div_dout_active;
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wire [7:0] div_dout;
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wire [3:0] div_page;
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wire sd_mosi0;
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divmmc divmmc0(
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.rst_n(n_rstcpu),
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.clk28(clk28),
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.ck14(ck14),
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.ck7(ck7),
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.en(divmmc_en == DIVMMC_ON || divmmc_en == DIVMMC_NOOS),
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.en_hooks(divmmc_en == DIVMMC_ON),
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.bus(bus),
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.d_out(div_dout),
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.d_out_active(div_dout_active),
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.sd_miso(sd_miso_tape_in),
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.sd_mosi(sd_mosi0),
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.sd_sck(sd_sck),
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.sd_cs(sd_cs),
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.rammap(port_dffd[4] | port_1ffd[0]),
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.magic_mode(magic_mode),
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.magic_map(magic_map),
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.page(div_page),
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.map(div_map),
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.automap(div_automap),
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.ram(div_ram),
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.ramwr_mask(div_ramwr_mask),
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.cpuwait(div_wait)
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);
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assign sd_mosi_tape_out = (divmmc_en == DIVMMC_OFF)? tape_out : sd_mosi0;
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/* ULAPLUS */
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wire up_dout_active;
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wire [7:0] up_dout;
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ulaplus ulaplus0(
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.rst_n(n_rstcpu),
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.clk28(clk28),
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.en(up_en),
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.bus(bus),
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.d_out(up_dout),
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.d_out_active(up_dout_active),
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.active(up_active),
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.ink_addr(up_ink_addr),
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.paper_addr(up_paper_addr),
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.ink(up_ink),
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.paper(up_paper)
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);
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/* MEMORY INITIALIZER */
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wire rom2ram_clk = clk7;
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wire [16:0] rom2ram_ram_address, rom2ram_rom_address;
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wire [7:0] rom2ram_datain, rom2ram_dataout;
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wire rom2ram_rom_rden;
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wire rom2ram_rom_data_ready;
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wire rom2ram_ram_wren;
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wire rom2ram_active;
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assign init_done = !rom2ram_active;
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reg [1:0] rom2ram_init;
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always @(posedge rom2ram_clk or negedge rst_n) begin
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if (!rst_n)
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rom2ram_init <= 0;
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else if (rom2ram_init != 3)
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rom2ram_init <= rom2ram_init + 1'b1;
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end
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rom2ram rom2ram0(
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.clock(rom2ram_clk),
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.init(rom2ram_init == 2),
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.datain(rom2ram_datain),
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.rom_data_ready(rom2ram_rom_data_ready),
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.init_busy(rom2ram_active),
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.rom_address(rom2ram_rom_address),
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.rom_rden(rom2ram_rom_rden),
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.ram_wren(rom2ram_ram_wren),
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.ram_address(rom2ram_ram_address),
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.dataout(rom2ram_dataout)
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);
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localparam ROM_OFFSET = 24'h13256;
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wire [23:0] asmi_addr = ROM_OFFSET + rom2ram_rom_address;
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asmi asmi0(
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.clkin(rom2ram_clk),
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.read(rom2ram_rom_rden),
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.rden(rom2ram_active),
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.addr(asmi_addr),
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.reset(!rst_n),
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.dataout(rom2ram_datain),
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.busy(),
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.data_valid(rom2ram_rom_data_ready)
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);
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/* MEMORY CONTROLLER */
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memcontrol memcontrol0(
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.clk28(clk28),
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.bus(bus),
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.va(va),
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.vd(vd),
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.n_vrd(n_vrd),
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.n_vwr(n_vwr),
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.machine(machine),
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.screenpage(screenpage),
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.screen_fetch(screen_fetch),
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.snow(snow),
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.screen_addr(screen_addr),
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.magic_map(magic_map),
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.rampage128(rampage128),
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.rompage128(rompage128),
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.port_1ffd(port_1ffd),
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.port_dffd(port_dffd),
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.rampage_ext(rampage_ext),
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.divmmc_en(divmmc_en != DIVMMC_OFF),
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.div_ram(div_ram),
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.div_map(div_map),
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.div_ramwr_mask(div_ramwr_mask),
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.div_page(div_page),
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.rom2ram_ram_address(rom2ram_ram_address),
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.rom2ram_ram_wren(rom2ram_ram_wren),
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.rom2ram_dataout(rom2ram_dataout),
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.magic_dout_active(magic_dout_active),
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.magic_dout(magic_dout),
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.up_dout_active(up_dout_active),
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.up_dout(up_dout),
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.div_dout_active(div_dout_active),
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.div_dout(div_dout),
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.turbosound_dout_active(turbosound_dout_active),
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.turbosound_dout(turbosound_dout),
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.ports_dout_active(ports_dout_active),
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.ports_dout(ports_dout)
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);
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endmodule
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