mirror of
https://github.com/UzixLS/zx-sizif-xxs.git
synced 2025-07-18 23:01:40 +03:00
319 lines
9.6 KiB
Systemverilog
319 lines
9.6 KiB
Systemverilog
import common::*;
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module video(
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input rst_n,
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input clk28,
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input machine_t machine,
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input turbo_t turbo,
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input [2:0] border,
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output reg [5:0] r,
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output reg [5:0] g,
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output reg [5:0] b,
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output reg vsync,
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output reg hsync,
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output reg csync,
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input read_allow,
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output reg read_req,
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output read_req_next,
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output [14:0] read_req_addr,
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input [7:0] read_data,
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output contention,
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output reg even_line,
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output port_ff_active,
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output [7:0] port_ff_data,
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input up_en,
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output [5:0] up_ink_addr,
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input [7:0] up_ink_data,
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output [5:0] up_paper_addr,
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input [7:0] up_paper_data,
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output [8:0] hc_out,
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output [8:0] vc_out,
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output clk14,
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output clk7,
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output clk35,
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output ck14,
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output ck7,
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output ck35
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);
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reg [8:0] vc;
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reg [10:0] hc0;
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wire [8:0] hc = hc0[10:2];
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assign vc_out = vc;
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assign hc_out = hc;
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assign clk14 = hc0[0];
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assign clk7 = hc0[1];
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assign clk35 = hc0[2];
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assign ck14 = hc0[0];
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assign ck7 = hc0[0] & hc0[1];
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assign ck35 = hc0[0] & hc0[1] & hc0[2];
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/* SYNC SIGNALS */
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localparam H_AREA = 256;
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localparam V_AREA = 192;
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localparam SCREEN_DELAY = 13;
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localparam H_LBORDER_S48 = 54 - SCREEN_DELAY;
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localparam H_RBORDER_S48 = 53 + SCREEN_DELAY;
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localparam H_BLANK1_S48 = 12;
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localparam H_SYNC_S48 = 33;
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localparam H_BLANK2_S48 = 40;
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localparam H_TOTAL_S48 = H_AREA + H_RBORDER_S48 + H_BLANK1_S48 + H_SYNC_S48 + H_BLANK2_S48 + H_LBORDER_S48;
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localparam V_BBORDER_S48 = 56;
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localparam V_SYNC_S48 = 8;
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localparam V_TBORDER_S48 = 56;
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localparam V_TOTAL_S48 = V_AREA + V_BBORDER_S48 + V_SYNC_S48 + V_TBORDER_S48;
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localparam H_LBORDER_S128 = 54 - SCREEN_DELAY;
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localparam H_RBORDER_S128 = 53 + SCREEN_DELAY;
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localparam H_BLANK1_S128 = 16;
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localparam H_SYNC_S128 = 33;
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localparam H_BLANK2_S128 = 44;
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localparam H_TOTAL_S128 = H_AREA + H_RBORDER_S128 + H_BLANK1_S128 + H_SYNC_S128 + H_BLANK2_S128 + H_LBORDER_S128;
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localparam V_BBORDER_S128 = 55;
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localparam V_SYNC_S128 = 8;
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localparam V_TBORDER_S128 = 56;
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localparam V_TOTAL_S128 = V_AREA + V_BBORDER_S128 + V_SYNC_S128 + V_TBORDER_S128;
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localparam H_LBORDER_PENT = 54 - SCREEN_DELAY;
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localparam H_RBORDER_PENT = 53 + SCREEN_DELAY;
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localparam H_BLANK1_PENT = 12;
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localparam H_SYNC_PENT = 33;
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localparam H_BLANK2_PENT = 40;
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localparam H_TOTAL_PENT = H_AREA + H_RBORDER_PENT + H_BLANK1_PENT + H_SYNC_PENT + H_BLANK2_PENT + H_LBORDER_PENT;
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localparam V_BBORDER_PENT = 56;
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localparam V_SYNC_PENT = 8;
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localparam V_TBORDER_PENT = 64;
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localparam V_TOTAL_PENT = V_AREA + V_BBORDER_PENT + V_SYNC_PENT + V_TBORDER_PENT;
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wire hc0_reset =
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(machine == MACHINE_S48)?
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hc0 == (H_TOTAL_S48<<2) - 1'b1 :
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(machine == MACHINE_S128 || machine == MACHINE_S3)?
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hc0 == (H_TOTAL_S128<<2) - 1'b1 :
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// Pentagon
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hc0 == (H_TOTAL_PENT<<2) - 1'b1 ;
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wire vc_reset =
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(machine == MACHINE_S48)?
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vc == V_TOTAL_S48 - 1'b1:
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(machine == MACHINE_S128 || machine == MACHINE_S3)?
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vc == V_TOTAL_S128 - 1'b1 :
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// Pentagon
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vc == V_TOTAL_PENT - 1'b1 ;
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wire hsync0 =
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(machine == MACHINE_S48)?
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(hc >= (H_AREA + H_RBORDER_S48 + H_BLANK1_S48)) && (hc < (H_AREA + H_RBORDER_S48 + H_BLANK1_S48 + H_SYNC_S48)) :
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(machine == MACHINE_S128 || machine == MACHINE_S3)?
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(hc >= (H_AREA + H_RBORDER_S128 + H_BLANK1_S128)) && (hc < (H_AREA + H_RBORDER_S128 + H_BLANK1_S128 + H_SYNC_S128)) :
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// Pentagon
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(hc >= (H_AREA + H_RBORDER_PENT + H_BLANK1_PENT)) && (hc < (H_AREA + H_RBORDER_PENT + H_BLANK1_PENT + H_SYNC_PENT)) ;
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wire vsync0 =
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(machine == MACHINE_S48)?
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(vc >= (V_AREA + V_BBORDER_S48)) && (vc < (V_AREA + V_BBORDER_S48 + V_SYNC_S48)) :
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(machine == MACHINE_S128 || machine == MACHINE_S3)?
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(vc >= (V_AREA + V_BBORDER_S128)) && (vc < (V_AREA + V_BBORDER_S128 + V_SYNC_S128)) :
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// Pentagon
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(vc >= (V_AREA + V_BBORDER_PENT)) && (vc < (V_AREA + V_BBORDER_PENT + V_SYNC_PENT)) ;
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wire blank =
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(machine == MACHINE_S48)?
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((vc >= (V_AREA + V_BBORDER_S48)) && (vc < (V_AREA + V_BBORDER_S48 + V_SYNC_S48))) ||
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((hc >= (H_AREA + H_RBORDER_S48)) &&
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(hc < (H_AREA + H_RBORDER_S48 + H_BLANK1_S48 + H_SYNC_S48 + H_BLANK2_S48))) :
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(machine == MACHINE_S128 || machine == MACHINE_S3)?
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((vc >= (V_AREA + V_BBORDER_S128)) && (vc < (V_AREA + V_BBORDER_S128 + V_SYNC_S128))) ||
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((hc >= (H_AREA + H_RBORDER_S128)) &&
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(hc < (H_AREA + H_RBORDER_S128 + H_BLANK1_S128 + H_SYNC_S128 + H_BLANK2_S128))) :
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// Pentagon
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((vc >= (V_AREA + V_BBORDER_PENT)) && (vc < (V_AREA + V_BBORDER_PENT + V_SYNC_PENT))) ||
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((hc >= (H_AREA + H_RBORDER_PENT)) &&
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(hc < (H_AREA + H_RBORDER_PENT + H_BLANK1_PENT + H_SYNC_PENT + H_BLANK2_PENT))) ;
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always @(posedge clk28 or negedge rst_n) begin
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if (!rst_n) begin
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hc0 <= 0;
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vc <= 0;
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end
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else if (hc0_reset) begin
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hc0 <= 0;
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if (vc_reset) begin
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vc <= 0;
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end
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else begin
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vc <= vc + 1'b1;
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end
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end
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else begin
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hc0 <= hc0 + 1'b1;
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end
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end
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reg [4:0] blink_cnt;
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wire blink = blink_cnt[$bits(blink_cnt)-1];
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always @(posedge clk28 or negedge rst_n) begin
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if (!rst_n)
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blink_cnt <= 0;
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else if (hc0_reset && vc_reset)
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blink_cnt <= blink_cnt + 1'b1;
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end
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reg hsync0_delayed;
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always @(posedge clk28)
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hsync0_delayed <= hsync0;
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always @(posedge clk28 or negedge rst_n) begin
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if (!rst_n)
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even_line <= 0;
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else if (hsync0 && !hsync0_delayed)
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even_line <= ~even_line;
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end
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/* SCREEN CONTROLLER */
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wire screen_show = (vc < V_AREA) && (hc0 >= (SCREEN_DELAY<<2) - 1) && (hc0 < ((H_AREA + SCREEN_DELAY)<<2) - 1);
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wire screen_update = hc0[4:0] == 5'b10011;
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wire border_update = (hc0[4:0] == 5'b10011) || (machine == MACHINE_PENT && ck7);
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wire bitmap_shift = hc0[1:0] == 2'b11;
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wire next_addr = hc0[4:0] == 5'b10000;
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reg screen_read, up_read;
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always @(posedge clk28 or negedge rst_n) begin
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if (!rst_n) begin
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screen_read <= 0;
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up_read <= 0;
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end
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else begin
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screen_read <= (vc < V_AREA) && (hc0 > 15) && (hc0 < (H_AREA<<2) + 17);
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up_read <= screen_read && (screen_update || up_read);
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end
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end
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reg [7:0] vaddr;
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reg [7:3] haddr;
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always @(posedge clk28 or negedge rst_n) begin
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if (!rst_n) begin
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vaddr <= 0;
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haddr <= 0;
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end
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else if (next_addr) begin
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vaddr <= vc[7:0];
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haddr <= hc[7:3];
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end
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end
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reg [7:0] bitmap, attr, bitmap_next, attr_next;
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reg [7:0] up_ink, up_paper;
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reg [1:0] read_cnt;
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localparam READ_CYCLES = 2'd2;
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assign read_req_next = screen_read && (read_allow || (|read_cnt && read_cnt != READ_CYCLES && turbo == TURBO_14));
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reg read_step;
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assign read_req_addr = (read_step == 1'd0)?
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{ 2'b10, vaddr[7:6], vaddr[2:0], vaddr[5:3], haddr[7:3] } :
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{ 5'b10110, vaddr[7:3], haddr[7:3] };
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assign up_ink_addr = up_read? { attr_next[7:6], 1'b0, attr_next[2:0] } : { 3'b0, border[2:0] };
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assign up_paper_addr = up_read? { attr_next[7:6], 1'b1, attr_next[5:3] } : { 3'b0, border[2:0] };
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always @(posedge clk28 or negedge rst_n) begin
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if (!rst_n) begin
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read_req <= 0;
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read_step <= 0;
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read_cnt <= 0;
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attr_next <= 0;
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bitmap_next <= 0;
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end
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else begin
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read_req <= read_req_next;
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if (read_cnt == READ_CYCLES) begin
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if (read_step == 1'd1)
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attr_next <= read_data;
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if (read_step == 1'd0)
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bitmap_next <= read_data;
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read_step <= read_step + 1'b1;
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read_cnt <= 0;
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end
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else if (read_req && read_req_next && !next_addr) begin
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read_cnt <= read_cnt + 1'b1;
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end
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else begin
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read_cnt <= 0;
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end
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end
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end
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always @(posedge clk28 or negedge rst_n) begin
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if (!rst_n) begin
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attr <= 0;
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bitmap <= 0;
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up_ink <= 0;
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up_paper <= 0;
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end
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else begin
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if (screen_show && screen_update)
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attr <= attr_next;
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else if (!screen_show && border_update)
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attr <= {2'b00, border[2:0], border[2:0]};
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if (screen_update)
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bitmap <= bitmap_next;
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else if (bitmap_shift)
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bitmap <= {bitmap[6:0], 1'b0};
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if (screen_update)
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up_ink <= up_ink_data;
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if (screen_update)
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up_paper <= up_paper_data;
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end
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end
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/* ATTRIBUTE PORT */
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wire port_ff_attr = (machine == MACHINE_PENT) || hc[3:1] == 3'h6 || hc[3:1] == 3'h0;
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wire port_ff_bitmap = (hc[3] && hc[1]);
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assign port_ff_active = screen_read && (port_ff_attr || port_ff_bitmap);
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assign port_ff_data =
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port_ff_attr? attr_next :
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port_ff_bitmap? bitmap_next :
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8'hFF;
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assign contention = (vc < V_AREA) && (hc < H_AREA) && (hc[2] || hc[3]);
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/* RGBS OUTPUT */
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wire pixel = bitmap[7];
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always @(posedge clk28) begin
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if (blank)
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{g, r, b} = 0;
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else if (up_en) begin
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g[5:3] = pixel? up_ink[7:5] : up_paper[7:5];
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r[5:3] = pixel? up_ink[4:2] : up_paper[4:2];
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b[5:4] = pixel? up_ink[1:0] : up_paper[1:0];
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g[2:0] = g[5:3];
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r[2:0] = r[5:3];
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b[3:0] = {b[5:4], b[5:4]};
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end
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else begin
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{g[5], r[5], b[5]} = (pixel ^ (attr[7] & blink))? attr[2:0] : attr[5:3];
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{g[4], r[4], b[4]} = attr[6]? {g[5], r[5], b[5]} : 3'b000;
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{g[3], r[3], b[3]} = {g[5], r[5], b[5]};
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{g[2], r[2], b[2]} = {g[4], r[4], b[4]};
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{g[1], r[1], b[1]} = {g[4], r[4], b[4]};
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{g[0], r[0], b[0]} = {g[5], r[5], b[5]};
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end
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end
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always @(posedge clk28) begin
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csync = ~(vsync0 ^ hsync0);
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vsync = ~vsync0;
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hsync = ~hsync0;
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end
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endmodule
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