mirror of
https://github.com/UzixLS/zx-sizif-xxs.git
synced 2025-07-19 07:11:28 +03:00
e33bd97a7e
New one is borrowed from Speccy 2010 project. It's have a much, much better output quality in price of increased FPGA resources usage.
195 lines
6.0 KiB
VHDL
195 lines
6.0 KiB
VHDL
-- Speccy 2010
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity vencode is
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generic(
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freq : integer := 42
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);
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port(
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clk : in std_logic;
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clk_en : in std_logic;
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-- Video Input
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videoR : in std_logic_vector(5 downto 0);
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videoG : in std_logic_vector(5 downto 0);
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videoB : in std_logic_vector(5 downto 0);
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videoHS_n : in std_logic;
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videoVS_n : in std_logic;
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videoPS_n : in std_logic;
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-- Video Output
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videoY : out std_logic_vector(7 downto 0);
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videoC : out std_logic_vector(7 downto 0);
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videoV : out std_logic_vector(7 downto 0)
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);
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end vencode;
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architecture rtl of vencode is
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signal carrier : unsigned(7 downto 0);
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signal vcounter : unsigned(8 downto 0);
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signal hcounter : unsigned(12 downto 0);
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signal burphase : unsigned(1 downto 0) := "00";
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signal window_v : std_logic;
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signal window_h : std_logic;
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signal window_c : std_logic;
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signal ivideoR : unsigned(5 downto 0);
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signal ivideoG : unsigned(5 downto 0);
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signal ivideoB : unsigned(5 downto 0);
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signal Y1 : unsigned(13 downto 0);
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signal Y2 : unsigned(13 downto 0);
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signal Y3 : unsigned(13 downto 0);
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signal U1 : unsigned(13 downto 0);
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signal U2 : unsigned(13 downto 0);
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signal U3 : unsigned(13 downto 0);
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signal V1 : unsigned(13 downto 0);
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signal V2 : unsigned(13 downto 0);
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signal V3 : unsigned(13 downto 0);
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signal burstUV : signed(13 downto 0);
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signal prevY : signed(13 downto 0);
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signal prevU : signed(13 downto 0);
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signal prevV : signed(13 downto 0);
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signal prevC : signed(23 downto 0);
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signal inSin : std_logic_vector(15 downto 0);
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signal inCos : std_logic_vector(15 downto 0);
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signal sin : signed(15 downto 0);
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signal cos : signed(15 downto 0);
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signal pcos : signed(15 downto 0);
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signal Um : signed(23 downto 0);
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signal Vm : signed(23 downto 0);
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signal Y : signed(7 downto 0);
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signal U : signed(7 downto 0);
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signal V : signed(7 downto 0);
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signal C : signed(7 downto 0);
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constant vref : signed(13 downto 0) := to_signed( 54, 8 ) & "000000";
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constant cent : signed(7 downto 0) := X"80";
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component vencode_sin_cos
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port(
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clk : in std_logic;
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phase : in std_logic_vector(7 downto 0);
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sinus : out std_logic_vector(15 downto 0);
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cosinus : out std_logic_vector(15 downto 0)
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);
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end component;
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begin
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process(clk, clk_en )
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variable carrierCounter : unsigned(15 downto 0);
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begin
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if ( clk'event and clk = '1' and clk_en = '1' ) then
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carrierCounter := carrierCounter + 157;
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if carrierCounter >= 6552 then
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carrier <= carrier + 28;
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carrierCounter := carrierCounter - 6552;
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else
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carrier <= carrier + 27;
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end if;
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end if;
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end process;
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vencode_sin_cos0 : vencode_sin_cos port map( clk, std_logic_vector( carrier ), inSin, inCos );
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sin <= signed( inSin( 15 downto 0 ) );
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cos <= signed( inCos( 15 downto 0 ) );
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pcos <= cos when burphase(0) = '0' else -cos;
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process(clk, clk_en )
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variable ivideoVS_n : std_logic;
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variable ivideoHS_n : std_logic;
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begin
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if ( clk'event and clk = '1' and clk_en = '1' ) then
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Y <= prevY( 13 downto 6 );
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Um <= U * sin;
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Vm <= V * pcos;
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videoY <= std_logic_vector( Y );
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videoC <= std_logic_vector( cent + C );
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videoV <= std_logic_vector( Y + C );
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ivideoR <= unsigned( videoR );
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ivideoG <= unsigned( videoG );
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ivideoB <= unsigned( videoB );
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if ( videoHS_n = '0' and ivideoHS_n = '1' ) then
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vcounter <= vcounter + 1;
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burphase <= burphase - 1;
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hcounter <= ( others => '0' );
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else
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hcounter <= hcounter + 1;
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end if;
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if (videoVS_n = '0' and ivideoVS_n = '1') then
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vcounter <= ( others => '0' );
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end if;
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if ( vcounter = ( 10 - 1 ) ) then
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window_v <= '1';
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elsif ( vcounter = ( 310 - 1 ) ) then
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window_v <= '0';
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end if;
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if (hcounter = ( integer( 10.5 * real( freq ) ) - 1 ) ) then
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window_h <= '1';
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elsif ( hcounter = ( integer( 62.5 * real( freq ) ) - 1 ) ) then
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window_h <= '0';
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end if;
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if ( hcounter = ( integer( 5.6 * real( freq ) ) - 1 ) ) then
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window_c <= '1';
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elsif ( hcounter = ( integer( 8.1 * real( freq ) ) - 1 ) ) then
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window_c <= '0';
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end if;
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ivideoVS_n := videoVS_n;
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ivideoHS_n := videoHS_n;
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end if;
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end process;
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-- Y = 0.299 R + 0.587 G + 0.114 B
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-- U = -0.147 R - 0.289 G + 0.436 B
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-- V = 0.615 R - 0.515 G - 0.100 B
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Y1 <= ( to_unsigned( 38, 8 ) * ivideoR );
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Y2 <= ( to_unsigned( 75, 8 ) * ivideoG );
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Y3 <= ( to_unsigned( 15, 8 ) * ivideoB );
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U1 <= ( to_unsigned( 19, 8 ) * ivideoR );
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U2 <= ( to_unsigned( 37, 8 ) * ivideoG );
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U3 <= ( to_unsigned( 56, 8 ) * ivideoB );
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V1 <= ( to_unsigned( 79, 8 ) * ivideoR );
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V2 <= ( to_unsigned( 66, 8 ) * ivideoG );
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V3 <= ( to_unsigned( 13, 8 ) * ivideoB );
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prevY <= to_signed( 0, 14 ) when videoPS_n = '0' else
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vref + signed( Y1 + Y2 + Y3 ) when ( window_h = '1' and window_v = '1' ) else
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vref;
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burstUV <= to_signed( 32, 8 ) & "000000" when ( window_c = '1' and window_v = '1' ) else
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( others => '0' );
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prevU <= signed( U3 - U1 - U2 ) when ( window_h = '1' and window_v = '1' ) else
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( -burstUV );
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prevV <= signed( V1 - V2 - V3 ) when ( window_h = '1' and window_v = '1' ) else
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( burstUV );
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U <= prevU( 13 downto 6 );
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V <= prevV( 13 downto 6 );
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prevC <= Um + Vm;
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C <= prevC( 23 downto 16 );
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end rtl;
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