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531 lines
17 KiB
Verilog
Executable File
531 lines
17 KiB
Verilog
Executable File
// megafunction wizard: %RAM initializer%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: ALTMEM_INIT
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// ============================================================
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// File Name: rom2ram.v
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// Megafunction Name(s):
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// ALTMEM_INIT
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//
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// Simulation Library Files(s):
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// lpm
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
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// ************************************************************
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//Copyright (C) 1991-2013 Altera Corporation
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Altera Program License
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//Subscription Agreement, Altera MegaCore Function License
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//Agreement, or other applicable license agreement, including,
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//without limitation, that your use is for the sole purpose of
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//programming logic devices manufactured by Altera and sold by
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//Altera or its authorized distributors. Please refer to the
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//applicable agreement for further details.
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//altmem_init CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone" INIT_TO_ZERO="NO" NUMWORDS=131072 PORT_ROM_DATA_READY="PORT_USED" ROM_READ_LATENCY=1 WIDTH=8 WIDTHAD=17 clock datain dataout init init_busy ram_address ram_wren rom_address rom_data_ready rom_rden
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//VERSION_BEGIN 13.0 cbx_altmem_init 2013:06:12:18:03:33:SJ cbx_altsyncram 2013:06:12:18:03:33:SJ cbx_cycloneii 2013:06:12:18:03:33:SJ cbx_lpm_add_sub 2013:06:12:18:03:33:SJ cbx_lpm_compare 2013:06:12:18:03:33:SJ cbx_lpm_counter 2013:06:12:18:03:33:SJ cbx_lpm_decode 2013:06:12:18:03:33:SJ cbx_lpm_mux 2013:06:12:18:03:33:SJ cbx_mgl 2013:06:12:18:33:59:SJ cbx_stratix 2013:06:12:18:03:33:SJ cbx_stratixii 2013:06:12:18:03:33:SJ cbx_stratixiii 2013:06:12:18:03:33:SJ cbx_stratixv 2013:06:12:18:03:33:SJ cbx_util_mgl 2013:06:12:18:03:33:SJ VERSION_END
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// altera message_off 10463
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//synthesis_resources = lpm_compare 2 lpm_counter 2 lut 32
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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//synopsys translate_on
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module rom2ram_meminit_qrn
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(
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clock,
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datain,
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dataout,
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init,
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init_busy,
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ram_address,
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ram_wren,
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rom_address,
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rom_data_ready,
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rom_rden) ;
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input clock;
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input [7:0] datain;
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output [7:0] dataout;
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input init;
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output init_busy;
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output [16:0] ram_address;
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output ram_wren;
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output [16:0] rom_address;
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input rom_data_ready;
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output rom_rden;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri0 [7:0] datain;
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tri0 rom_data_ready;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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reg [0:0] capture_init;
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reg [16:0] delay_addr;
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wire [16:0] wire_delay_addr_ena;
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reg [7:0] delay_data;
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wire [7:0] wire_delay_data_ena;
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reg [2:0] prev_state;
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wire [2:0] wire_state_reg_d;
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reg [2:0] state_reg;
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wire [2:0] wire_state_reg_sclr;
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wire [2:0] wire_state_reg_sload;
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wire wire_addr_cmpr_aeb;
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wire wire_addr_cmpr_alb;
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wire wire_wait_cmpr_aeb;
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wire wire_wait_cmpr_alb;
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wire [16:0] wire_addr_ctr_q;
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wire [0:0] wire_wait_ctr_q;
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wire [0:0] addrct_eq_numwords;
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wire [0:0] addrct_lt_numwords;
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wire clken;
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wire [7:0] dataout_w;
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wire [0:0] done_state;
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wire [0:0] idle_state;
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wire [0:0] ram_write_state;
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wire [0:0] reset_state_machine;
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wire [0:0] rom_addr_state;
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wire [0:0] rom_data_capture_state;
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wire [0:0] state_machine_clken;
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// synopsys translate_off
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initial
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capture_init = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (clken == 1'b1) capture_init <= ((init | capture_init) & (~ done_state));
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// synopsys translate_off
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initial
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delay_addr[0:0] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_addr_ena[0:0] == 1'b1) delay_addr[0:0] <= wire_addr_ctr_q[0:0];
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// synopsys translate_off
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initial
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delay_addr[1:1] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_addr_ena[1:1] == 1'b1) delay_addr[1:1] <= wire_addr_ctr_q[1:1];
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// synopsys translate_off
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initial
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delay_addr[2:2] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_addr_ena[2:2] == 1'b1) delay_addr[2:2] <= wire_addr_ctr_q[2:2];
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// synopsys translate_off
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initial
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delay_addr[3:3] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_addr_ena[3:3] == 1'b1) delay_addr[3:3] <= wire_addr_ctr_q[3:3];
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// synopsys translate_off
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initial
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delay_addr[4:4] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_addr_ena[4:4] == 1'b1) delay_addr[4:4] <= wire_addr_ctr_q[4:4];
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// synopsys translate_off
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initial
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delay_addr[5:5] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_addr_ena[5:5] == 1'b1) delay_addr[5:5] <= wire_addr_ctr_q[5:5];
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// synopsys translate_off
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initial
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delay_addr[6:6] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_addr_ena[6:6] == 1'b1) delay_addr[6:6] <= wire_addr_ctr_q[6:6];
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// synopsys translate_off
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initial
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delay_addr[7:7] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_addr_ena[7:7] == 1'b1) delay_addr[7:7] <= wire_addr_ctr_q[7:7];
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// synopsys translate_off
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initial
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delay_addr[8:8] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_addr_ena[8:8] == 1'b1) delay_addr[8:8] <= wire_addr_ctr_q[8:8];
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// synopsys translate_off
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initial
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delay_addr[9:9] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_addr_ena[9:9] == 1'b1) delay_addr[9:9] <= wire_addr_ctr_q[9:9];
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// synopsys translate_off
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initial
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delay_addr[10:10] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_addr_ena[10:10] == 1'b1) delay_addr[10:10] <= wire_addr_ctr_q[10:10];
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// synopsys translate_off
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initial
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delay_addr[11:11] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_addr_ena[11:11] == 1'b1) delay_addr[11:11] <= wire_addr_ctr_q[11:11];
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// synopsys translate_off
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initial
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delay_addr[12:12] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_addr_ena[12:12] == 1'b1) delay_addr[12:12] <= wire_addr_ctr_q[12:12];
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// synopsys translate_off
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initial
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delay_addr[13:13] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_addr_ena[13:13] == 1'b1) delay_addr[13:13] <= wire_addr_ctr_q[13:13];
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// synopsys translate_off
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initial
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delay_addr[14:14] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_addr_ena[14:14] == 1'b1) delay_addr[14:14] <= wire_addr_ctr_q[14:14];
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// synopsys translate_off
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initial
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delay_addr[15:15] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_addr_ena[15:15] == 1'b1) delay_addr[15:15] <= wire_addr_ctr_q[15:15];
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// synopsys translate_off
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initial
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delay_addr[16:16] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_addr_ena[16:16] == 1'b1) delay_addr[16:16] <= wire_addr_ctr_q[16:16];
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assign
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wire_delay_addr_ena = {17{(clken & rom_data_capture_state)}};
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// synopsys translate_off
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initial
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delay_data[0:0] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_data_ena[0:0] == 1'b1) delay_data[0:0] <= datain[0:0];
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// synopsys translate_off
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initial
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delay_data[1:1] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_data_ena[1:1] == 1'b1) delay_data[1:1] <= datain[1:1];
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// synopsys translate_off
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initial
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delay_data[2:2] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_data_ena[2:2] == 1'b1) delay_data[2:2] <= datain[2:2];
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// synopsys translate_off
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initial
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delay_data[3:3] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_data_ena[3:3] == 1'b1) delay_data[3:3] <= datain[3:3];
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// synopsys translate_off
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initial
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delay_data[4:4] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_data_ena[4:4] == 1'b1) delay_data[4:4] <= datain[4:4];
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// synopsys translate_off
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initial
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delay_data[5:5] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_data_ena[5:5] == 1'b1) delay_data[5:5] <= datain[5:5];
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// synopsys translate_off
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initial
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delay_data[6:6] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_data_ena[6:6] == 1'b1) delay_data[6:6] <= datain[6:6];
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// synopsys translate_off
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initial
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delay_data[7:7] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_data_ena[7:7] == 1'b1) delay_data[7:7] <= datain[7:7];
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assign
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wire_delay_data_ena = {8{(clken & rom_data_capture_state)}};
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// synopsys translate_off
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initial
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prev_state = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (clken == 1'b1) prev_state <= state_reg;
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// synopsys translate_off
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initial
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state_reg[0:0] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (state_machine_clken == 1'b1)
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if (wire_state_reg_sclr[0:0] == 1'b1) state_reg[0:0] <= 1'b0;
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else if (wire_state_reg_sload[0:0] == 1'b1) state_reg[0:0] <= 1;
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else state_reg[0:0] <= wire_state_reg_d[0:0];
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// synopsys translate_off
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initial
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state_reg[1:1] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (state_machine_clken == 1'b1)
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if (wire_state_reg_sclr[1:1] == 1'b1) state_reg[1:1] <= 1'b0;
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else if (wire_state_reg_sload[1:1] == 1'b1) state_reg[1:1] <= 1;
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else state_reg[1:1] <= wire_state_reg_d[1:1];
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// synopsys translate_off
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initial
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state_reg[2:2] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (state_machine_clken == 1'b1)
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if (wire_state_reg_sclr[2:2] == 1'b1) state_reg[2:2] <= 1'b0;
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else if (wire_state_reg_sload[2:2] == 1'b1) state_reg[2:2] <= 1;
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else state_reg[2:2] <= wire_state_reg_d[2:2];
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assign
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wire_state_reg_d = {(((~ state_reg[2]) & state_reg[1]) & state_reg[0]), ((~ state_reg[2]) & (state_reg[1] ^ state_reg[0])), ((~ state_reg[2]) & (~ state_reg[0]))};
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assign
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wire_state_reg_sclr = {{2{reset_state_machine}}, 1'b0},
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wire_state_reg_sload = {{2{1'b0}}, reset_state_machine};
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lpm_compare addr_cmpr
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(
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.aeb(wire_addr_cmpr_aeb),
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.agb(),
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.ageb(),
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.alb(wire_addr_cmpr_alb),
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.aleb(),
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.aneb(),
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.dataa(delay_addr),
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.datab({17{1'b1}})
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`ifndef FORMAL_VERIFICATION
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// synopsys translate_off
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`endif
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,
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.aclr(1'b0),
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.clken(1'b1),
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.clock(1'b0)
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`ifndef FORMAL_VERIFICATION
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// synopsys translate_on
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`endif
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);
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defparam
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addr_cmpr.lpm_width = 17,
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addr_cmpr.lpm_type = "lpm_compare";
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lpm_compare wait_cmpr
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(
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.aeb(wire_wait_cmpr_aeb),
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.agb(),
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.ageb(),
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.alb(wire_wait_cmpr_alb),
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.aleb(),
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.aneb(),
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.dataa(wire_wait_ctr_q),
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.datab(1'b0)
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`ifndef FORMAL_VERIFICATION
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// synopsys translate_off
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`endif
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,
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.aclr(1'b0),
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.clken(1'b1),
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.clock(1'b0)
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`ifndef FORMAL_VERIFICATION
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// synopsys translate_on
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`endif
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);
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defparam
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wait_cmpr.lpm_width = 1,
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wait_cmpr.lpm_type = "lpm_compare";
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lpm_counter addr_ctr
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(
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.clk_en(clken),
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.clock(clock),
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.cnt_en(ram_write_state),
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.cout(),
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.eq(),
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.q(wire_addr_ctr_q),
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.sclr(((~ state_reg[1]) & (~ state_reg[0])))
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`ifndef FORMAL_VERIFICATION
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// synopsys translate_off
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`endif
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,
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.aclr(1'b0),
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.aload(1'b0),
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.aset(1'b0),
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.cin(1'b1),
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.data({17{1'b0}}),
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.sload(1'b0),
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.sset(1'b0),
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.updown(1'b1)
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`ifndef FORMAL_VERIFICATION
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// synopsys translate_on
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`endif
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);
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defparam
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addr_ctr.lpm_direction = "UP",
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addr_ctr.lpm_modulus = 131072,
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addr_ctr.lpm_port_updown = "PORT_UNUSED",
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addr_ctr.lpm_width = 17,
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addr_ctr.lpm_type = "lpm_counter";
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lpm_counter wait_ctr
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(
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.clk_en(clken),
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.clock(clock),
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.cnt_en(rom_addr_state),
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.cout(),
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.eq(),
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.q(wire_wait_ctr_q),
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.sclr((~ rom_addr_state))
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`ifndef FORMAL_VERIFICATION
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// synopsys translate_off
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`endif
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,
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.aclr(1'b0),
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.aload(1'b0),
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.aset(1'b0),
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.cin(1'b1),
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.data({1{1'b0}}),
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.sload(1'b0),
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.sset(1'b0),
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.updown(1'b1)
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`ifndef FORMAL_VERIFICATION
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// synopsys translate_on
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`endif
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);
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defparam
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wait_ctr.lpm_direction = "UP",
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wait_ctr.lpm_modulus = 1,
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wait_ctr.lpm_port_updown = "PORT_UNUSED",
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wait_ctr.lpm_width = 1,
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wait_ctr.lpm_type = "lpm_counter";
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assign
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addrct_eq_numwords = wire_addr_cmpr_aeb,
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addrct_lt_numwords = wire_addr_cmpr_alb,
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clken = 1'b1,
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dataout = dataout_w,
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dataout_w = delay_data,
|
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done_state = ((state_reg[2] & (~ state_reg[1])) & (~ state_reg[0])),
|
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idle_state = (((~ state_reg[2]) & (~ state_reg[1])) & (~ state_reg[0])),
|
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init_busy = capture_init,
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ram_address = delay_addr,
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ram_wren = ram_write_state,
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ram_write_state = (((~ state_reg[2]) & state_reg[1]) & state_reg[0]),
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reset_state_machine = (ram_write_state & addrct_lt_numwords),
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rom_addr_state = (((~ state_reg[2]) & (~ state_reg[1])) & state_reg[0]),
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rom_address = wire_addr_ctr_q,
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rom_data_capture_state = (((~ state_reg[2]) & state_reg[1]) & (~ state_reg[0])),
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rom_rden = (((~ prev_state[2]) & (((~ prev_state[1]) & (~ prev_state[0])) | (prev_state[1] & prev_state[0]))) & (((~ state_reg[2]) & (~ state_reg[1])) & state_reg[0])),
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state_machine_clken = (clken & ((idle_state & capture_init) | ((rom_data_capture_state | done_state) | (capture_init & (((~ (rom_addr_state & (~ rom_data_ready))) | (rom_addr_state & rom_data_ready)) | (ram_write_state & addrct_eq_numwords))))));
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endmodule //rom2ram_meminit_qrn
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//VALID FILE
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module rom2ram (
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clock,
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datain,
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init,
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rom_data_ready,
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dataout,
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init_busy,
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ram_address,
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ram_wren,
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rom_address,
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rom_rden);
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input clock;
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input [7:0] datain;
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input init;
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input rom_data_ready;
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output [7:0] dataout;
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output init_busy;
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output [16:0] ram_address;
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output ram_wren;
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output [16:0] rom_address;
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output rom_rden;
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wire [16:0] sub_wire0;
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wire sub_wire1;
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wire [16:0] sub_wire2;
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wire [7:0] sub_wire3;
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wire sub_wire4;
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wire sub_wire5;
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wire [16:0] ram_address = sub_wire0[16:0];
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wire ram_wren = sub_wire1;
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wire [16:0] rom_address = sub_wire2[16:0];
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wire [7:0] dataout = sub_wire3[7:0];
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wire init_busy = sub_wire4;
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wire rom_rden = sub_wire5;
|
|
|
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rom2ram_meminit_qrn rom2ram_meminit_qrn_component (
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.clock (clock),
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.init (init),
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.datain (datain),
|
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.rom_data_ready (rom_data_ready),
|
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.ram_address (sub_wire0),
|
|
.ram_wren (sub_wire1),
|
|
.rom_address (sub_wire2),
|
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.dataout (sub_wire3),
|
|
.init_busy (sub_wire4),
|
|
.rom_rden (sub_wire5));
|
|
|
|
endmodule
|
|
|
|
// ============================================================
|
|
// CNX file retrieval info
|
|
// ============================================================
|
|
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
|
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
|
// Retrieval info: CONSTANT: INIT_FILE STRING "UNUSED"
|
|
// Retrieval info: CONSTANT: INIT_TO_ZERO STRING "NO"
|
|
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
|
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
|
|
// Retrieval info: CONSTANT: LPM_TYPE STRING "altmem_init"
|
|
// Retrieval info: CONSTANT: NUMWORDS NUMERIC "131072"
|
|
// Retrieval info: CONSTANT: PORT_ROM_DATA_READY STRING "PORT_USED"
|
|
// Retrieval info: CONSTANT: ROM_READ_LATENCY NUMERIC "1"
|
|
// Retrieval info: CONSTANT: WIDTH NUMERIC "8"
|
|
// Retrieval info: CONSTANT: WIDTHAD NUMERIC "17"
|
|
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
|
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
|
// Retrieval info: USED_PORT: datain 0 0 8 0 INPUT NODEFVAL "datain[7..0]"
|
|
// Retrieval info: CONNECT: @datain 0 0 8 0 datain 0 0 8 0
|
|
// Retrieval info: USED_PORT: dataout 0 0 8 0 OUTPUT NODEFVAL "dataout[7..0]"
|
|
// Retrieval info: CONNECT: dataout 0 0 8 0 @dataout 0 0 8 0
|
|
// Retrieval info: USED_PORT: init 0 0 0 0 INPUT NODEFVAL "init"
|
|
// Retrieval info: CONNECT: @init 0 0 0 0 init 0 0 0 0
|
|
// Retrieval info: USED_PORT: init_busy 0 0 0 0 OUTPUT NODEFVAL "init_busy"
|
|
// Retrieval info: CONNECT: init_busy 0 0 0 0 @init_busy 0 0 0 0
|
|
// Retrieval info: USED_PORT: ram_address 0 0 17 0 OUTPUT NODEFVAL "ram_address[16..0]"
|
|
// Retrieval info: CONNECT: ram_address 0 0 17 0 @ram_address 0 0 17 0
|
|
// Retrieval info: USED_PORT: ram_wren 0 0 0 0 OUTPUT NODEFVAL "ram_wren"
|
|
// Retrieval info: CONNECT: ram_wren 0 0 0 0 @ram_wren 0 0 0 0
|
|
// Retrieval info: USED_PORT: rom_address 0 0 17 0 OUTPUT NODEFVAL "rom_address[16..0]"
|
|
// Retrieval info: CONNECT: rom_address 0 0 17 0 @rom_address 0 0 17 0
|
|
// Retrieval info: USED_PORT: rom_data_ready 0 0 0 0 INPUT NODEFVAL "rom_data_ready"
|
|
// Retrieval info: CONNECT: @rom_data_ready 0 0 0 0 rom_data_ready 0 0 0 0
|
|
// Retrieval info: USED_PORT: rom_rden 0 0 0 0 OUTPUT NODEFVAL "rom_rden"
|
|
// Retrieval info: CONNECT: rom_rden 0 0 0 0 @rom_rden 0 0 0 0
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL rom2ram.v TRUE FALSE
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL rom2ram.qip TRUE FALSE
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL rom2ram.bsf FALSE TRUE
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL rom2ram_inst.v FALSE TRUE
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL rom2ram_bb.v FALSE TRUE
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL rom2ram.inc FALSE TRUE
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL rom2ram.cmp FALSE TRUE
|
|
// Retrieval info: LIB_FILE: lpm
|