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https://github.com/UzixLS/zx-sizif-xxs.git
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21 lines
1.1 KiB
Tcl
Executable File
21 lines
1.1 KiB
Tcl
Executable File
create_clock -period 28MHz -name {clk28} [get_ports {clk_in}]
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create_generated_clock -name {clkcpu} -divide_by 2 -source [get_ports {clk_in}] [get_registers {cpu:cpu0|clkcpu}]
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create_generated_clock -name {hc0[1]} -divide_by 4 -source [get_ports {clk_in}] [get_registers {video:video0|hc0[1]}]
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derive_pll_clocks
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derive_clocks -period 14MHz
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set_multicycle_path -from {vencode:*|*} -to {vencode:*|*} -setup 4
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set_multicycle_path -from {vencode:*|*} -to {vencode:*|*} -hold 3
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# One video read cycle = ~71ns. SRAM speed = 55ns
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# So we have about 16ns to setup control signals (n_vrd, n_vwr, va - 10ns) and read back data (vd - 6ns)
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set_max_delay -from [get_pins -compatibility_mode video0|*] -to [get_ports n_vrd] 10ns
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set_max_delay -from [get_pins -compatibility_mode video0|*] -to [get_ports n_vwr] 10ns
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set_max_delay -from [get_pins -compatibility_mode video0|*] -to [get_ports va[*]] 10ns
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set_max_delay -from [get_ports vd[*]] -to [get_pins -compatibility_mode video0|*] 6ns
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set_false_path -from * -to [get_ports {snd_l}]
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set_false_path -from * -to [get_ports {snd_r}]
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