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63 lines
1.3 KiB
Systemverilog
Executable File
63 lines
1.3 KiB
Systemverilog
Executable File
module mixer(
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input rst_n,
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input clk28,
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input beeper,
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input tape_out,
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input tape_in,
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input [7:0] ay_a0,
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input [7:0] ay_b0,
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input [7:0] ay_c0,
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input [7:0] ay_a1,
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input [7:0] ay_b1,
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input [7:0] ay_c1,
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input [7:0] sd_l0,
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input [7:0] sd_l1,
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input [7:0] sd_r0,
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input [7:0] sd_r1,
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input ay_acb,
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input mono,
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output dac_l,
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output dac_r
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);
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localparam WIDTH = 13;
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reg [WIDTH:0] dac_l_cnt, dac_r_cnt;
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assign dac_l = dac_l_cnt[WIDTH];
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assign dac_r = dac_r_cnt[WIDTH];
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wire [WIDTH-1:0] dac_next_l =
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{ay_a0, 1'b0} +
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(ay_acb? ay_c0 : ay_b0) +
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{ay_a1, 1'b0} +
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{1'b0, ay_b1} +
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{sd_l0, 1'b0} +
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{sd_l1, 1'b0}
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;
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wire [WIDTH-1:0] dac_next_r =
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(ay_acb? {ay_b0, 1'b0} : {ay_c0, 1'b0}) +
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(ay_acb? ay_c0 : ay_b0) +
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{1'b0, ay_b1} +
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{ay_c1, 1'b0} +
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{sd_r0, 1'b0} +
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{sd_r1, 1'b0}
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;
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wire [WIDTH-1:0] dac_next_lr = {beeper, tape_out, tape_in, 7'd0};
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always @(posedge clk28 or negedge rst_n) begin
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if (!rst_n) begin
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dac_l_cnt <= 0;
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dac_r_cnt <= 0;
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end
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else begin
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dac_l_cnt <= dac_l_cnt[WIDTH-1:0] + dac_next_lr + dac_next_l + (mono? dac_next_r : {WIDTH{1'b0}});
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dac_r_cnt <= dac_r_cnt[WIDTH-1:0] + dac_next_lr + dac_next_r + (mono? dac_next_l : {WIDTH{1'b0}});
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end
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end
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endmodule
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