uzix/zx-sizif-xxs
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replace composite video output implementation

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New one is borrowed from Speccy 2010 project. It's have a much, much
better output quality in price of increased FPGA resources usage.
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UzixLS
2021-11-15 22:57:36 +03:00
parent f30d6faa6d
commit e33bd97a7e
12 changed files with 645 additions and 566 deletions
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23
fpga/syn/clocks.sdc
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@ -1,13 +1,10 @@
create_clock -period 28MHz -name {clk28} [get_ports {clk_in}]
# clkcpu 3.5 or 7 MHz
create_generated_clock -name {clkcpu} -divide_by 4 -source [get_ports {clk_in}] [get_registers {cpucontrol:cpucontrol0|clkcpu}]
# hc0[2] 3.5 MHz
create_generated_clock -name {hc0_2} -divide_by 8 -source [get_ports {clk_in}] [get_registers {screen:screen0|hc0[2]}]
# hsync len 4.7uS, 14e6/(1/4.7e-6) ~= 65
create_generated_clock -name {hsync} -divide_by 126 -source [get_ports {clk_in}] [get_registers {screen:screen0|hsync}]
derive_pll_clocks
derive_clocks -period 14MHz
create_clock -period 28MHz -name {clk28} [get_ports {clk_in}]
create_generated_clock -name {clkcpu} -divide_by 2 -source [get_ports {clk_in}] [get_registers {cpucontrol:cpucontrol0|clkcpu}]
create_generated_clock -name {hc0[1]} -divide_by 4 -source [get_ports {clk_in}] [get_registers {screen:screen0|hc0[1]}]
derive_pll_clocks
derive_clocks -period 14MHz
set_multicycle_path -from {vencode:*|*} -to {vencode:*|*} -setup 4
set_multicycle_path -from {vencode:*|*} -to {vencode:*|*} -hold 3