fix basic 128 crashes when divmmc is enabled

fpga/rtl/divmmc.sv

@@ -21,6 +21,7 @@ module divmmc(
     input rammap,
     input mask_hooks,
     input mask_nmi_hook,
+    input basic48_paged,
 
     output reg [3:0] page,
     output map,
@@ -30,6 +31,19 @@ module divmmc(
     output ext_wait_cycle2
 );
 
+reg rom_m1_access, rom_m1_access0;
+always @(posedge clk28 or negedge rst_n) begin
+    if (!rst_n) begin
+        rom_m1_access <= 0;
+        rom_m1_access0 <= 0;
+    end
+    else if (bus.m1) begin
+        rom_m1_access0 <= bus.a_raw[15:14] == 2'b00;
+    end
+    else begin
+        rom_m1_access <= rom_m1_access0;
+    end
+end
 
 reg automap, automap_next;
 always @(posedge clk28 or negedge rst_n) begin
@@ -45,16 +59,16 @@ always @(posedge clk28 or negedge rst_n) begin
             automap_next <= 0;
         end
         else if (
-                (bus.a == 16'h0000) || // power-on/reset/rst0/software restart
-                (bus.a == 16'h0008) || // syntax error
-                (bus.a == 16'h0038) || // im1 interrupt/rst #38
-                (bus.a == 16'h0066 && !mask_nmi_hook) || // nmi routine
-                (bus.a == 16'h04C6) || // tape save routine
-                (bus.a == 16'h0562)    // tape load and verify routine
+                (bus.a == 16'h0000)                                       || // power-on/reset/rst0/software restart
+                (bus.a == 16'h0008 && (basic48_paged || !rom_m1_access))  || // syntax error
+                (bus.a == 16'h0038 && (basic48_paged || !rom_m1_access))  || // im1 interrupt/rst #38
+                (bus.a == 16'h0066 && !mask_nmi_hook)                     || // nmi routine
+                (bus.a == 16'h04C6 && (basic48_paged || !rom_m1_access))  || // tape save routine
+                (bus.a == 16'h0562 && (basic48_paged || !rom_m1_access))     // tape load and verify routine
                 ) begin
             automap_next <= 1'b1;
         end
-        else if (bus.a[15:8] == 8'h3D) begin // tr-dos mapping area
+        else if (bus.a[15:8] == 8'h3D && (basic48_paged || !rom_m1_access)) begin // tr-dos mapping area
             automap_next <= 1'b1;
             automap <= 1'b1;
         end

fpga/rtl/mem.sv

@@ -10,6 +10,7 @@ module mem(
 
     output bus_valid,
     output cpuwait,
+    output basic48_paged,
 
     input machine_t machine,
     input turbo_t turbo,
@@ -89,6 +90,9 @@ always @* begin
                                                          {2'b11, a[14], a[15], a[14], a[13]} ;
 end
 
+assign basic48_paged = (va_18_13[18:14] == 5'd1) ||
+                       (va_18_13[18:14] == 5'd3) ;
+
 assign vd[7:0] =
     ~n_vrd                 ? {8{1'bz}} :
     bus.wr                 ? {8{1'bz}} :

fpga/rtl/top.sv

@@ -62,6 +62,7 @@ wire [2:0] ram_page128;
 wire init_done;
 wire mem_bus_valid;
 wire mem_wait;
+wire basic48_paged;
 wire sd_indication;
 
 
@@ -394,6 +395,7 @@ divmmc divmmc0(
     .rammap(port_dffd[4] | port_1ffd[0]),
     .mask_hooks(magic_map),
     .mask_nmi_hook(magic_mode),
+    .basic48_paged(basic48_paged),
 
     .page(div_page),
     .map(div_map),
@@ -481,6 +483,7 @@ mem mem0(
 
     .bus_valid(mem_bus_valid),
     .cpuwait(mem_wait),
+    .basic48_paged(basic48_paged),
 
     .machine(machine),
     .turbo(turbo),