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divmmc.sv: remove redundant check

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UzixLS
2021-06-19 11:29:56 +03:00
parent 55c59f66e2
commit df3381a03c
1 changed files with 1 additions and 1 deletions
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fpga/rtl/divmmc.sv
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@ -41,7 +41,7 @@ always @(posedge clk28 or negedge rst_n) begin
div_automap_next <= 0;
end
else if (
(bus.a == 16'h0000 && !magic_mode) || // power-on/reset/rst0/software restart
bus.a_reg == 16'h0000 || // power-on/reset/rst0/software restart
bus.a_reg == 16'h0008 || // syntax error
bus.a_reg == 16'h0038 || // im1 interrupt/rst #38
(bus.a_reg == 16'h0066 && !magic_mode) || // nmi routine