From cf2671b9ad36b8c0d9d38575b8fef126e09493b6 Mon Sep 17 00:00:00 2001
From: Eugene Lozovoy <uzix.ls@gmail.com>
Date: Sun, 30 Oct 2022 20:55:26 +0300
Subject: [PATCH] fix ps/2 sticking keys

---
 fpga/rtl/ps2_rxtx.v | 39 +++++++++++++++++----------------------
 1 file changed, 17 insertions(+), 22 deletions(-)

diff --git a/fpga/rtl/ps2_rxtx.v b/fpga/rtl/ps2_rxtx.v
index 8644cdf..bfc0bde 100644
--- a/fpga/rtl/ps2_rxtx.v
+++ b/fpga/rtl/ps2_rxtx.v
@@ -16,28 +16,21 @@ module ps2_rxtx#(
 
 
 localparam CLKWAIT_US = 1;
+localparam TOUT_US = 150;
 localparam CLKWAIT_TICKS = int'(CLKWAIT_US*CLK_FREQ/1e6) + 1'b1;
-localparam TOUT_US = 150; // must be greater than CLKWAIT_US
 localparam TOUT_TICKS = int'(TOUT_US*CLK_FREQ/1e6) + 1'b1;
-localparam TIMER_WIDTH = $clog2(TOUT_TICKS);
-reg [TIMER_WIDTH-1:0] timer;
+reg [$clog2(TOUT_TICKS)-1:0] timer;
 
 
-reg ps2_freeze; // debounce
 reg ps2_dat;
 reg [1:0] ps2_clk;
-wire ps2_clk_fall = ps2_freeze? 1'b0 : (ps2_clk[0] == 0 && ps2_clk[1] == 1'b1);
+wire ps2_clk_fall = ps2_clk[0] == 0 && ps2_clk[1] == 1'b1;
 always @(posedge clk or negedge rst_n) begin
     if (!rst_n) begin
-        ps2_freeze <= 0;
         ps2_dat <= 1'b1;
         ps2_clk <= 2'b11;
     end
     else begin
-        if (timer == CLKWAIT_TICKS)
-            ps2_freeze <= 1'b0;
-        else if (ps2_clk_fall)
-            ps2_freeze <= 1'b1;
         ps2_dat <= ps2_dat_in;
         ps2_clk <= {ps2_clk[0], ps2_clk_in};
     end
@@ -59,21 +52,23 @@ always @(posedge clk or negedge rst_n) begin
         dataout_valid <= 0;
         dataout_error <= 0;
         if (ps2_clk_fall) begin
-            if (bit_cnt == 4'd10) begin
-                bit_cnt <= 0;
-                if (rxbits[0] == 0 && ~rxbits[9] == ^rxbits[8:1] && ps2_dat == 1'b1)
-                    dataout_valid <= 1'b1;
-                else
-                    dataout_error <= 1'b1;
-            end
-            else begin
-                bit_cnt <= bit_cnt + 1'b1;
-                rxbits <= {ps2_dat, rxbits[9:1]};
-            end
             timer <= 1'b1;
         end
         else if (timer != 0) begin
-            if (timer == TOUT_TICKS) begin
+            if (timer == CLKWAIT_TICKS && !ps2_clk) begin
+                if (bit_cnt == 4'd10) begin
+                    if (rxbits[0] == 0 && ~rxbits[9] == ^rxbits[8:1] && ps2_dat == 1'b1)
+                        dataout_valid <= 1'b1;
+                    else
+                        dataout_error <= 1'b1;
+                    bit_cnt <= 0;
+                end
+                else begin
+                    rxbits <= {ps2_dat, rxbits[9:1]};
+                    bit_cnt <= bit_cnt + 1'b1;
+                end
+            end
+            else if (timer == TOUT_TICKS) begin
                 dataout_error <= bit_cnt != 0;
                 bit_cnt <= 0;
             end