uzix/zx-sizif-xxs
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fix stability

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UzixLS
2021-05-04 20:57:55 +03:00
parent 2ab04059a3
commit 9fd93f0988
6 changed files with 34 additions and 25 deletions
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1
fpga/rtl/common.sv
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@ -15,4 +15,5 @@ interface cpu_bus();
wire wr;
wire ioreq;
wire a_valid;
endinterface

2
fpga/rtl/divmmc.sv
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@ -33,7 +33,7 @@ always @(posedge clk28 or negedge rst_n) begin
div_automap_next <= 0;
div_automap <= 0;
end
else if (bus.m1 && bus.mreq && magic_map == 0) begin
else if (bus.m1 && bus.mreq && magic_map == 0 && bus.a_valid) begin
if (sd_cd || !en || port_dffd_d4 || port_1ffd_d0) begin
div_automap_next <= 0;
end

6
fpga/rtl/magic.sv
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@ -40,11 +40,11 @@ always @(posedge clk28 or negedge rst_n) begin
if (magic_button == 1'b1 && n_int == 1'b1 && n_int_next == 1'b0)
magic_mode <= 1'b1;
if (magic_map && bus.mreq && bus.rd && bus.a == 16'hf000 && !magic_map_next) begin
if (magic_map && bus.mreq && bus.rd && bus.a_valid && bus.a == 16'hf000 && !magic_map_next) begin
magic_unmap_next <= 1'b1;
magic_mode <= 1'b0;
end
else if (magic_map && bus.mreq && bus.rd && bus.a == 16'hf008) begin
else if (magic_map && bus.mreq && bus.rd && bus.a_valid && bus.a == 16'hf008) begin
magic_unmap_next <= 1'b1;
magic_map_next <= 1'b1;
end
@ -52,7 +52,7 @@ always @(posedge clk28 or negedge rst_n) begin
magic_map <= 1'b0;
magic_unmap_next <= 1'b0;
end
else if (magic_mode && bus.m1 && bus.mreq && (bus.a == 16'h0066 || magic_map_next)) begin
else if (magic_mode && bus.m1 && bus.mreq && ((bus.a_valid && bus.a == 16'h0066) || magic_map_next)) begin
magic_map <= 1'b1;
magic_map_next <= 1'b0;
end

22
fpga/rtl/screen.sv
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@ -13,9 +13,9 @@ module screen(
input [2:0] border,
input up_en,
output reg [1:0] r,
output reg [1:0] g,
output reg [1:0] b,
output reg [2:0] r,
output reg [2:0] g,
output reg [2:0] b,
output reg vsync,
output reg hsync,
output reg csync,
@ -186,7 +186,7 @@ wire screen_show = (vc < V_AREA) && (hc0 >= (SCREEN_DELAY<<2) - 2) && (hc0 < ((H
wire screen_update = vc < V_AREA && hc <= H_AREA && hc != 0 && hc0[4:0] == 5'b11110;
wire border_update = !screen_show && ((timings == TIMINGS_PENT && ck7) || hc0[4:0] == 5'b11110);
wire bitmap_shift = hc0[1:0] == 2'b10;
wire screen_read_next = (screen_load || up_en) && ((!bus.iorq && !bus.mreq) || bus.rfsh || clkwait);
wire screen_read_next = (screen_load || up_en) && ((!bus.iorq && !bus.mreq && !bus.m1) || bus.rfsh || clkwait);
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
@ -245,15 +245,17 @@ end
always @(posedge clk28) begin
if (blank)
{g, r, b} = 6'b000000;
{g, r, b} = 0;
else if (up_en) begin
g = pixel? up_ink[7:5] : up_paper[7:5];
r = pixel? up_ink[4:2] : up_paper[4:2];
b = pixel? up_ink[1:0] : up_paper[1:0];
g = pixel? up_ink[7:5] : up_paper[7:5];
r = pixel? up_ink[4:2] : up_paper[4:2];
b[2:1] = pixel? up_ink[1:0] : up_paper[1:0];
b[0] = |b[2:1];
end
else begin
{g[1], r[1], b[1]} = (pixel ^ (attr[7] & blink))? attr[2:0] : attr[5:3];
{g[0], r[0], b[0]} = ((g[1] | r[1] | b[1]) & attr[6])? 3'b111 : 3'b000;
{g[2], r[2], b[2]} = (pixel ^ (attr[7] & blink))? attr[2:0] : attr[5:3];
{g[1], r[1], b[1]} = ((g[2] | r[2] | b[2]) & attr[6])? 3'b111 : 3'b000;
{g[0], r[0], b[0]} = {g[1], r[1], b[1]};
end
csync = ~(vsync0 ^ hsync0);
vsync = ~vsync0;

20
fpga/rtl/top.sv
View File

@ -52,9 +52,11 @@ timings_t timings;
turbo_t turbo;
wire clkwait;
reg n_iorq_delayed;
always @(posedge clk28)
reg n_iorq_delayed, a_valid;
always @(posedge clk28) begin
n_iorq_delayed <= n_iorq;
a_valid <= screen_read == 0;
end
cpu_bus bus();
always @* begin
bus.a = {a[15:13], va[12:0]};
@ -65,7 +67,8 @@ always @* begin
bus.rfsh = ~n_rfsh;
bus.rd = ~n_rd;
bus.wr = ~n_wr;
bus.ioreq = n_m1 == 1'b1 && n_iorq == 1'b0 && n_iorq_delayed == 1'b0;
bus.ioreq = n_m1 == 1'b1 && n_iorq == 1'b0 && n_iorq_delayed == 1'b0 && a_valid;
bus.a_valid = a_valid;
end
@ -100,7 +103,7 @@ assign ps2_data = (ps2_dat_out == 0)? 1'b0 : 1'bz;
/* SCREEN CONTROLLER */
reg [2:0] border;
reg up_en;
reg [1:0] r, g, b;
reg [2:0] r, g, b;
reg hsync;
wire blink;
reg magic_beeper;
@ -146,13 +149,15 @@ screen screen0(
.ck35(ck35)
);
/* VIDEO OUTPUT */
always @*
vdac <= {r, g, b};
vdac <= {g[2], r[2], b[2], g[1], r[1], b[1]};
reg [2:0] chroma0;
chroma_gen #(.CLK_FREQ(40_000_000)) chroma_gen1(
.cg_clock(clk40),
.cg_rgb({g[1],r[1],b[1]}),
.cg_rgb({g[2],r[2],b[2]}),
.cg_hsync(hsync),
.cg_enable(1'b1),
.cg_pnsel(1'b0),
@ -380,7 +385,8 @@ divmmc divmmc0(
.div_ramwr_mask(div_ramwr_mask),
.div_wait(div_wait)
);
assign sd_mosi = (sd_cs == 1'b0)? sd_mosi0 : tape_out;
///assign sd_mosi = (sd_cs == 1'b0)? sd_mosi0 : tape_out;
assign sd_mosi = sd_mosi0;
/* ULAPLUS */