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https://github.com/UzixLS/zx-sizif-xxs.git
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fpga: wip
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UzixLS
@ -33,17 +33,17 @@
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//applicable agreement for further details.
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//altmem_init CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone" INIT_TO_ZERO="NO" NUMWORDS=32768 PORT_ROM_DATA_READY="PORT_USED" ROM_READ_LATENCY=1 WIDTH=8 WIDTHAD=15 clock datain dataout init init_busy ram_address ram_wren rom_address rom_data_ready rom_rden
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//altmem_init CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone" INIT_TO_ZERO="NO" NUMWORDS=131072 PORT_ROM_DATA_READY="PORT_USED" ROM_READ_LATENCY=1 WIDTH=8 WIDTHAD=17 clock datain dataout init init_busy ram_address ram_wren rom_address rom_data_ready rom_rden
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//VERSION_BEGIN 13.0 cbx_altmem_init 2013:06:12:18:03:33:SJ cbx_altsyncram 2013:06:12:18:03:33:SJ cbx_cycloneii 2013:06:12:18:03:33:SJ cbx_lpm_add_sub 2013:06:12:18:03:33:SJ cbx_lpm_compare 2013:06:12:18:03:33:SJ cbx_lpm_counter 2013:06:12:18:03:33:SJ cbx_lpm_decode 2013:06:12:18:03:33:SJ cbx_lpm_mux 2013:06:12:18:03:33:SJ cbx_mgl 2013:06:12:18:33:59:SJ cbx_stratix 2013:06:12:18:03:33:SJ cbx_stratixii 2013:06:12:18:03:33:SJ cbx_stratixiii 2013:06:12:18:03:33:SJ cbx_stratixv 2013:06:12:18:03:33:SJ cbx_util_mgl 2013:06:12:18:03:33:SJ VERSION_END
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// altera message_off 10463
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//synthesis_resources = lpm_compare 2 lpm_counter 2 lut 30
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//synthesis_resources = lpm_compare 2 lpm_counter 2 lut 32
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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//synopsys translate_on
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module rom2ram_meminit_kqn
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module rom2ram_meminit_qrn
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(
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clock,
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datain,
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@ -60,9 +60,9 @@ module rom2ram_meminit_kqn
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output [7:0] dataout;
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input init;
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output init_busy;
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output [14:0] ram_address;
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output [16:0] ram_address;
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output ram_wren;
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output [14:0] rom_address;
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output [16:0] rom_address;
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input rom_data_ready;
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output rom_rden;
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`ifndef ALTERA_RESERVED_QIS
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@ -75,8 +75,8 @@ module rom2ram_meminit_kqn
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`endif
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reg [0:0] capture_init;
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reg [14:0] delay_addr;
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wire [14:0] wire_delay_addr_ena;
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reg [16:0] delay_addr;
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wire [16:0] wire_delay_addr_ena;
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reg [7:0] delay_data;
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wire [7:0] wire_delay_data_ena;
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reg [2:0] prev_state;
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@ -88,7 +88,7 @@ module rom2ram_meminit_kqn
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wire wire_addr_cmpr_alb;
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wire wire_wait_cmpr_aeb;
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wire wire_wait_cmpr_alb;
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wire [14:0] wire_addr_ctr_q;
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wire [16:0] wire_addr_ctr_q;
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wire [0:0] wire_wait_ctr_q;
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wire [0:0] addrct_eq_numwords;
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wire [0:0] addrct_lt_numwords;
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@ -198,8 +198,20 @@ module rom2ram_meminit_kqn
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_addr_ena[14:14] == 1'b1) delay_addr[14:14] <= wire_addr_ctr_q[14:14];
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// synopsys translate_off
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initial
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delay_addr[15:15] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_addr_ena[15:15] == 1'b1) delay_addr[15:15] <= wire_addr_ctr_q[15:15];
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// synopsys translate_off
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initial
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delay_addr[16:16] = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (wire_delay_addr_ena[16:16] == 1'b1) delay_addr[16:16] <= wire_addr_ctr_q[16:16];
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assign
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wire_delay_addr_ena = {15{(clken & rom_data_capture_state)}};
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wire_delay_addr_ena = {17{(clken & rom_data_capture_state)}};
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// synopsys translate_off
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initial
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delay_data[0:0] = 0;
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@ -297,7 +309,7 @@ module rom2ram_meminit_kqn
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.aleb(),
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.aneb(),
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.dataa(delay_addr),
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.datab({15{1'b1}})
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.datab({17{1'b1}})
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`ifndef FORMAL_VERIFICATION
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// synopsys translate_off
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`endif
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@ -310,7 +322,7 @@ module rom2ram_meminit_kqn
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`endif
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);
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defparam
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addr_cmpr.lpm_width = 15,
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addr_cmpr.lpm_width = 17,
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addr_cmpr.lpm_type = "lpm_compare";
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lpm_compare wait_cmpr
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(
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@ -353,7 +365,7 @@ module rom2ram_meminit_kqn
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.aload(1'b0),
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.aset(1'b0),
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.cin(1'b1),
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.data({15{1'b0}}),
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.data({17{1'b0}}),
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.sload(1'b0),
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.sset(1'b0),
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.updown(1'b1)
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@ -363,9 +375,9 @@ module rom2ram_meminit_kqn
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);
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defparam
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addr_ctr.lpm_direction = "UP",
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addr_ctr.lpm_modulus = 32768,
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addr_ctr.lpm_modulus = 131072,
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addr_ctr.lpm_port_updown = "PORT_UNUSED",
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addr_ctr.lpm_width = 15,
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addr_ctr.lpm_width = 17,
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addr_ctr.lpm_type = "lpm_counter";
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lpm_counter wait_ctr
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(
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@ -416,7 +428,7 @@ module rom2ram_meminit_kqn
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rom_data_capture_state = (((~ state_reg[2]) & state_reg[1]) & (~ state_reg[0])),
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rom_rden = (((~ prev_state[2]) & (((~ prev_state[1]) & (~ prev_state[0])) | (prev_state[1] & prev_state[0]))) & (((~ state_reg[2]) & (~ state_reg[1])) & state_reg[0])),
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state_machine_clken = (clken & ((idle_state & capture_init) | ((rom_data_capture_state | done_state) | (capture_init & (((~ (rom_addr_state & (~ rom_data_ready))) | (rom_addr_state & rom_data_ready)) | (ram_write_state & addrct_eq_numwords))))));
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endmodule //rom2ram_meminit_kqn
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endmodule //rom2ram_meminit_qrn
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//VALID FILE
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@ -441,25 +453,25 @@ module rom2ram (
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input rom_data_ready;
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output [7:0] dataout;
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output init_busy;
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output [14:0] ram_address;
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output [16:0] ram_address;
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output ram_wren;
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output [14:0] rom_address;
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output [16:0] rom_address;
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output rom_rden;
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wire [14:0] sub_wire0;
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wire [16:0] sub_wire0;
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wire sub_wire1;
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wire [14:0] sub_wire2;
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wire [16:0] sub_wire2;
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wire [7:0] sub_wire3;
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wire sub_wire4;
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wire sub_wire5;
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wire [14:0] ram_address = sub_wire0[14:0];
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wire [16:0] ram_address = sub_wire0[16:0];
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wire ram_wren = sub_wire1;
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wire [14:0] rom_address = sub_wire2[14:0];
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wire [16:0] rom_address = sub_wire2[16:0];
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wire [7:0] dataout = sub_wire3[7:0];
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wire init_busy = sub_wire4;
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wire rom_rden = sub_wire5;
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rom2ram_meminit_kqn rom2ram_meminit_kqn_component (
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rom2ram_meminit_qrn rom2ram_meminit_qrn_component (
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.clock (clock),
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.init (init),
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.datain (datain),
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@ -483,11 +495,11 @@ endmodule
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
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// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altmem_init"
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// Retrieval info: CONSTANT: NUMWORDS NUMERIC "32768"
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// Retrieval info: CONSTANT: NUMWORDS NUMERIC "131072"
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// Retrieval info: CONSTANT: PORT_ROM_DATA_READY STRING "PORT_USED"
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// Retrieval info: CONSTANT: ROM_READ_LATENCY NUMERIC "1"
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// Retrieval info: CONSTANT: WIDTH NUMERIC "8"
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// Retrieval info: CONSTANT: WIDTHAD NUMERIC "15"
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// Retrieval info: CONSTANT: WIDTHAD NUMERIC "17"
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
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// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
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// Retrieval info: USED_PORT: datain 0 0 8 0 INPUT NODEFVAL "datain[7..0]"
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@ -498,12 +510,12 @@ endmodule
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// Retrieval info: CONNECT: @init 0 0 0 0 init 0 0 0 0
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// Retrieval info: USED_PORT: init_busy 0 0 0 0 OUTPUT NODEFVAL "init_busy"
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// Retrieval info: CONNECT: init_busy 0 0 0 0 @init_busy 0 0 0 0
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// Retrieval info: USED_PORT: ram_address 0 0 15 0 OUTPUT NODEFVAL "ram_address[14..0]"
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// Retrieval info: CONNECT: ram_address 0 0 15 0 @ram_address 0 0 15 0
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// Retrieval info: USED_PORT: ram_address 0 0 17 0 OUTPUT NODEFVAL "ram_address[16..0]"
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// Retrieval info: CONNECT: ram_address 0 0 17 0 @ram_address 0 0 17 0
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// Retrieval info: USED_PORT: ram_wren 0 0 0 0 OUTPUT NODEFVAL "ram_wren"
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// Retrieval info: CONNECT: ram_wren 0 0 0 0 @ram_wren 0 0 0 0
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// Retrieval info: USED_PORT: rom_address 0 0 15 0 OUTPUT NODEFVAL "rom_address[14..0]"
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// Retrieval info: CONNECT: rom_address 0 0 15 0 @rom_address 0 0 15 0
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// Retrieval info: USED_PORT: rom_address 0 0 17 0 OUTPUT NODEFVAL "rom_address[16..0]"
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// Retrieval info: CONNECT: rom_address 0 0 17 0 @rom_address 0 0 17 0
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// Retrieval info: USED_PORT: rom_data_ready 0 0 0 0 INPUT NODEFVAL "rom_data_ready"
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// Retrieval info: CONNECT: @rom_data_ready 0 0 0 0 rom_data_ready 0 0 0 0
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// Retrieval info: USED_PORT: rom_rden 0 0 0 0 OUTPUT NODEFVAL "rom_rden"
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@ -7,7 +7,7 @@
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<width>1</width>
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<mode>7</mode>
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<hex_block>
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<hex_filename>../../rom/testrom.hex</hex_filename>
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<hex_filename>../../rom/sizif.hex</hex_filename>
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<hex_addressing>relative</hex_addressing>
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<hex_offset>0</hex_offset>
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</hex_block>
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@ -54,7 +54,6 @@ set_instance_assignment -name CLOCK_SETTINGS clkcpu -to clkcpu
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set_global_assignment -name AUTO_RESOURCE_SHARING OFF
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set_global_assignment -name AUTO_LCELL_INSERTION OFF
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set_global_assignment -name FMAX_REQUIREMENT "32 MHz" -section_id clk32
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set_instance_assignment -name CLOCK_SETTINGS clk32 -to clk32
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set_global_assignment -name FMAX_REQUIREMENT "8 MHz" -section_id clk8
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set_global_assignment -name FMAX_REQUIREMENT "4 MHz" -section_id clk4
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set_instance_assignment -name CLOCK_SETTINGS clk8 -to "lpm_counter:wgcnt_rtl_1|dffs[1]"
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@ -152,7 +151,10 @@ set_location_assignment PIN_99 -to va[8]
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set_location_assignment PIN_100 -to va[9]
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set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
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set_location_assignment PIN_53 -to n_iorq
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set_location_assignment PIN_10 -to clk28
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set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name USE_SIGNALTAP_FILE output/stp1.stp
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set_global_assignment -name RTLV_GROUP_RELATED_NODES OFF
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set_global_assignment -name VERILOG_INCLUDE_FILE ../rtl/ps2_codes.vh
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set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/mixer.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/soundrive.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/screen.sv
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@ -162,6 +164,8 @@ set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/divmmc.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/cpucontrol.sv
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set_global_assignment -name VERILOG_FILE ../rtl/chroma_gen.v
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set_global_assignment -name VHDL_FILE ../rtl/ym2149.vhd
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set_global_assignment -name VERILOG_FILE ../rtl/ps2.v
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set_global_assignment -name VERILOG_FILE ../rtl/ps2_rxtx.v
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set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/common.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/top.sv
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set_global_assignment -name SDC_FILE clocks.sdc
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@ -169,9 +173,8 @@ set_global_assignment -name CDF_FILE output/zx_ula.cdf
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set_global_assignment -name QIP_FILE ip/pll.qip
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set_global_assignment -name QIP_FILE ip/rom2ram.qip
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set_global_assignment -name QIP_FILE ip/asmi.qip
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set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
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set_global_assignment -name SIGNALTAP_FILE stp1.stp
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set_global_assignment -name SLD_FILE "stp1_auto_stripped.stp"
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set_global_assignment -name RTLV_GROUP_RELATED_NODES OFF
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set_global_assignment -name SLD_FILE "/home/uzix/zx-sizif-xxs/fpga/syn/output/stp1_auto_stripped.stp"
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_miso_tape_in
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_iorq
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set_location_assignment PIN_10 -to clk_in
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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