mirror of
https://github.com/UzixLS/zx-sizif-xxs.git
synced 2025-07-19 07:11:28 +03:00
improve compatibility with slower sram chips
This commit is contained in:
Eugene Lozovoy
2
Makefile
2
Makefile
@ -1,5 +1,5 @@
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OUTDIR=out_new
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REV=B
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REV=zero_A
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.PHONY: all build_rev clean pipeline pipeline_sof
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@ -6,14 +6,14 @@ endpackage
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interface cpu_bus();
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wire [15:0] a;
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wire [7:0] d;
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wire iorq;
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wire mreq;
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wire m1;
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wire rfsh;
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wire rd;
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wire wr;
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reg [15:0] a;
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reg [7:0] d;
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reg iorq;
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reg mreq;
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reg m1;
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reg rfsh;
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reg rd;
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reg wr;
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reg [15:0] a_reg;
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reg [7:0] d_reg;
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@ -16,7 +16,6 @@ module cpucontrol(
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input [2:0] rampage128,
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input machine_t machine,
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input turbo_t turbo,
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input ext_wait_cycle,
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input init_done_in,
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output reg n_rstcpu,
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@ -46,19 +45,22 @@ assign snow = bus.a[14] && ~bus.a[15] && bus.rfsh && (machine == MACHINE_S48 ||
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/* CLOCK */
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reg [2:0] turbo_wait;
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wire turbo_wait_trig0 = bus.rd || bus.wr;
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reg turbo_wait_trig1;
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reg [3:0] turbo_wait;
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wire turbo_wait_trig0 = turbo == TURBO_14 && bus.mreq && !bus.rfsh;
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wire turbo_wait_trig1 = turbo == TURBO_14 && (bus.rd || bus.wr);
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reg turbo_wait_trig0_prev, turbo_wait_trig1_prev;
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always @(posedge clk28) begin
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turbo_wait[0] <= turbo == TURBO_14 && turbo_wait_trig0 && !turbo_wait_trig1;
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turbo_wait[1] <= turbo_wait[0] && (bus.iorq || ext_wait_cycle);
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turbo_wait[0] <= turbo_wait_trig0 && !turbo_wait_trig0_prev;
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turbo_wait[1] <= turbo_wait[0] || (turbo_wait_trig1 && !turbo_wait_trig1_prev);
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turbo_wait[2] <= turbo_wait[1];
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turbo_wait_trig1 <= turbo_wait_trig0;
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turbo_wait[3] <= turbo_wait[2];
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turbo_wait_trig0_prev <= turbo_wait_trig0;
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turbo_wait_trig1_prev <= turbo_wait_trig1;
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end
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reg clkcpu_prev;
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assign clkcpu_ck = clkcpu && !clkcpu_prev;
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assign clkwait = contention || (|turbo_wait);
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assign clkwait = contention || (|turbo_wait[3:1]);
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always @(posedge clk28) begin
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clkcpu_prev <= clkcpu;
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if (clkwait)
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@ -5,6 +5,7 @@ module screen(
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input clk28,
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input machine_t machine,
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input turbo_t turbo,
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input [2:0] border,
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output reg [5:0] r,
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@ -17,7 +18,7 @@ module screen(
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input fetch_allow,
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output reg fetch,
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output fetch_next,
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output reg [14:0] addr,
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output [14:0] addr,
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input [7:0] fetch_data,
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output contention,
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@ -199,12 +200,16 @@ always @(posedge clk28 or negedge rst_n) begin
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end
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end
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reg loading;
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reg loading, loading_up;
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always @(posedge clk28 or negedge rst_n) begin
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if (!rst_n)
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if (!rst_n) begin
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loading <= 0;
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else
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loading_up <= 0;
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end
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else begin
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loading <= (vc < V_AREA) && (hc0 > 15) && (hc0 < (H_AREA<<2) + 17);
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loading_up <= loading && (screen_update || loading_up);
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end
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end
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@ -213,19 +218,25 @@ wire [7:0] attr_border = {2'b00, border[2:0], border[2:0]};
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reg [7:0] bitmap, attr, bitmap_next, attr_next;
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reg [7:0] up_ink0, up_paper0;
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reg fetch_step;
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wire fetch_bitmap = fetch && fetch_step == 1'd0;
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wire fetch_attr = fetch && fetch_step == 1'd1;
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assign fetch_next = loading && fetch_allow;
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reg [1:0] fetch_cnt;
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localparam FETCH_CYCLES = 2'd2;
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assign fetch_next = loading && (fetch_allow || (|fetch_cnt && fetch_cnt != FETCH_CYCLES && turbo == TURBO_14));
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assign up_ink_addr = { attr_next[7:6], 1'b0, attr_next[2:0] };
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assign up_paper_addr = { attr_next[7:6], 1'b1, attr_next[5:3] };
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reg fetch_step;
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wire fetch_bitmap = fetch && fetch_step == 1'd0 && fetch_cnt == FETCH_CYCLES;
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wire fetch_attr = fetch && fetch_step == 1'd1 && fetch_cnt == FETCH_CYCLES;
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assign addr = (fetch_step == 1'd0)?
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{ 2'b10, vaddr[7:6], vaddr[2:0], vaddr[5:3], haddr[7:3] } :
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{ 5'b10110, vaddr[7:3], haddr[7:3] };
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assign up_ink_addr = loading_up? { attr_next[7:6], 1'b0, attr_next[2:0] } : { 3'b0, attr_border[2:0] };
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assign up_paper_addr = loading_up? { attr_next[7:6], 1'b1, attr_next[5:3] } : { 3'b0, attr_border[2:0] };
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always @(posedge clk28 or negedge rst_n) begin
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if (!rst_n) begin
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addr <= 0;
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fetch <= 0;
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fetch_step <= 0;
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fetch_cnt <= 0;
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attr <= 0;
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bitmap <= 0;
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attr_next <= 0;
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@ -234,23 +245,20 @@ always @(posedge clk28 or negedge rst_n) begin
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up_paper0 <= 0;
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end
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else begin
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if (ck14) begin
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addr <= ((fetch && fetch_step == 1'd1) || (!fetch && fetch_step == 1'b0))?
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{ 2'b10, vaddr[7:6], vaddr[2:0], vaddr[5:3], haddr[7:3] } :
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{ 5'b10110, vaddr[7:3], haddr[7:3] };
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if (fetch)
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fetch_step <= fetch_step + 1'b1;
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fetch <= fetch_next;
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if (fetch_attr)
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fetch <= fetch_next;
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if (fetch_cnt == FETCH_CYCLES) begin
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if (fetch_step == 1'd1)
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attr_next <= fetch_data;
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else if (!loading)
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attr_next <= attr_border;
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if (fetch_bitmap)
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if (fetch_step == 1'd0)
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bitmap_next <= fetch_data;
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else if (!loading)
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bitmap_next <= 0;
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fetch_step <= fetch_step + 1'b1;
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fetch_cnt <= 0;
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end
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else if (fetch && fetch_next && !next_addr) begin
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fetch_cnt <= fetch_cnt + 1'b1;
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end
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else begin
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fetch_cnt <= 0;
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end
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if (screen_show && screen_update)
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@ -60,7 +60,6 @@ wire magic_reboot, magic_beeper;
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wire up_active;
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wire clkwait;
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wire [2:0] rampage128;
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wire div_wait;
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wire init_done;
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wire screen_fetch, screen_fetch_next;
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@ -74,8 +73,8 @@ always @(posedge clk28 or negedge rst_n) begin
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bus_memreq <= 0;
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end
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else if (!screen_fetch && !screen_fetch_next) begin
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bus.a_reg <= bus.a;
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bus.d_reg <= bus.d;
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bus.a_reg <= {a[15:13], va[12:0]};
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bus.d_reg <= vd;
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bus_ioreq <= n_iorq == 1'b0 && n_m1 == 1'b1;
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bus_memreq <= n_mreq == 1'b0 && n_rfsh == 1'b1;
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end
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@ -86,16 +85,18 @@ always @(posedge clk28 or negedge rst_n) begin
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bus_memreq <= 0;
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end
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end
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assign bus.a = {a[15:13], va[12:0]};
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assign bus.d = vd;
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assign bus.iorq = ~n_iorq;
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assign bus.mreq = ~n_mreq;
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assign bus.m1 = ~n_m1;
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assign bus.rfsh = ~n_rfsh;
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assign bus.rd = ~n_rd;
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assign bus.wr = ~n_wr;
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assign bus.ioreq = bus_ioreq & ~n_iorq;
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assign bus.memreq = bus_memreq & ~n_mreq;
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always @(posedge clk168) begin
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bus.a <= {a[15:13], va[12:0]};
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bus.d <= vd;
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bus.iorq <= ~n_iorq;
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bus.mreq <= ~n_mreq;
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bus.m1 <= ~n_m1;
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bus.rfsh <= ~n_rfsh;
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bus.rd <= ~n_rd;
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bus.wr <= ~n_wr;
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end
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assign bus.ioreq = bus_ioreq & bus.iorq;
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assign bus.memreq = bus_memreq & bus.mreq;
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/* RESET */
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@ -122,6 +123,7 @@ screen screen0(
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.clk28(clk28),
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.machine(machine),
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.turbo(turbo),
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.border(screen_border),
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.r(r),
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@ -131,7 +133,7 @@ screen screen0(
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.vsync(vsync),
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.hsync(hsync),
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.fetch_allow((!bus.iorq && !bus.mreq) || bus.rfsh || clkwait),
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.fetch_allow((!bus.iorq && !bus.mreq) || bus.rfsh || (clkwait && turbo == TURBO_NONE)),
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.fetch(screen_fetch),
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.addr(screen_addr),
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.fetch_next(screen_fetch_next),
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@ -212,9 +214,8 @@ cpucontrol cpucontrol0(
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.hc(hc),
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.rampage128(rampage128),
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.machine(machine),
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.screen_contention(screen_contention),
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.turbo(turbo),
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.ext_wait_cycle(div_wait),
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.screen_contention(screen_contention),
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.init_done_in(init_done),
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.n_rstcpu(n_rstcpu),
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@ -411,8 +412,7 @@ divmmc divmmc0(
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.map(div_map),
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.automap(div_automap),
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.ram(div_ram),
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.ramwr_mask(div_ramwr_mask),
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.cpuwait(div_wait)
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.ramwr_mask(div_ramwr_mask)
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);
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assign sd_mosi_tape_out = (!divmmc_en && !zc_en)? tape_out : sd_mosi0;
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@ -8,10 +8,13 @@ derive_clocks -period 14MHz
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set_multicycle_path -from {vencode:*|*} -to {vencode:*|*} -setup 4
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set_multicycle_path -from {vencode:*|*} -to {vencode:*|*} -hold 3
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# One screen read cycle = ~71ns. SRAM speed = 55ns
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# So we have about 16ns to setup control signals (n_vrd, n_vwr, va - 10ns) and read back data (vd - 6ns)
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set_max_delay -from [get_pins -compatibility_mode screen0|*] -to [get_ports n_vrd] 10ns
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set_max_delay -from [get_pins -compatibility_mode screen0|*] -to [get_ports n_vwr] 10ns
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set_max_delay -from [get_pins -compatibility_mode screen0|*] -to [get_ports va[*]] 10ns
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set_max_delay -from [get_ports vd[*]] -to [get_pins -compatibility_mode screen0|*] 6ns
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# One screen read cycle = ~71ns. SRAM speed = 55ns
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# So we have about 16ns to setup control signals (n_vrd, n_vwr, va - 10ns) and read back data (vd - 6ns)
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set_max_delay -from [get_pins -compatibility_mode screen0|*] -to [get_ports n_vrd] 10ns
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set_max_delay -from [get_pins -compatibility_mode screen0|*] -to [get_ports n_vwr] 10ns
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set_max_delay -from [get_pins -compatibility_mode screen0|*] -to [get_ports va[*]] 10ns
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set_max_delay -from [get_ports vd[*]] -to [get_pins -compatibility_mode screen0|*] 6ns
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set_false_path -from * -to [get_ports {snd_l}]
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set_false_path -from * -to [get_ports {snd_r}]
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@ -58,7 +58,7 @@ set_global_assignment -name FMAX_REQUIREMENT "4 MHz" -section_id clk4
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set_instance_assignment -name CLOCK_SETTINGS clk8 -to "lpm_counter:wgcnt_rtl_1|dffs[1]"
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set_instance_assignment -name CLOCK_SETTINGS clk4 -to "lpm_counter:wgcnt_rtl_1|dffs[2]"
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set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
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set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
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set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output/
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set_global_assignment -name FMAX_REQUIREMENT "7.156 MHz" -section_id clk7
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@ -67,7 +67,7 @@ set_global_assignment -name DUTY_CYCLE 40 -section_id clk7
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set_global_assignment -name SAVE_DISK_SPACE OFF
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set_global_assignment -name SMART_RECOMPILE ON
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set_global_assignment -name POWER_USE_PVA OFF
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set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
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set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
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set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
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@ -165,7 +165,6 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[5]
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[6]
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[7]
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set_global_assignment -name VERILOG_MACRO "REV_A=<None>"
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
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set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/ym2149.sv
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set_global_assignment -name VERILOG_FILE ../rtl/vencode_sin_cos.v
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set_global_assignment -name VHDL_FILE ../rtl/vencode.vhd
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@ -188,4 +187,14 @@ set_global_assignment -name SDC_FILE clocks.sdc
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set_global_assignment -name CDF_FILE output/zx_ula.cdf
|
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set_global_assignment -name QIP_FILE ip/pll.qip
|
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set_global_assignment -name QIP_FILE ip/rom2ram.qip
|
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set_global_assignment -name QIP_FILE ip/asmi.qip
|
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set_global_assignment -name QIP_FILE ip/asmi.qip
|
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
|
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
|
||||
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@ -58,7 +58,7 @@ set_global_assignment -name FMAX_REQUIREMENT "4 MHz" -section_id clk4
|
||||
set_instance_assignment -name CLOCK_SETTINGS clk8 -to "lpm_counter:wgcnt_rtl_1|dffs[1]"
|
||||
set_instance_assignment -name CLOCK_SETTINGS clk4 -to "lpm_counter:wgcnt_rtl_1|dffs[2]"
|
||||
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output/
|
||||
set_global_assignment -name FMAX_REQUIREMENT "7.156 MHz" -section_id clk7
|
||||
@ -67,7 +67,7 @@ set_global_assignment -name DUTY_CYCLE 40 -section_id clk7
|
||||
set_global_assignment -name SAVE_DISK_SPACE OFF
|
||||
set_global_assignment -name SMART_RECOMPILE ON
|
||||
set_global_assignment -name POWER_USE_PVA OFF
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
|
||||
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
|
||||
@ -187,5 +187,14 @@ set_global_assignment -name CDF_FILE output/zx_ula.cdf
|
||||
set_global_assignment -name QIP_FILE ip/pll.qip
|
||||
set_global_assignment -name QIP_FILE ip/rom2ram.qip
|
||||
set_global_assignment -name QIP_FILE ip/asmi.qip
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
set_global_assignment -name VERILOG_MACRO "REV_B=<None>"
|
||||
set_global_assignment -name VERILOG_MACRO "REV_B=<None>"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
|
||||
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@ -58,7 +58,7 @@ set_global_assignment -name FMAX_REQUIREMENT "4 MHz" -section_id clk4
|
||||
set_instance_assignment -name CLOCK_SETTINGS clk8 -to "lpm_counter:wgcnt_rtl_1|dffs[1]"
|
||||
set_instance_assignment -name CLOCK_SETTINGS clk4 -to "lpm_counter:wgcnt_rtl_1|dffs[2]"
|
||||
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output/
|
||||
set_global_assignment -name FMAX_REQUIREMENT "7.156 MHz" -section_id clk7
|
||||
@ -67,7 +67,7 @@ set_global_assignment -name DUTY_CYCLE 40 -section_id clk7
|
||||
set_global_assignment -name SAVE_DISK_SPACE OFF
|
||||
set_global_assignment -name SMART_RECOMPILE ON
|
||||
set_global_assignment -name POWER_USE_PVA OFF
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
|
||||
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
|
||||
@ -189,10 +189,13 @@ set_global_assignment -name QIP_FILE ip/rom2ram.qip
|
||||
set_global_assignment -name QIP_FILE ip/asmi.qip
|
||||
set_global_assignment -name VERILOG_MACRO "REV_ZERO_A=<None>"
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to clkcpu
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
|
||||
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
Reference in New Issue
Block a user