uzix/zx-sizif-xxs
1
0
Fork 0
mirror of https://github.com/UzixLS/zx-sizif-xxs.git synced 2025-07-19 07:11:28 +03:00
Code Issues Projects Releases Wiki Activity

[minor] refactor fpga project

Browse Source
This commit is contained in:
UzixLS
2021-11-18 20:38:14 +03:00
parent e33bd97a7e
commit 93bf6fc638
3 changed files with 227 additions and 224 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
fpga/syn/Makefile
View File

@ -1,4 +1,4 @@
REVISION = zx_ula
REVISION = rev_A
.PHONY: build sof2jic program_sof program_jic clean report
@ -6,7 +6,10 @@ build:
quartus_sh --no_banner --flow compile zx_ula -c ${REVISION}
sof2jic:
cp -f "output/${REVISION}.sof" output/zx_ula.sof
quartus_cpf -c sof2jic.cof
mv output/zx_ula.jic "output/${REVISION}.jic"
rm output/zx_ula.sof
program_sof:
quartus_pgm --no_banner --mode=jtag -o "P;output/${REVISION}.sof"

35
fpga/syn/zx_ula.qsf → fpga/syn/rev_A.qsf Executable file → Normal file
View File

@ -25,7 +25,7 @@
# Notes:
#
# 1) The default values for assignments are stored in the file:
# zx_ula_assignment_defaults.qdf
# rev_A_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
@ -39,8 +39,8 @@
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C3T100C8
set_global_assignment -name TOP_LEVEL_ENTITY zx_ula
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:15:12 APRIL 28, 2019"
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:56:16 NOVEMBER 08, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL"
@ -51,7 +51,6 @@ set_global_assignment -name FMAX_REQUIREMENT "14.4 MHz"
set_global_assignment -name FMAX_REQUIREMENT "14.4 MHz" -section_id clk14
set_global_assignment -name FMAX_REQUIREMENT "7.156 MHz" -section_id clkcpu
set_instance_assignment -name CLOCK_SETTINGS clkcpu -to clkcpu
set_global_assignment -name AUTO_RESOURCE_SHARING OFF
set_global_assignment -name AUTO_LCELL_INSERTION OFF
set_global_assignment -name FMAX_REQUIREMENT "32 MHz" -section_id clk32
set_global_assignment -name FMAX_REQUIREMENT "8 MHz" -section_id clk8
@ -69,7 +68,6 @@ set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name POWER_USE_PVA OFF
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
set_global_assignment -name SLOW_SLEW_RATE OFF
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
@ -158,6 +156,19 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_miso_tape_in
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_iorq
set_location_assignment PIN_10 -to clk_in
set_global_assignment -name SLD_FILE "/home/uzix/zx-sizif-xxs/fpga/rtl/stp2_auto_stripped.stp"
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[0]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[1]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[2]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[4]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[3]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[5]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[6]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[7]
set_global_assignment -name VERILOG_MACRO "REV_A=<None>"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/ym2149.sv
set_global_assignment -name VERILOG_FILE ../rtl/vencode_sin_cos.v
set_global_assignment -name VHDL_FILE ../rtl/vencode.vhd
set_global_assignment -name VERILOG_INCLUDE_FILE ../rtl/ps2_codes.vh
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/mixer.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/soundrive.sv
@ -168,9 +179,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/divmmc.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/cpucontrol.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/memcontrol.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/turbosound.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/ym2149.sv
set_global_assignment -name VERILOG_FILE ../rtl/vencode_sin_cos.v
set_global_assignment -name VHDL_FILE ../rtl/vencode.vhd
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/ulaplus.sv
set_global_assignment -name VERILOG_FILE ../rtl/ps2.v
set_global_assignment -name VERILOG_FILE ../rtl/ps2_rxtx.v
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/common.sv
@ -180,13 +189,3 @@ set_global_assignment -name CDF_FILE output/zx_ula.cdf
set_global_assignment -name QIP_FILE ip/pll.qip
set_global_assignment -name QIP_FILE ip/rom2ram.qip
set_global_assignment -name QIP_FILE ip/asmi.qip
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/ulaplus.sv
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[0]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[1]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[2]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[4]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[3]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[5]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[6]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[7]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

15
fpga/syn/zx_ula.qpf
View File

@ -1,6 +1,6 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
@ -16,15 +16,16 @@
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 08:15:12 April 28, 2019
# Quartus II 32-bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
# Date created = 20:26:38 November 08, 2021
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "9.0"
DATE = "08:15:12 April 28, 2019"
QUARTUS_VERSION = "13.0"
DATE = "20:26:38 November 08, 2021"
# Revisions
PROJECT_REVISION = "zx_ula"
PROJECT_REVISION = "rev_A"
PROJECT_REVISION = "rev_B"