From 93bf6fc638b72c53663ac5079392c35b6981b41b Mon Sep 17 00:00:00 2001 From: UzixLS Date: Thu, 18 Nov 2021 20:38:14 +0300 Subject: [PATCH] [minor] refactor fpga project --- fpga/syn/Makefile | 7 +- fpga/syn/{zx_ula.qsf => rev_A.qsf} | 383 ++++++++++++++--------------- fpga/syn/zx_ula.qpf | 61 ++--- 3 files changed, 227 insertions(+), 224 deletions(-) rename fpga/syn/{zx_ula.qsf => rev_A.qsf} (89%) mode change 100755 => 100644 diff --git a/fpga/syn/Makefile b/fpga/syn/Makefile index 58f2d95..bc755c8 100644 --- a/fpga/syn/Makefile +++ b/fpga/syn/Makefile @@ -1,4 +1,4 @@ -REVISION = zx_ula +REVISION = rev_A .PHONY: build sof2jic program_sof program_jic clean report @@ -6,7 +6,10 @@ build: quartus_sh --no_banner --flow compile zx_ula -c ${REVISION} sof2jic: - quartus_cpf -c sof2jic.cof + cp -f "output/${REVISION}.sof" output/zx_ula.sof + quartus_cpf -c sof2jic.cof + mv output/zx_ula.jic "output/${REVISION}.jic" + rm output/zx_ula.sof program_sof: quartus_pgm --no_banner --mode=jtag -o "P;output/${REVISION}.sof" diff --git a/fpga/syn/zx_ula.qsf b/fpga/syn/rev_A.qsf old mode 100755 new mode 100644 similarity index 89% rename from fpga/syn/zx_ula.qsf rename to fpga/syn/rev_A.qsf index 343ce59..123c9dc --- a/fpga/syn/zx_ula.qsf +++ b/fpga/syn/rev_A.qsf @@ -1,192 +1,191 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2009 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II -# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition -# Date created = 08:15:12 April 28, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# zx_ula_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - -set_global_assignment -name FAMILY Cyclone -set_global_assignment -name DEVICE EP1C3T100C8 -set_global_assignment -name TOP_LEVEL_ENTITY zx_ula -set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2" -set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:15:12 APRIL 28, 2019" -set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga -set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 -set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA -set_global_assignment -name FMAX_REQUIREMENT "14.4 MHz" -set_global_assignment -name FMAX_REQUIREMENT "14.4 MHz" -section_id clk14 -set_global_assignment -name FMAX_REQUIREMENT "7.156 MHz" -section_id clkcpu -set_instance_assignment -name CLOCK_SETTINGS clkcpu -to clkcpu -set_global_assignment -name AUTO_RESOURCE_SHARING OFF -set_global_assignment -name AUTO_LCELL_INSERTION OFF -set_global_assignment -name FMAX_REQUIREMENT "32 MHz" -section_id clk32 -set_global_assignment -name FMAX_REQUIREMENT "8 MHz" -section_id clk8 -set_global_assignment -name FMAX_REQUIREMENT "4 MHz" -section_id clk4 -set_instance_assignment -name CLOCK_SETTINGS clk8 -to "lpm_counter:wgcnt_rtl_1|dffs[1]" -set_instance_assignment -name CLOCK_SETTINGS clk4 -to "lpm_counter:wgcnt_rtl_1|dffs[2]" - -set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output/ -set_global_assignment -name FMAX_REQUIREMENT "7.156 MHz" -section_id clk7 -set_global_assignment -name DUTY_CYCLE 40 -section_id clk7 - -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name POWER_USE_PVA OFF -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF -set_global_assignment -name SLOW_SLEW_RATE OFF -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF - -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100 -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_rd -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_wr -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_cd -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_m1 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_mreq -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_rfsh -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_rstcpu -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_nmi -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name USE_CONFIGURATION_DEVICE ON -set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPCS4 -set_location_assignment PIN_1 -to va[10] -set_location_assignment PIN_2 -to va[5] -set_location_assignment PIN_3 -to vd[4] -set_location_assignment PIN_4 -to va[12] -set_location_assignment PIN_5 -to va[11] -set_location_assignment PIN_20 -to ps2_dat -set_location_assignment PIN_21 -to ps2_clk -set_location_assignment PIN_22 -to reserv[0] -set_location_assignment PIN_23 -to reserv[1] -set_location_assignment PIN_24 -to composite[0] -set_location_assignment PIN_25 -to composite[7] -set_location_assignment PIN_26 -to composite[6] -set_location_assignment PIN_27 -to composite[5] -set_location_assignment PIN_28 -to composite[4] -set_location_assignment PIN_29 -to composite[3] -set_location_assignment PIN_34 -to composite[2] -set_location_assignment PIN_35 -to composite[1] -set_location_assignment PIN_36 -to snd_l -set_location_assignment PIN_37 -to snd_r -set_location_assignment PIN_38 -to sd_cd -set_location_assignment PIN_39 -to sd_cs -set_location_assignment PIN_40 -to sd_miso_tape_in -set_location_assignment PIN_41 -to sd_sck -set_location_assignment PIN_42 -to sd_mosi_tape_out -set_location_assignment PIN_47 -to vd[2] -set_location_assignment PIN_48 -to vd[0] -set_location_assignment PIN_49 -to vd[7] -set_location_assignment PIN_50 -to vd[1] -set_location_assignment PIN_51 -to vd[6] -set_location_assignment PIN_52 -to n_mreq -set_location_assignment PIN_54 -to n_int -set_location_assignment PIN_55 -to n_nmi -set_location_assignment PIN_56 -to va[14] -set_location_assignment PIN_57 -to n_vrd -set_location_assignment PIN_65 -to va[16] -set_location_assignment PIN_68 -to va[18] -set_location_assignment PIN_69 -to va[15] -set_location_assignment PIN_70 -to va[13] -set_location_assignment PIN_71 -to n_vwr -set_location_assignment PIN_72 -to va[17] -set_location_assignment PIN_73 -to clkcpu -set_location_assignment PIN_74 -to n_wr -set_location_assignment PIN_75 -to n_rd -set_location_assignment PIN_76 -to a[14] -set_location_assignment PIN_77 -to a[15] -set_location_assignment PIN_78 -to a[13] -set_location_assignment PIN_79 -to vd[5] -set_location_assignment PIN_84 -to n_rstcpu -set_location_assignment PIN_85 -to n_m1 -set_location_assignment PIN_86 -to n_rfsh -set_location_assignment PIN_87 -to vd[3] -set_location_assignment PIN_88 -to va[0] -set_location_assignment PIN_89 -to va[1] -set_location_assignment PIN_90 -to va[2] -set_location_assignment PIN_91 -to va[3] -set_location_assignment PIN_92 -to va[4] -set_location_assignment PIN_97 -to va[6] -set_location_assignment PIN_98 -to va[7] -set_location_assignment PIN_99 -to va[8] -set_location_assignment PIN_100 -to va[9] -set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP" -set_location_assignment PIN_53 -to n_iorq -set_global_assignment -name ENABLE_SIGNALTAP OFF -set_global_assignment -name USE_SIGNALTAP_FILE output/stp1.stp -set_global_assignment -name RTLV_GROUP_RELATED_NODES OFF -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_miso_tape_in -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_iorq -set_location_assignment PIN_10 -to clk_in -set_global_assignment -name SLD_FILE "/home/uzix/zx-sizif-xxs/fpga/rtl/stp2_auto_stripped.stp" -set_global_assignment -name VERILOG_INCLUDE_FILE ../rtl/ps2_codes.vh -set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/mixer.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/soundrive.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/screen.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/ports.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/magic.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/divmmc.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/cpucontrol.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/memcontrol.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/turbosound.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/ym2149.sv -set_global_assignment -name VERILOG_FILE ../rtl/vencode_sin_cos.v -set_global_assignment -name VHDL_FILE ../rtl/vencode.vhd -set_global_assignment -name VERILOG_FILE ../rtl/ps2.v -set_global_assignment -name VERILOG_FILE ../rtl/ps2_rxtx.v -set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/common.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/top.sv -set_global_assignment -name SDC_FILE clocks.sdc -set_global_assignment -name CDF_FILE output/zx_ula.cdf -set_global_assignment -name QIP_FILE ip/pll.qip -set_global_assignment -name QIP_FILE ip/rom2ram.qip -set_global_assignment -name QIP_FILE ip/asmi.qip -set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/ulaplus.sv -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[0] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[1] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[2] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[4] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[3] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[5] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[7] -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +# Date created = 08:15:12 April 28, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# rev_A_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY Cyclone +set_global_assignment -name DEVICE EP1C3T100C8 +set_global_assignment -name TOP_LEVEL_ENTITY zx_ula +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:56:16 NOVEMBER 08, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 +set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA +set_global_assignment -name FMAX_REQUIREMENT "14.4 MHz" +set_global_assignment -name FMAX_REQUIREMENT "14.4 MHz" -section_id clk14 +set_global_assignment -name FMAX_REQUIREMENT "7.156 MHz" -section_id clkcpu +set_instance_assignment -name CLOCK_SETTINGS clkcpu -to clkcpu +set_global_assignment -name AUTO_LCELL_INSERTION OFF +set_global_assignment -name FMAX_REQUIREMENT "32 MHz" -section_id clk32 +set_global_assignment -name FMAX_REQUIREMENT "8 MHz" -section_id clk8 +set_global_assignment -name FMAX_REQUIREMENT "4 MHz" -section_id clk4 +set_instance_assignment -name CLOCK_SETTINGS clk8 -to "lpm_counter:wgcnt_rtl_1|dffs[1]" +set_instance_assignment -name CLOCK_SETTINGS clk4 -to "lpm_counter:wgcnt_rtl_1|dffs[2]" + +set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output/ +set_global_assignment -name FMAX_REQUIREMENT "7.156 MHz" -section_id clk7 +set_global_assignment -name DUTY_CYCLE 40 -section_id clk7 + +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name POWER_USE_PVA OFF +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF + +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100 +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_rd +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_wr +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_cd +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_m1 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_mreq +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_rfsh +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_rstcpu +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_nmi +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPCS4 +set_location_assignment PIN_1 -to va[10] +set_location_assignment PIN_2 -to va[5] +set_location_assignment PIN_3 -to vd[4] +set_location_assignment PIN_4 -to va[12] +set_location_assignment PIN_5 -to va[11] +set_location_assignment PIN_20 -to ps2_dat +set_location_assignment PIN_21 -to ps2_clk +set_location_assignment PIN_22 -to reserv[0] +set_location_assignment PIN_23 -to reserv[1] +set_location_assignment PIN_24 -to composite[0] +set_location_assignment PIN_25 -to composite[7] +set_location_assignment PIN_26 -to composite[6] +set_location_assignment PIN_27 -to composite[5] +set_location_assignment PIN_28 -to composite[4] +set_location_assignment PIN_29 -to composite[3] +set_location_assignment PIN_34 -to composite[2] +set_location_assignment PIN_35 -to composite[1] +set_location_assignment PIN_36 -to snd_l +set_location_assignment PIN_37 -to snd_r +set_location_assignment PIN_38 -to sd_cd +set_location_assignment PIN_39 -to sd_cs +set_location_assignment PIN_40 -to sd_miso_tape_in +set_location_assignment PIN_41 -to sd_sck +set_location_assignment PIN_42 -to sd_mosi_tape_out +set_location_assignment PIN_47 -to vd[2] +set_location_assignment PIN_48 -to vd[0] +set_location_assignment PIN_49 -to vd[7] +set_location_assignment PIN_50 -to vd[1] +set_location_assignment PIN_51 -to vd[6] +set_location_assignment PIN_52 -to n_mreq +set_location_assignment PIN_54 -to n_int +set_location_assignment PIN_55 -to n_nmi +set_location_assignment PIN_56 -to va[14] +set_location_assignment PIN_57 -to n_vrd +set_location_assignment PIN_65 -to va[16] +set_location_assignment PIN_68 -to va[18] +set_location_assignment PIN_69 -to va[15] +set_location_assignment PIN_70 -to va[13] +set_location_assignment PIN_71 -to n_vwr +set_location_assignment PIN_72 -to va[17] +set_location_assignment PIN_73 -to clkcpu +set_location_assignment PIN_74 -to n_wr +set_location_assignment PIN_75 -to n_rd +set_location_assignment PIN_76 -to a[14] +set_location_assignment PIN_77 -to a[15] +set_location_assignment PIN_78 -to a[13] +set_location_assignment PIN_79 -to vd[5] +set_location_assignment PIN_84 -to n_rstcpu +set_location_assignment PIN_85 -to n_m1 +set_location_assignment PIN_86 -to n_rfsh +set_location_assignment PIN_87 -to vd[3] +set_location_assignment PIN_88 -to va[0] +set_location_assignment PIN_89 -to va[1] +set_location_assignment PIN_90 -to va[2] +set_location_assignment PIN_91 -to va[3] +set_location_assignment PIN_92 -to va[4] +set_location_assignment PIN_97 -to va[6] +set_location_assignment PIN_98 -to va[7] +set_location_assignment PIN_99 -to va[8] +set_location_assignment PIN_100 -to va[9] +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP" +set_location_assignment PIN_53 -to n_iorq +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE output/stp1.stp +set_global_assignment -name RTLV_GROUP_RELATED_NODES OFF +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_miso_tape_in +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_iorq +set_location_assignment PIN_10 -to clk_in +set_global_assignment -name SLD_FILE "/home/uzix/zx-sizif-xxs/fpga/rtl/stp2_auto_stripped.stp" +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[0] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[1] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[2] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[4] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[5] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[7] +set_global_assignment -name VERILOG_MACRO "REV_A=" +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/ym2149.sv +set_global_assignment -name VERILOG_FILE ../rtl/vencode_sin_cos.v +set_global_assignment -name VHDL_FILE ../rtl/vencode.vhd +set_global_assignment -name VERILOG_INCLUDE_FILE ../rtl/ps2_codes.vh +set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/mixer.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/soundrive.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/screen.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/ports.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/magic.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/divmmc.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/cpucontrol.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/memcontrol.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/turbosound.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/ulaplus.sv +set_global_assignment -name VERILOG_FILE ../rtl/ps2.v +set_global_assignment -name VERILOG_FILE ../rtl/ps2_rxtx.v +set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/common.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/top.sv +set_global_assignment -name SDC_FILE clocks.sdc +set_global_assignment -name CDF_FILE output/zx_ula.cdf +set_global_assignment -name QIP_FILE ip/pll.qip +set_global_assignment -name QIP_FILE ip/rom2ram.qip +set_global_assignment -name QIP_FILE ip/asmi.qip \ No newline at end of file diff --git a/fpga/syn/zx_ula.qpf b/fpga/syn/zx_ula.qpf index 2dd0842..2338303 100755 --- a/fpga/syn/zx_ula.qpf +++ b/fpga/syn/zx_ula.qpf @@ -1,30 +1,31 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2009 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II -# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition -# Date created = 08:15:12 April 28, 2019 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "9.0" -DATE = "08:15:12 April 28, 2019" - -# Revisions - -PROJECT_REVISION = "zx_ula" +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 32-bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version +# Date created = 20:26:38 November 08, 2021 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "20:26:38 November 08, 2021" + +# Revisions + +PROJECT_REVISION = "rev_A" +PROJECT_REVISION = "rev_B"