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ulaplus.sv: fix indentation

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UzixLS
2021-06-17 21:57:16 +03:00
parent 545b5533bb
commit 695589d6c2
1 changed files with 8 additions and 8 deletions
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16
fpga/rtl/ulaplus.sv
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@ -33,9 +33,9 @@ always @(posedge clk28 or negedge rst_n) begin
end
else begin
if (port_bf3b_cs && bus.wr)
addr_reg <= bus.d_reg;
addr_reg <= bus.d_reg;
if (port_ff3b_cs && bus.wr && addr_reg == 8'b01000000)
active <= bus.d_reg[0];
active <= bus.d_reg[0];
write_req <= {write_req[0], port_ff3b_cs && bus.wr && addr_reg[7:6] == 2'b00};
port_ff3b_rd <= port_ff3b_cs && bus.rd;
@ -74,14 +74,14 @@ endmodule
module ulaplus_ram(q, a, d, we, clk);
output reg [7:0] q;
input [7:0] d;
input [5:0] a;
input we, clk;
reg [7:0] mem [0:63];
output reg [7:0] q;
input [7:0] d;
input [5:0] a;
input we, clk;
reg [7:0] mem [0:63];
always @(posedge clk) begin
if (we)
mem[a] <= d;
q <= mem[a];
end
end
endmodule