uzix/zx-sizif-xxs
1
0
Fork 0
mirror of https://github.com/UzixLS/zx-sizif-xxs.git synced 2025-07-19 07:11:28 +03:00
Code Issues Projects Releases Wiki Activity

update testbench T80

Browse Source
This commit is contained in:
UzixLS
2021-05-26 13:49:01 +03:00
parent 8f84aeb17b
commit 63e499e10e
2 changed files with 30 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
fpga/tb/t80/t80n_mcode.vhd
View File

@ -213,7 +213,7 @@ begin
--Z80N_data_o <= Z80N_data_s;
process (IR, ISet, MCycle, F, NMICycle, IntCycle, ext_Data_i, ext_ACC_i)
process (IR, ISet, MCycle, F, NMICycle, IntCycle, ext_Data_i, ext_ACC_i, XY_State)
variable DDD : std_logic_vector(2 downto 0);
variable SSS : std_logic_vector(2 downto 0);
variable DPair : std_logic_vector(1 downto 0);
@ -829,14 +829,16 @@ begin
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
TStates <= "100";
--TStates <= "100";
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
Z80N_command_o <= NMIACK_MSB;
when 3 =>
TStates <= "100";
--TStates <= "100";
Write <= '1';
Z80N_command_o <= NMIACK_LSB;
when others => null;
end case;
elsif IntCycle = '1' then
@ -2269,7 +2271,7 @@ begin
when "01010110"|"01110110" =>
-- IM 1
IMode <= "01";
when "01011110"|"01110111" =>
when "01011110"|"01111110" =>
-- IM 2
IMode <= "10";
-- 16 bit arithmetic
@ -2377,8 +2379,8 @@ begin
Write <= '1';
when others =>
end case;
when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-- RETI, RETN
when "01001101" =>
-- RETI
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
@ -2393,6 +2395,24 @@ begin
I_RETN <= '1';
when others => null;
end case;
when "01000101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-- RETN
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_TO <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
Z80N_command_o <= RETN_LSB;
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
I_RETN <= '1';
Z80N_command_o <= RETN_MSB;
when others => null;
end case;
when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-- IN r,(C)
MCycles <= "010";

8
fpga/tb/t80/t80n_pack.vhd
View File

@ -62,10 +62,10 @@ library ieee;
use ieee.std_logic_1164.std_logic_vector;
package Z80N_pack is
type Z80N_seq is ( NONE, MMU, NEXTREGW, MUL_DE, ADD_HL_A, ADD_DE_A, ADD_BC_A, SWAPNIB_A, PIXELDN, SET_A_E, PIXELAD, MIRROR_A, PUSH_nn, LDPIRX, ADD_HL_nn , ADD_DE_nn , ADD_BC_nn,
LDIRSCALE,
BSLA_DE_B, BSRA_DE_B, BSRL_DE_B, BSRF_DE_B, BRLC_DE_B,
JP_C);
type Z80N_seq is ( NONE, MMU, NEXTREGW, MUL_DE, ADD_HL_A, ADD_DE_A, ADD_BC_A, SWAPNIB_A,
PIXELDN, SET_A_E, PIXELAD, MIRROR_A, PUSH_nn, LDPIRX, ADD_HL_nn, ADD_DE_nn,
ADD_BC_nn, LDIRSCALE, BSLA_DE_B, BSRA_DE_B, BSRL_DE_B, BSRF_DE_B, BRLC_DE_B,
JP_C, NMIACK_LSB, NMIACK_MSB, RETN_LSB, RETN_MSB );
signal Z80N_seq_s : Z80N_seq;
end package;