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fix #1ffd port decoding

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UzixLS
2022-01-30 15:45:48 +03:00
parent 46f56755df
commit 52bf3711e0
1 changed files with 2 additions and 1 deletions
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3
fpga/rtl/ports.sv
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@ -117,7 +117,8 @@ end
/* PORT #1FFD */ /* PORT #1FFD */
wire port_1ffd_cs = bus.ioreq && bus.a_reg == 16'h1FFD && (machine == MACHINE_S3 || magic_map); wire port_1ffd_cs = bus.ioreq && bus.a_reg[15:12] == 4'b0001 && !bus.a_reg[1] &&
(machine == MACHINE_S3 || magic_map);
always @(posedge clk28 or negedge rst_n) begin always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin if (!rst_n) begin
port_1ffd <= 0; port_1ffd <= 0;