From 52bf3711e0d0dcb1f8af0f7f532d7946fc6fc588 Mon Sep 17 00:00:00 2001
From: UzixLS <uzix.ls@gmail.com>
Date: Sun, 30 Jan 2022 15:45:48 +0300
Subject: [PATCH] fix #1ffd port decoding

---
 fpga/rtl/ports.sv | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/fpga/rtl/ports.sv b/fpga/rtl/ports.sv
index 3c8f7ec..f5b920c 100755
--- a/fpga/rtl/ports.sv
+++ b/fpga/rtl/ports.sv
@@ -117,7 +117,8 @@ end
 
 
 /* PORT #1FFD */
-wire port_1ffd_cs = bus.ioreq && bus.a_reg == 16'h1FFD && (machine == MACHINE_S3 || magic_map);
+wire port_1ffd_cs = bus.ioreq && bus.a_reg[15:12] == 4'b0001 && !bus.a_reg[1] &&
+                    (machine == MACHINE_S3 || magic_map);
 always @(posedge clk28 or negedge rst_n) begin
     if (!rst_n) begin
         port_1ffd <= 0;