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add support for ZC SD card controller; replace NO-OS divmmc mode with ZC

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UzixLS
2022-01-31 21:39:26 +03:00
parent d6a31c0502
commit 456cb97fac
13 changed files with 63 additions and 41 deletions
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1
fpga/rtl/common.sv
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@ -2,7 +2,6 @@ package common;
typedef enum { MACHINE_S48, MACHINE_S128, MACHINE_S3, MACHINE_PENT } machine_t;
typedef enum { TURBO_NONE, TURBO_4, TURBO_5, TURBO_7, TURBO_14 } turbo_t;
typedef enum { PANNING_MONO, PANNING_ABC, PANNING_ACB } panning_t;
typedef enum { DIVMMC_OFF, DIVMMC_ON, DIVMMC_NOOS } divmmc_t;
endpackage

33
fpga/rtl/divmmc.sv
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@ -6,11 +6,13 @@ module divmmc(
input ck7,
input en,
input en_hooks,
input en_zc,
cpu_bus bus,
output [7:0] d_out,
output d_out_active,
input sd_cd,
input sd_miso,
output sd_mosi,
output reg sd_sck,
@ -61,21 +63,20 @@ always @(posedge clk28 or negedge rst_n) begin
end
end
reg spi_rd;
reg conmem, mapram;
wire port_e3_cs = en && bus.ioreq && bus.a_reg[7:0] == 8'hE3;
wire port_e7_cs = en && bus.ioreq && bus.a_reg[7:0] == 8'hE7;
wire port_eb_cs = en && bus.ioreq && bus.a_reg[7:0] == 8'hEB;
wire port_57_cs = en_zc && bus.ioreq && bus.a_reg[7:0] == 8'h57;
wire port_77_cs = en_zc && bus.ioreq && bus.a_reg[7:0] == 8'h77;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
spi_rd <= 0;
page <= 0;
mapram <= 0;
conmem <= 0;
sd_cs <= 1'b1;
end
else begin
spi_rd <= port_eb_cs && bus.rd;
if (port_e3_cs && bus.wr) begin
page <= bus.d_reg[3:0];
mapram <= bus.d_reg[6] | mapram;
@ -84,6 +85,22 @@ always @(posedge clk28 or negedge rst_n) begin
if (port_e7_cs && bus.wr) begin
sd_cs <= bus.d_reg[0];
end
else if (port_77_cs && bus.wr) begin
sd_cs <= bus.d_reg[1] | ~bus.d_reg[0];
end
end
end
reg spi_rd, zc_rd;
wire [7:0] zc_data = {7'b0000000, sd_cd};
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
spi_rd <= 0;
zc_rd <= 0;
end
else begin
spi_rd <= (port_eb_cs || port_57_cs) && bus.rd;
zc_rd <= port_77_cs && bus.rd;
end
end
@ -93,7 +110,7 @@ assign cpuwait = ~spi_cnt[3];
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n)
spi_cnt <= 0;
else if (port_eb_cs && (bus.rd || bus.wr))
else if ((port_eb_cs || port_57_cs) && (bus.rd || bus.wr))
spi_cnt <= 4'b1110;
else if (spi_cnt_en && ck7)
spi_cnt <= spi_cnt + 1'b1;
@ -103,7 +120,7 @@ reg spi_mosi_en;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n)
spi_mosi_en <= 0;
else if (port_eb_cs && bus.wr)
else if ((port_eb_cs || port_57_cs) && bus.wr)
spi_mosi_en <= 1'b1;
else if (!spi_cnt_en)
spi_mosi_en <= 0;
@ -114,7 +131,7 @@ assign sd_mosi = spi_mosi_en? spi_reg[7] : 1'b1;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n)
spi_reg <= 0;
else if (port_eb_cs && bus.wr)
else if ((port_eb_cs || port_57_cs) && bus.wr)
spi_reg <= bus.d_reg;
else if (spi_cnt[3] == 1'b0 && ck7)
spi_reg[7:0] <= {spi_reg[6:0], sd_miso};
@ -136,7 +153,7 @@ assign ramwr_mask =
(!bus.a[13] || page == 4'b0011) &&
!conmem && automap && mapram;
assign d_out_active = spi_rd;
assign d_out = spi_reg;
assign d_out_active = zc_rd | spi_rd;
assign d_out = zc_rd? zc_data : spi_reg;
endmodule

11
fpga/rtl/magic.sv
View File

@ -13,7 +13,6 @@ module magic(
input magic_button,
input pause_button,
input sd_cd,
input div_automap,
output reg magic_mode,
@ -25,7 +24,8 @@ module magic(
output turbo_t turbo,
output panning_t panning,
output reg joy_sinclair,
output divmmc_t divmmc_en,
output reg divmmc_en,
output reg zc_en,
output reg ulaplus_en,
output reg ay_en,
output reg covox_en,
@ -80,7 +80,8 @@ always @(posedge clk28 or negedge rst_n) begin
turbo <= TURBO_NONE;
panning <= PANNING_ABC;
joy_sinclair <= 0;
divmmc_en <= DIVMMC_NOOS;
divmmc_en <= 0;
zc_en <= 1'b1;
ulaplus_en <= 1'b1;
ay_en <= 1'b1;
covox_en <= 1'b1;
@ -93,14 +94,14 @@ always @(posedge clk28 or negedge rst_n) begin
8'h04: panning <= panning_t'(bus.d_reg[1:0]);
8'h07: joy_sinclair <= bus.d_reg[0];
8'h08: ay_en <= bus.d_reg[0];
8'h09: divmmc_en <= divmmc_t'(bus.d_reg[1:0]);
8'h09: {zc_en, divmmc_en} <= bus.d_reg[1:0];
8'h0a: ulaplus_en <= bus.d_reg[0];
8'h0b: {soundrive_en, covox_en} <= bus.d_reg[1:0];
endcase
end
reg config_rd;
wire [7:0] config_data = {4'b0000, div_automap, sd_cd, pause_button, magic_button};
wire [7:0] config_data = {4'b0000, div_automap, 1'b1, pause_button, magic_button};
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n)
config_rd <= 0;

15
fpga/rtl/top.sv
View File

@ -234,7 +234,8 @@ wire magic_dout_active;
wire magic_mode, magic_map;
wire joy_sinclair, up_en, ay_en, covox_en, soundrive_en;
panning_t panning;
divmmc_t divmmc_en;
wire divmmc_en, zc_en;
magic magic0(
.rst_n(n_rstcpu),
.clk28(clk28),
@ -249,7 +250,6 @@ magic magic0(
.magic_button(ps2_key_magic),
.pause_button(ps2_key_pause),
.sd_cd(sd_cd),
.div_automap(div_automap),
.magic_mode(magic_mode),
@ -262,6 +262,7 @@ magic magic0(
.joy_sinclair(joy_sinclair),
.panning(panning),
.divmmc_en(divmmc_en),
.zc_en(zc_en),
.ulaplus_en(up_en),
.ay_en(ay_en),
.covox_en(covox_en),
@ -387,13 +388,15 @@ divmmc divmmc0(
.clk28(clk28),
.ck14(ck14),
.ck7(ck7),
.en(divmmc_en == DIVMMC_ON || divmmc_en == DIVMMC_NOOS),
.en_hooks(divmmc_en == DIVMMC_ON),
.en(divmmc_en),
.en_hooks(divmmc_en),
.en_zc(zc_en),
.bus(bus),
.d_out(div_dout),
.d_out_active(div_dout_active),
.sd_cd(sd_cd),
.sd_miso(sd_miso_tape_in),
.sd_mosi(sd_mosi0),
.sd_sck(sd_sck),
@ -410,7 +413,7 @@ divmmc divmmc0(
.ramwr_mask(div_ramwr_mask),
.cpuwait(div_wait)
);
assign sd_mosi_tape_out = (divmmc_en == DIVMMC_OFF)? tape_out : sd_mosi0;
assign sd_mosi_tape_out = (!divmmc_en && !zc_en)? tape_out : sd_mosi0;
/* ULAPLUS */
@ -498,7 +501,7 @@ memcontrol memcontrol0(
.port_1ffd(port_1ffd),
.port_dffd(port_dffd),
.rampage_ext(rampage_ext),
.divmmc_en(divmmc_en != DIVMMC_OFF),
.divmmc_en(divmmc_en),
.div_ram(div_ram),
.div_map(div_map),
.div_ramwr_mask(div_ramwr_mask),