From 3a086ac5e5f5010561d6ed6b3c79515cd95e9d92 Mon Sep 17 00:00:00 2001
From: Eugene Lozovoy <uzix.ls@gmail.com>
Date: Tue, 9 Aug 2022 12:48:53 +0300
Subject: [PATCH] improve turbo modes reliability

---
 fpga/rtl/divmmc.sv     | 14 +++++++++----
 fpga/rtl/magic.sv      | 16 ++++++++------
 fpga/rtl/memcontrol.sv |  2 +-
 fpga/rtl/top.sv        |  2 +-
 fpga/tb/rom.asm        | 47 +++++++++++++++++++++++++++++++-----------
 5 files changed, 57 insertions(+), 24 deletions(-)

diff --git a/fpga/rtl/divmmc.sv b/fpga/rtl/divmmc.sv
index e360e0d..964a2a2 100755
--- a/fpga/rtl/divmmc.sv
+++ b/fpga/rtl/divmmc.sv
@@ -24,17 +24,19 @@ module divmmc(
 
     output reg [3:0] page,
     output map,
-    output reg automap,
+    output automap,
     output ram,
     output ramwr_mask,
     output cpuwait
 );
 
+
+reg automap0;
 reg automap_next;
 always @(posedge clk28 or negedge rst_n) begin
     if (!rst_n) begin
         automap_next <= 0;
-        automap <= 0;
+        automap0 <= 0;
     end
     else if (bus.m1 && bus.memreq && !magic_map) begin
         if (!en_hooks || !en || rammap) begin
@@ -55,14 +57,18 @@ always @(posedge clk28 or negedge rst_n) begin
         end
         else if (bus.a_reg[15:8] == 8'h3D) begin // tr-dos mapping area
             automap_next <= 1'b1;
-            automap <= 1'b1;
+            automap0 <= 1'b1;
         end
     end
     else if (!bus.m1) begin
-        automap <= automap_next;
+        automap0 <= automap_next;
     end
 end
 
+// #3Dxx entrypoint is critical for timings, so we're arming 'map' signal as soon as possible
+assign automap = automap0 || (bus.m1 && bus.memreq && !magic_map && en_hooks && en && !rammap && bus.a_reg[15:8] == 8'h3D);
+
+
 reg conmem, mapram;
 wire port_e3_cs = en && bus.ioreq && bus.a_reg[7:0] == 8'hE3;
 wire port_e7_cs = en && bus.ioreq && bus.a_reg[7:0] == 8'hE7;
diff --git a/fpga/rtl/magic.sv b/fpga/rtl/magic.sv
index f280da4..3f12a51 100755
--- a/fpga/rtl/magic.sv
+++ b/fpga/rtl/magic.sv
@@ -16,7 +16,7 @@ module magic(
     input div_automap,
 
     output reg magic_mode,
-    output reg magic_map,
+    output magic_map,
 
     output reg magic_reboot,
     output reg magic_beeper,
@@ -34,11 +34,12 @@ module magic(
 
 reg magic_unmap_next;
 reg magic_map_next;
+reg magic_map0;
 always @(posedge clk28 or negedge rst_n) begin
     if (!rst_n) begin
         n_nmi <= 1'b1;
         magic_mode <= 1'b1;
-        magic_map <= 1'b1;
+        magic_map0 <= 1'b1;
         magic_map_next <= 0;
         magic_unmap_next <= 0;
     end
@@ -49,26 +50,29 @@ always @(posedge clk28 or negedge rst_n) begin
             magic_mode <= 1'b1;
         end
 
-        if (magic_map && bus.memreq && bus.rd && bus.a_reg == 16'hf000 && !magic_map_next) begin
+        if (magic_map0 && bus.memreq && bus.rd && bus.a_reg == 16'hf000 && !magic_map_next) begin
             magic_unmap_next <= 1'b1;
             magic_mode <= 1'b0;
         end
-        else if (magic_map && bus.memreq && bus.rd && bus.a_reg == 16'hf008) begin
+        else if (magic_map0 && bus.memreq && bus.rd && bus.a_reg == 16'hf008) begin
             magic_unmap_next <= 1'b1;
             magic_map_next <= 1'b1;
         end
         else if (magic_unmap_next && !bus.memreq) begin
-            magic_map <= 1'b0;
+            magic_map0 <= 1'b0;
             magic_unmap_next <= 1'b0;
         end
         else if (magic_mode && bus.m1 && bus.memreq && (bus.a_reg == 16'h0066 || magic_map_next)) begin
             n_nmi <= 1'b1;
-            magic_map <= 1'b1;
+            magic_map0 <= 1'b1;
             magic_map_next <= 1'b0;
         end
     end
 end
 
+// this signal is critical for timings, so we're arming it as soon as possible
+assign magic_map = magic_map0 || (magic_mode && bus.m1 && bus.memreq && (bus.a_reg == 16'h0066 || magic_map_next) && !magic_unmap_next);
+
 
 /* MAGIC CONFIG */
 wire config_cs = magic_map && bus.ioreq && bus.a_reg[7:0] == 8'hFF;
diff --git a/fpga/rtl/memcontrol.sv b/fpga/rtl/memcontrol.sv
index feec9c5..ab6a347 100644
--- a/fpga/rtl/memcontrol.sv
+++ b/fpga/rtl/memcontrol.sv
@@ -52,7 +52,7 @@ module memcontrol(
 
 reg romreq, ramreq, ramreq_wr;
 reg [18:13] va_18_13;
-always @(posedge clk28) begin
+always @(negedge clk28) begin
     romreq =  bus.mreq && bus.a[15:14] == 2'b00 &&
         (magic_map || (!div_ram && div_map) || (!div_ram && !port_dffd[4] && !port_1ffd[0]));
     ramreq = bus.mreq && !romreq;
diff --git a/fpga/rtl/top.sv b/fpga/rtl/top.sv
index 37e69f7..c24cab6 100755
--- a/fpga/rtl/top.sv
+++ b/fpga/rtl/top.sv
@@ -214,7 +214,7 @@ cpucontrol cpucontrol0(
     .machine(machine),
     .screen_contention(screen_contention),
     .turbo(turbo),
-    .ext_wait_cycle(div_wait || up_active),
+    .ext_wait_cycle(div_wait),
     .init_done_in(init_done),
 
     .n_rstcpu(n_rstcpu),
diff --git a/fpga/tb/rom.asm b/fpga/tb/rom.asm
index 6b54a52..d9eaab5 100644
--- a/fpga/tb/rom.asm
+++ b/fpga/tb/rom.asm
@@ -1,20 +1,22 @@
     DEVICE ZXSPECTRUM48
 
-    ORG #8000 // mapped #0000
+    ORG #0000
 Start:
     nop
-    jp #1000
+    jp Main
 
-    ORG #8038
+    ORG #0038
 Int1:
 	reti
 
-    ORG #8066
+    ORG #0066
 Nmi:
     retn
 
-    ORG #9000
+    ORG #1000
 Main:
+    jp #3D00
+
     im 2
     ei
 
@@ -35,23 +37,44 @@ Main:
     //ld b, #ff
     //ld hl, #4000
     //otir
-
-    jp #1fff
 Loop:
     halt
     jr Loop
 
 
-    ORG #C000 // mapped #0000
+    ORG #8000 // mapped #0000
+MagicROM_Start:
+    ld bc, #09ff ; divmmc = 1
+    ld a, 1      ; ...
+    out (c), a   ; ...
+    ld bc, #03ff ; cpu freq = 7mhz
+    ld a, 3      ; ...
+    out (c), a   ; ...
+    ld bc, #0000
+    push bc
+    jp #f008
+    ORG #F000
+MagicROM_ExitVector:
+    ret
+    ORG #F008
+MagicROM_ReadoutVector:
+    nop
+    ret
+
+    ORG #A000 // mapped #0000
 DivROM_Start:
     nop
-    ld bc, #3D00
+    ld bc, #1000
     push bc
     jp #1FFF
-    ORG #DFFF // mapped #1FFF
-    nop
+    ORG #BFFF // mapped #1FFF
+DivROM_ExitVector:
+    ret
     ORG #1D00 // mapped #3D00
-    jp #0000
+DivROM_EnterVector_TRDOS:
+    ld bc, #1000
+    push bc
+    jp #1FFF
 
 
     SAVEBIN "rom.bin",0,65536