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fpga: some minor refactors

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UzixLS
2022-01-30 15:54:41 +03:00
parent 8af0274e87
commit 391a0b32bf
5 changed files with 22 additions and 29 deletions
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6
fpga/rtl/magic.sv
View File

@ -28,7 +28,7 @@ module magic(
output divmmc_t divmmc_en,
output reg ulaplus_en,
output reg covox_en,
output reg sd_en
output reg soundrive_en
);
reg magic_unmap_next;
@ -82,7 +82,7 @@ always @(posedge clk28 or negedge rst_n) begin
divmmc_en <= DIVMMC_NOOS;
ulaplus_en <= 1'b1;
covox_en <= 1'b1;
sd_en <= 1'b1;
soundrive_en <= 1'b1;
end
else if (config_cs && bus.wr) case (bus.a_reg[15:8])
8'h00: magic_reboot <= bus.d_reg[0];
@ -93,7 +93,7 @@ always @(posedge clk28 or negedge rst_n) begin
8'h07: joy_sinclair <= bus.d_reg[0];
8'h09: divmmc_en <= divmmc_t'(bus.d_reg[1:0]);
8'h0a: ulaplus_en <= bus.d_reg[0];
8'h0b: {sd_en, covox_en} <= bus.d_reg[1:0];
8'h0b: {soundrive_en, covox_en} <= bus.d_reg[1:0];
endcase
end

20
fpga/rtl/memcontrol.sv
View File

@ -1,7 +1,6 @@
import common::*;
module memcontrol(
input rst_n,
input clk28,
cpu_bus bus,
output [18:0] va,
@ -45,25 +44,18 @@ module memcontrol(
/* MEMORY CONTROLLER */
reg romreq, ramreq, ramreq_wr;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
romreq = 1'b0;
ramreq = 1'b0;
ramreq_wr = 1'b0;
end
else begin
romreq = bus.mreq && !bus.rfsh && bus.a[14] == 0 && bus.a[15] == 0 &&
(magic_map || (!div_ram && div_map) || (!div_ram && !port_dffd[4] && !port_1ffd[0]));
ramreq = bus.mreq && !bus.rfsh && !romreq;
ramreq_wr = ramreq && bus.wr && div_ramwr_mask == 0;
end
always @(posedge clk28) begin
romreq = bus.mreq && !bus.rfsh && bus.a[14] == 0 && bus.a[15] == 0 &&
(magic_map || (!div_ram && div_map) || (!div_ram && !port_dffd[4] && !port_1ffd[0]));
ramreq = bus.mreq && !bus.rfsh && !romreq;
ramreq_wr = ramreq && bus.wr && div_ramwr_mask == 0;
end
assign n_vrd = ((((ramreq || romreq) && bus.rd) || screen_fetch) && !rom2ram_ram_wren)? 1'b0 : 1'b1;
assign n_vwr = ((ramreq_wr && bus.wr && !screen_fetch) || rom2ram_ram_wren)? 1'b0 : 1'b1;
/* VA[18:13] map
* 00xxxx 128Kb of roms
* 00xxxx 112Kb of roms
* 00111x 16Kb of magic ram
* 01xxxx 128Kb of divmmc memory
* 10xxxx 128Kb of extended ram (via port dffd)

7
fpga/rtl/ports.sv
View File

@ -82,10 +82,11 @@ end
/* PORT #7FFD */
reg lock_7ffd;
wire port_7ffd_cs = bus.ioreq && bus.a_reg[1] == 0 && bus.a_reg[15] == 0 &&
(bus.a_reg[14] == 1'b1 || (!magic_map && machine != MACHINE_S3)) &&
(machine != MACHINE_S48 || magic_map);
reg lock_7ffd;
(machine != MACHINE_S48 || magic_map) &&
(lock_7ffd == 0 || port_dffd[4] == 1'b1);
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
rampage128 <= 0;
@ -93,7 +94,7 @@ always @(posedge clk28 or negedge rst_n) begin
rompage128 <= 0;
lock_7ffd <= 0;
end
else if (port_7ffd_cs && bus.wr && (lock_7ffd == 0 || port_dffd[4] == 1'b1)) begin
else if (port_7ffd_cs && bus.wr) begin
rampage128 <= bus.d_reg[2:0];
screenpage <= bus.d_reg[3];
rompage128 <= bus.d_reg[4];

8
fpga/rtl/top.sv
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@ -232,7 +232,7 @@ wire div_automap;
wire [7:0] magic_dout;
wire magic_dout_active;
wire magic_mode, magic_map;
wire joy_sinclair, up_en, covox_en, sd_en;
wire joy_sinclair, up_en, covox_en, soundrive_en;
panning_t panning;
divmmc_t divmmc_en;
magic magic0(
@ -264,7 +264,7 @@ magic magic0(
.divmmc_en(divmmc_en),
.ulaplus_en(up_en),
.covox_en(covox_en),
.sd_en(sd_en)
.soundrive_en(soundrive_en)
);
@ -338,7 +338,7 @@ soundrive soundrive0(
.rst_n(usrrst_n),
.clk28(clk28),
.en_covox(covox_en),
.en_soundrive(sd_en),
.en_soundrive(soundrive_en),
.bus(bus),
@ -348,6 +348,7 @@ soundrive soundrive0(
.ch_r1(soundrive_r1)
);
/* SOUND MIXER */
mixer mixer0(
.rst_n(usrrst_n),
@ -478,7 +479,6 @@ asmi asmi0(
/* MEMORY CONTROLLER */
memcontrol memcontrol0(
.rst_n(rst_n),
.clk28(clk28),
.bus(bus),
.va(va),

8
fpga/rtl/turbosound.sv
View File

@ -24,8 +24,8 @@ reg ay_bc1;
reg ay_sel;
wire ay_rd0 = bus.rd && ay_bc1 == 1'b1 && ay_bdir == 1'b0 && ay_sel == 1'b0;
wire ay_rd1 = bus.rd && ay_bc1 == 1'b1 && ay_bdir == 1'b0 && ay_sel == 1'b1;
wire port_bffd = bus.ioreq && bus.a_reg[15] == 1'b1 && bus.a_reg[1] == 0;
wire port_fffd = bus.ioreq && bus.a_reg[15] == 1'b1 && bus.a_reg[14] == 1'b1 && bus.a_reg[1] == 0;
wire port_bffd = en && bus.ioreq && bus.a_reg[15] == 1'b1 && bus.a_reg[1] == 0;
wire port_fffd = en && bus.ioreq && bus.a_reg[15] == 1'b1 && bus.a_reg[14] == 1'b1 && bus.a_reg[1] == 0;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
ay_bc1 <= 0;
@ -33,8 +33,8 @@ always @(posedge clk28 or negedge rst_n) begin
ay_sel <= 0;
end
else begin
ay_bc1 <= en && port_fffd;
ay_bdir <= en && port_bffd && bus.wr;
ay_bc1 <= port_fffd;
ay_bdir <= port_bffd && bus.wr;
if (!en_ts)
ay_sel <= 0;
else if (bus.ioreq && port_fffd && bus.wr && bus.d_reg[7:3] == 5'b11111)